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Mark Apton | 1 Feb 2012 01:30
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Sr. SI Engineer (Backplane Architect) needed at Huawei in Santa Clara, CA;

My Team is looking for a Senior Staff Engineer(Backplane
Architect)/Principle Engineer;
Responsibilities/Descriptions

Responsible for providing the backplane architecture and 10G+ High Speed SI
solutions for Next Generation telecommunications equipment in the router,
switch and transmission product lines to meet system design requirements.
Experience in co-designing of ASIC, Package, PCB and System interconnects
desired. including:

-     Design and analysis of multi-gigabit serial links for Backplane and
chip-to-chip interfaces meeting CEI, XFI, XLAUI, SFI, 10Gbase-KR, PCIe, and
other standards.

-     Familiar with ASIC, Hardware, interconnect teams to evaluate design
tradeoffs and optimize design performance / risk / cost /manufacturability.

-     To evaluate package designs, characterization of SerDes, and design
experiments to do the same.

-     Modeling of electromagnetic 3-D structures.

-     Modeling and analyzing power delivery networks (PDN).

-     Familiar with memory technologies such as DDR2/DDR3 is preferred.

Qualifications/Requirements:

-     Performing physical measurements to collect data for design
validation and simulation correlations.
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Xu Shuai | 1 Feb 2012 02:09

答复: [SI-LIST] Why remove the power/gnd plane area between the I/O connector and transformer/filter?

Hi,

I think the power plane in that region should be removed.

But removing all the GND plane in that region may result in EMI problem.
Trace without reference is easy to pick up the noise inside the enclosure. 

Removing the GND plane just below the transformer is not necessary and I
have not seen any evidence.

Sometimes it is better to split the GND into digital GND and chassis GND.

Shuai
-----邮件原件-----
发件人: si-list-bounce@... [mailto:si-list-bounce <at> freelists.org]
代表 Shao, Peng
发送时间: 2012年1月31日 17:36
收件人: si-list@...
主题: [SI-LIST] Why remove the power/gnd plane area between the I/O
connector and transformer/filter?

Experts,
You may know that there is a traditional layout rule for out-board I/O
signals. The power/gnd plane area between I/O transformer/filter and
connector should be removed for EMI/ESD consideration.
I cannot understand why we need to do that or the function to improve
EMI/ESD. Could you please give out your opinion? Thanks.
( To get high impedance trace? )

Peng, Shao   SI Engineer
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David A Mullenex | 1 Feb 2012 07:40
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Re: RT5880 question

Greetings Luciano,

Looks like you are butting up against the minimum order quantity (MoQ) and possibly panelization issue.

The MoQ can be described more accurately as the minimum order in terms of minimal payment a specific fab
supplier requires for them to come out ahead on a small build.

Let's say your fab supplier of choice deals with orders of no less than $2000.00 (translate to local
currency as appropriate).  Then if your PCB would cost $10.00, and you want 2 or 200, You will still be
charged $2000.00. Well, mostly as there is some dependency on yields the Fab house can get on your design
and what tollerances you set/accept.

At a basic level, the minimum cost is not only a function of the PCB fab materials. There is design and line
setup time, line processing time, analysis, production labor, tooling, test coverage (if specified),
programming, processing materials, aspect ratios for drills, projected yields, etc., etc.,

I am not on the Manufacturing side but rather from the high-speed complex System / Board / FPGA definition
and design side, where we tend to pick these aspects up as customers. I expect that some hard core
manufacturing experts on this list can give you as much further details as you require on what goes into the
MoQ.  

BTW, any capable and reputable fab supplier will walk you through this as well. Different fan suppliers
have different MoQs.

Simply ask your supplier about their MoQ, their planned panelization and then as to how flexible they are on
this if you are a repeat customer.

Best Regards,
- David.
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Albert Ruehli | 1 Feb 2012 13:23
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Request for help

How're you doing and I trust that I find you in good health. I'm really
sorry to reach out to you this manner and I'm sorry for not informing you
about my urgent trip to Scotland. I am here for a Seminar and to complete a
project. Presently, I will be glad if I could confide in you and I want
this issue to be confidential between You and I because I don't want people
to get worried about my situation.
Everything was fine until I got robbed on my way back to the hotel and I
lost my Wallet, mobile phone and some valuables during this incident. I had
to block my account and bank cards immediately the incident happened. I am
facing a hard time here because I have no money on me to clear Hotel bills
and some expenses. I'm sending you this message to inform you that am
stranded at the moment and need your help with a loan of $3350 to pay up
the bills and make arrangements to get back home.

Am sorry for the inconvenience this message might cause you but please
understand that am in a very bad situation right now and would appreciate
if you could help me out.

Thanks in advance, Best regards,   Albert

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hrzhu | 1 Feb 2012 16:43
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EMI radation measurement

Hi experts,
I want to measure the EMI radiation in the anechoic chamber. The setup of the measurement  is as follows: the
test board is put on the table to receive the signal and measured by spectrum analyzer. The RF signal
generated by the signal source is launched into the horn antenna. 

We want to measure the maximum radiated E-field in accordance with the sweep frequency. However, the
measurement setup just only operate at each excited frequency point? So, I wonder how can I to solve it and
how to get the maximum E-field?

Thanks a lot~

Vincent, Zhu

2012-02-01 

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Pehr Andersson | 1 Feb 2012 18:17
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Difference between coupling and crosstalk

Hello experts!

What is the difference between coupling and crosstalk?

* Crosstalk is dependent on the bit pattern. ?
* Coupling is not dependent on the bit pattern. ?

Can we then use coupling in frequency domain to get crosstalk, if the
crosstalk is time-domain phenomena, that is, it is dependent on the
bit pattern?

For example if we want to estimate how much crosstalk we will receive
on the victim line when having two aggressors with rise time 24ps and
bit rate 10G, then we could use PSFEXT and PSNEXT for estimating FEXT
and NEXT crosstalk.
But will it tell me how much crosstalk I can expect, or how much it
will close my eye?

Thanks and best regards, Pelle
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Dudi Tash | 1 Feb 2012 18:28
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Re: Difference between coupling and crosstalk

Hi Pelle,

Coupling is the mechanism that causes the crosstalk.

There are two of those mechanisms. The first is capacitive coupling and the second is inductive coupling.

The stronger the coupling, the stronger is the crosstalk, hence the incentive should be reducing the
coupling mechanisms.

In order to do that:

1. Separate the air gap between two (or more) adjacent traces
2. Reduce the distance between GND plane and trace signal (meaning reducing the controlled impedance)
3. Use slower (higher rise time) technologies as possible
4. Reduce the delta V of the signals as possible
5. Use differential pairs if possible

Hope this helps

Best Regards,
Dgtronix Ltd. I Founder & CEO I Dudi Tash 
eFax: +972-3-7256490 I Mobile: +972-54-6345629 I Office: +972-9-9660967
www.dgtronix-tech.com

*This email contains confidential and proprietary information of Dgtronix Ltd.*

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[mailto:si-list-bounce@...] On Behalf Of Pehr Andersson
Sent: Wednesday, February 01, 2012 7:17 PM
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Bond, David | 1 Feb 2012 19:39
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EMI, Package design and FPGA pinouts

Hello SI Experts,
Can anyone point me to a good reference which deals with how to minimize
EMI thru silicon package design?   (i.e. not box design...)

Specifically, the areas of concern are that I have a large-ish silicon
die with a core clock speed >500MHz with many differential I/Os running
at 10Gbps in a flip-chip BGA (probably a 3-2-3 stackup).  My customer is
very concerned about the EMI of this device.  I'm looking for ways which
can minimize the EMI.  I've heard that the use of a grounded metal lid
is helpful; and that placing a ring of ground balls on the outer ring of
the package is helpful.  But these seem to be more qualitative answers
than quantitative.

Any pointers or suggestions would be much appreciated.

Thanks in advance,

-david.

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Sen Velmurugan | 1 Feb 2012 23:33
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Re: Why remove the power/gnd plane area between the I/O connector and transformer/filter?


Removing Digital GND plane under LAN transformers will be 
beneficial,especially when there are more ports. The signal propagation 
is current flow in the transformer line side coils thru few inches of 
trace and LAN cable, so why Digital GND or any reference on I/O side ? 
Higher inter pair trace gap for longer length of trace is recommended. 
Also, it is better not to bring lot of chassis GND area to inside of the 
PCB to minimize ESD energy getting inside the Faraday cage.
Sen
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Shao, Peng | 2 Feb 2012 04:18
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Re: Why remove the power/gnd plane area between the I/O connector and transformer/filter?

Hi, Sen
Thanks for your and all the other's input.
For this question, I think the summary should be:
1. It is unnecessary to put any power/gnd/chassis plane for signal trace in this area;
2. For ESD consideration, minimizing the energy getting inside PCB, no chassis plane neither;
3. For noise propagation consideration, it is better to remove the digital power/plane in this area;
Right? 

Shaopeng

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Sen Velmurugan
Sent: 2012年2月2日 6:34

To: si-list@...
Subject: [SI-LIST] Re: Why remove the power/gnd plane area between the I/O connector and transformer/filter?

Removing Digital GND plane under LAN transformers will be beneficial,especially when there are more
ports. The signal propagation is current flow in the transformer line side coils thru few inches of trace
and LAN cable, so why Digital GND or any reference on I/O side ? 
Higher inter pair trace gap for longer length of trace is recommended. 
Also, it is better not to bring lot of chassis GND area to inside of the PCB to minimize ESD energy getting
inside the Faraday cage.
Sen
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