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Bill Grenoble | 1 Dec 2011 01:34
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Re: Current Sense Resistor Measurement

Hello,
  DC-DC converter with a fuse. This sounds like ULF work, around 50-60 Hz. 
Put away the 10 GHz scope and connect a digital VOM across the resistor. 
That will give you some idea of the current. Size your resistor  to 
produce less than a 1 volt drop. If you don't know what the current is 
going in to the DC-DC converter, take the fuse off and set your VOM to 
amps. Now you know the average current.
   IF you want to see the pretty waveforms that the DC-DC converter cooks 
up for you, put your .1 ohm resistor back, use a two channel scope with 
1X probes, turn off any termination in the 'scope, and connect the 
probes to either side of the resistor. Use a general purpose scope, like 
the Tektronix "lunch box" scope. Set the Y display to A-B, make sure 
both channels are set to the same voltage range.
   If you are going to do the differential scope trick, hook both probes 
to the calibrator, and adjust the gain until the line goes flat. Use 
identical probes (natch!). If you are working  above a MHz, use 10x 
probes and adjust them with the calibrator. Then invert B, and adjust 
until the signal goes away. Watch for funny stuff around the vertical 
edges of the 1000 Hz square wave. Now hook your 'scope across the 
resistor and see what you get.
   If you are looking for RF, get your expensive scope out. Get a high 
frequency bead or toroid, put a wire through the hole and replace the 
fuse with the wire. put another wire through the toroid and connect it 
to your 'scope. Look at the wire with the terminator off, then on. Also 
watch the rest of the unit to see if the toroid is causing trouble.
   When you know the current going into the DC-DC converter, the power 
rating of the resistor is I*I*R . (Sorry, no superscript on this 
machine.) In picking the resistance, size it so that the voltage drop is 
less than 5% of the input voltage. Grab your trusty VOM and measure the 
voltages, just in case the problem you are investigating is caused by
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WANG Zhenwei | 1 Dec 2011 03:13
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what level of overshoot is acceptalbe

Hi guys,
         I have a problem: what level of overshoot is acceptable? I was
ordered to qualify a new nand flash on my project. There are an signal
integrity measurement on overshooting. Some info form spec of nand:

1. power supply:3.3V, so the ideal logic high is 3.3V. 

2. max power : 3.6V

3. Input High Voltage VIH:  2.0~ VCC +0.3;  Input Low Voltage VIL,
-0.3~0.8

3. NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +
0.4V for durations of 20 ns or less.

         So my formula is :

         The max acceptable overshoot=(max power + 0.4V )/( ideal logic
high )=(3.6V + 0.4V)/3.3V!%.

        Am I right?

BR

Zhenwei Wang

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ERIK KUNDRO | 1 Dec 2011 03:50
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Re: what level of overshoot is acceptalbe

Hello,
I think you are over thinking the problem. The spec says max overshoot is vcc+ 0.4V for 20ns or less. Vcc being
the actual Vcc the part is seeing at the moment of overshoot... NOT the max the part can tolerate. 

So, if your Vcc at the part is 3.3V, then the max overshoot your can tolerate is 3.3V+0.4V=3.7V. For 20ns or
less. The instant you cross the 3.7V threshold, you violate the spec... not matter how brief.

If your Vcc at the part is 3.4V, then the max overshoot your can tolerate is 3.4V+0.4V=3.8V. For 20ns or
less.The instant you cross the 3.8V threshold, you violate the spec... not matter how brief.

If your Vcc at the part is 3.0V, then the max overshoot your can tolerate is 3.0V+0.4V=3.4V. For 20ns or
less.The instant you cross the 3.4V threshold, you violate the spec... not matter how brief.

Call the manufacturer of the part for clarification if you are not sure how to interpret this. An FAE should
be able to get you the answer.  

Erik M. Kundro

--- On Wed, 11/30/11, WANG Zhenwei
<Zhenwei.Wang@...> wrote:

From: WANG Zhenwei <Zhenwei.Wang@...>
Subject: [SI-LIST] what level of overshoot is acceptalbe
To: si-list@...
Date: Wednesday, November 30, 2011, 8:13 PM

Hi guys,
         I have a problem: what level of overshoot is acceptable? I was
ordered to qualify a new nand flash on my project. There are an signal
integrity measurement on overshooting. Some info form spec of nand:
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Tom Dagostino | 1 Dec 2011 03:51

Re: what level of overshoot is acceptable

Zhenwei

The max input spec is not 3.6V + 0.4V it is the present Vcc plus 0.4V.  The
spec is trying to tell you not to turn on the clamp diode.  The clamp diode
is referenced to Vcc and not allowing the voltage to go greater than 0.4V
above Vcc will keep the clamp diode off.

Tom Dagostino

Teraspeed Labs
9999 SW Wilshire St.
Suite 102
Portland, OR 97225
USA

971-279-5325  Office
971-279-5326   FAX
503-430-1065  Cell

tom@... 
www.teraspeed.com 

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

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From: si-list-bounce@...
[mailto:si-list-bounce@...] On
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WANG Zhenwei | 1 Dec 2011 05:51
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Re: what level of overshoot is acceptalbe

Hi Rrik,
    thanks for quick response. if i am not misunderstanding you description, the acceptable overshoot is less
than 0.4V/vcc, which is 0.4v/3.3v% in my project. am i right? 

BR

Zhenwei Wang

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T: +86 21 6182 4420

M: +86 13671886168

Zhenwei.Wang@...

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From: ERIK KUNDRO [mailto:kundro85@...] 
Sent: 2011Äê12ÔÂ1ÈÕ 10:50
To: si-list@...; WANG Zhenwei
Subject: Re: [SI-LIST] what level of overshoot is acceptalbe

Hello,
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Yuriy Shlepnev | 1 Dec 2011 06:37
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Re: surface roughness

Femi,

I totally agree with you on need of further research in the roughness
characterization. That is exactly why we are discussing the problem here at
SI LIST and at the conferences focused on SI analysis, such as DesignCon.
Professor Huray's and your research results are very important for
understanding of the roughness characterization. If Huray's model works, it
should be available in a software for advanced signal integrity analysis - I
do not see any problem with that. Due to the simplicity of the final
equations, it will probably be in any SI analysis tool very soon. Though,
there are some question. 
Can Huray's model be used for any type of rough conductor surface? 
If not - how to distinguish. If yes, why surfaces that do not look like
pyramids of snowballs by any imagination can be still modeled with that
particular approximation?
Is there a procedure to find parameters of the model for a given surface
micro-structure  - ball radius, base size and number of balls (assuming that
we have equipment to get the details of a surface)?
Why Huray model does not explain the capacitive effect of roughness?
Are there any other models that we have to consider in the signal integrity
software?

A few words in defense of Hammerstad model. First of all, it is physics
based - Morgan's model is physical. A fit to a modeled data can be
considered an empirical macro-model. Morgan investigated just a few profiles
with the common increase in length along the surface equal 2 - that where
the main restriction came from. The shape of the surface had minor effect -
here is a commonality with your conclusion on independence of absorption
from actual geometry of piled balls. Hammerstad coefficient simply describes
increase in attenuation due to transition from regular skin-effect without
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ERIK KUNDRO | 1 Dec 2011 06:48
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Re: what level of overshoot is acceptalbe

I guess you can look at it as 12% above Vcc. Just be careful not to assume its always 12%. If your Vcc was
slightly less or slightly more... it could be 10% or 13% because the ration relative to 0.4V would change.
Basically, if your Vcc is 3.3V, then you can experience up to 3.7V of overshoot for no more than 20ns. Very
important to keep the 20ns in mind. If you see 3.7000V last for 21ns, then its too much. If you cross the 3.7V
threshold, even for an instant, then you violate the spec...

Ideally, you should not go above VIH, which you said was Vcc+0.3V or in this case 3.6V assuming a Vcc of 3.3V. I
always like to be conservative like that.

Keep in mind that overshoot can vary from board to board and part to part depending on processes variance of
the IO drivers. So if you are close already, I would take steps to remove the overshoot because the next
board or part could have more or less overshoot.

If you are getting overshoot on some signals, add series resistors at the signal source to squelch the
overshoot. You may have to play around with the resistor value (I'd start with 25Ω), but at some point
that resistor should remove the overshoot and you should get a near textbook waveform. If you have a signal
integrity simulation tool, you can get the IBIS models and simulate the interface while experimenting
with various series resistor values. Just be aware that the series resistors may slow down the rising
edges of the signal and cause timing errors if you slow them down too much.

Erik M. Kundro

--- On Wed, 11/30/11, WANG Zhenwei
<Zhenwei.Wang@...> wrote:

From: WANG Zhenwei <Zhenwei.Wang@...>
Subject: RE: [SI-LIST] what level of overshoot is acceptalbe
To: "ERIK KUNDRO" <kundro85@...>, si-list@...
Date: Wednesday, November 30, 2011, 10:51 PM
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WANG Zhenwei | 1 Dec 2011 06:58
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Re: what level of overshoot is acceptalbe

Hi Erik,
    i very understand. my boss want a warrant that no different between primary chip and the secondary chip,
espectially in SI. but the measurement on overshooting exceeds 25%, which peak is exceed to 4V(flash was
power 3.3V). the result is very bad. so my question is what level of overshoot is acceptable? that is the history.

BR

Zhenwei Wang

------------------------------------------------------------------
ALCATEL-LUCENT

APAC ENTERPRISE ENGINEERING AND DEVELOPMENT CENTER

T: +86 21 6182 4420

M: +86 13671886168

Zhenwei.Wang@...

------------------------------------------------------------------

________________________________

From: ERIK KUNDRO [mailto:kundro85@...] 
Sent: 2011Äê12ÔÂ1ÈÕ 13:49
To: si-list@...; WANG Zhenwei
Subject: RE: [SI-LIST] what level of overshoot is acceptalbe

I guess you can look at it as 12% above Vcc. Just be careful not to assume its always 12%. If your Vcc was
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Nijagunamurthy, Hithesh (GE Intelligent Platforms | 1 Dec 2011 07:01
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Re: what level of overshoot is acceptalbe

How exactly are you measuring the overshoot? Active probes? Or is this just in simulation.

-Hithesh

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of WANG Zhenwei
Sent: Thursday, December 01, 2011 11:28 AM
To: ERIK KUNDRO; si-list@...
Subject: [SI-LIST] Re: what level of overshoot is acceptalbe

Hi Erik,
    i very understand. my boss want a warrant that no different between primary chip and the secondary chip,
espectially in SI. but the measurement on overshooting exceeds 25%, which peak is exceed to 4V(flash was
power 3.3V). the result is very bad. so my question is what level of overshoot is acceptable? that is the history.

BR

Zhenwei Wang

------------------------------------------------------------------
ALCATEL-LUCENT

APAC ENTERPRISE ENGINEERING AND DEVELOPMENT CENTER

T: +86 21 6182 4420

M: +86 13671886168

Zhenwei.Wang@...
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john lin | 1 Dec 2011 09:34
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Re: SDD21 and SDD11

Hi,
I would like to show my appreciation to all experts, who response my
questions.  :-)
Thanks,
John

2011/11/30 john lin <johnlinc@...>

> Hi SI experts,
>
> Could you please help to comment about  I have a good SDD21, insertion
> loss,  but not a good SDD11, return loss?
> Shall low insertion loss have a low return loss?
> The total power shall include transmitted and reflected powers.
>
>  From my recent S4P extraction for a differential pair about 3 inch in
> length, I can see
>  SDD21 does meet spec. However, the SDD11 violates the spec, less than
>  -10dB.
> will it be OK?  Is the SDD21 our main concern?
>
> Thank you for your helps in advance.
>
> Best Regards,
> John
>
>

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