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Bob Ross | 1 Nov 2011 01:38

[IBIS] Asian IBIS Summit (Shanghai) - Fifth Announcement

To All:

The IBIS Open Forum is holding an Asian IBIS Summit Meeting in

Shanghai, China, a major technology center.  The meeting will take

place on Tuesday, November 15, 2011.

Several companies listed below are co-sponsoring this large event

to be held at the Parkyard Hotel, Shanghai.  Like in previous

years, we are planning for a large number of attendees including

several IBIS experts from the USA.

As noted in the AGENDA section below, we have a full program. The

Agenda will be issued later.

For travel consideration, two other Asian IBIS Summits follow this

event:

  Yokohama, Japan, Friday, November 18, Pacifico Yokohama

  Taipei, Taiwan, Monday, November 21, Sherwood Hotel

Bob Ross
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Cosmin Iorga | 1 Nov 2011 06:57
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Looking for FPGA on-die PDN Frequency Characteristic Measurement Test Cases

Hello Everyone,
 
I am looking for potential FPGA test cases where I can further study/test a technique for measuring on-die
the frequency characteristic (frequency profile) of the power distribution impedance of the FPGA. I
have developed and tested this technique so far on Xilinx FPGAs and it works well but I am interested to see
how it works in different applications using various other types of FPGAs. If you want to participate in
this study please let me know. 
 
What you get is: free multiple on-die measurements of power distribution profile of your FPGA project that
you can use to verify/adjust decoupling capacitors values, troubleshoot PDN issues, or figure out
resonance peaks where you do not want the FPGA clock to operate. 
 
What I get is: further study and validation of this measurement technique.
 
There should be no major impact to your project and the test should be fast. This technique uses a
measurement block built only with common logic blocks existing in any FPGA and which then is connected
through a serial interface to a notebook computer. A software application runs on the computer and
measures the impedance profile of the power distribution as seen by the on-die circuits inside the FPGA.
After this measurement, the FPGA can be reprogrammed to the original state/functions. 
If you are interested or have any questions please contact me at this email address or at  
Best Regards,
Cosmin
　
Cosmin Iorga, Ph.D.
Founder,
NoiseCoupling.comhttp://www.noisecoupling.comcosmin.iorga <at> noisecoupling.com
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N. Paul Taddonio | 1 Nov 2011 13:25

Re: How to solve short circuit issues in high dense pcbs

You may also be able to apply freezer spray to various locations on the 
board while observing the resistance from power to ground.

----- Original Message ----- 
From: "Istvan Nagy" <buenos@...>
To: "rskiruban" <rskiruban@...>; <si-list@...>
Sent: Monday, October 31, 2011 5:14 PM
Subject: [SI-LIST] Re: How to solve short circuit issues in high dense pcbs

> Hi,
>
> You might have known this already, but I think it's worth mentioning:
> If you measure power planes with a multimeter, you would find that most 
> low
> voltage rails appear to be a short circuit, like 1...10 Ohms. For example 
> a
> 1W+ processor's core and I/O rails normally look like this. That is not a
> short circuit, but it's normal.
>
> Sometimes there is really a short circuit. Then what I do is either use a
> thermal camera, or use a logic analyzer on the power sequencing logic to
> find out which power rail has the short. I normally use an FPGA for
> sequencing and use the Actel-Identify on-chip debugger and some tricks in
> the sequencer's VHDL code. The sequencer turns every rail on, and if a
> powerOK signal doesn't get asserted on one rail (due to a short circuit
> load), then the sequencer shuts down within milliseconds and latches all
> signals (Power_OK and Power_Enable), then it displays them on my screen.
> This way its easy to see which rail has really a short, without leaving it
> on for seconds or minutes (risking a damage) to inspect by a human (me in
> the lab). So its safe enough. If you dont have an FPGA on your board for
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Filion, Marc-Andre | 1 Nov 2011 16:45

Re: 10 Layer Stack-up board/TWR PCB

Hi,
I've always heard that it's a golden rule to have a symmetrical and balanced stackup, is it just a solid myth
or does it have solid roots?
Is it possible to have a non-balanced PCB? Does the dielectric must be also balanced or just the copper layer?
What are the impact of having an unbalanced stackup? 

Best regards,

Marc-André Filion | Hardware designer | Kontron Canada | T 450 437 5682 x2243 |
E marc-andre.filion@... 

Kontron Canada Inc
4555 Rue Ambroise-Lafortune
Boisbriand (Québec) J7H 0A4

The information contained in this document is confidential and property of Kontron Canada Inc. Any
unauthorized review, use, disclosure or distribution is prohibited without express written consent of
Kontron Canada Inc. If you are not the intended recipient, please contact the sender and destroy all
copies of the original message and enclosed attachments.
-----Message d'origine-----
De : si-list-bounce@...
[mailto:si-list-bounce@...] De la part de Jory McKinley
Envoyé : Monday, October 31, 2011 6:06 PM
À : Jory McKinley; Jayasuryan KG; si-list@...
Objet : [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB

This is a better baanced stack!
 
 
 
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Rick Collins | 1 Nov 2011 16:44
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Re: 10 Layer Stack-up board/TWR PCB

For the purpose of impedance and SI issues the power and ground 
layers are interchangable.  But you will get much higher capacitance 
between the power and ground layers if you were to alternate 
them.  For example swap PWR2 and GND2 so that you get higher 
capacitance between the alternate pairs GND1/PWR1, PWR1/GND2 and 
GND2/PWR2.  Otherwise I don't see any issues with the stackup.

I assume the green layer is a power layer and the blue layer is a 
ground layer.  I would recommend that you make these layers solid 
with no traces.  I also don't see any connection between the top 
(RF-ADC) area and the bottom area (Digital?).  Shouldn't these be 
connected?  I suppose these are actually signal layers with extra 
ground or power plane?

The capacitance between these layers is very significant at high 
frequencies.  I suggest that you try to maximize it as much as practical.

Rick

PS Now I need to deal with the couple of dozen "Out of Office" 
replies I always get when I post to this list....

At 01:39 PM 10/31/2011, you wrote:
>Dear Experts,
>
>
>I have a question regarding my Through Wall Radio(TWR) PCB. My 
>stack-up is as follows.
>
>
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Jory McKinley | 1 Nov 2011 17:02
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Re: 10 Layer Stack-up board/TWR PCB

My post are showing up either without content or partial?   Hopefully this one post correctly. 
This is the stack-up I would consider for Jayasuryan board:
 
TOP      
 
GND                      
DVDD1_2/D2VDD1_2/DVDD1_8

GND

SIG1/SIG2
 
SIG3/SIG4

GND

DVDD5/DVDD3_3

GND 

BOTTOM

Regards,
-Jory
 
 

From: "Filion, Marc-Andre" <marc-andre.filion@...>
To: Jory McKinley <jory_mckinley@...>
Cc: si-list@...
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Doug Brooks | 1 Nov 2011 19:00

Mode conversion question

Assume I have a differential trace pair. Assume there is a slight 
offset in the two signals.

My understanding of mode conversion is that the signal pair will 
become two components --- an odd mode component and an even mode component.

In trying to understand WHY that happens I have come to believe there 
is no physical change in the signals. What we do is MODEL the signals 
as two separate components, an odd mode component and an even mode 
component, which combine together to equal the actual signal. Thus 
mode conversion is a mathematical (and physical) model that allows us 
to deal with the analysis, rather than an actual physical phenomenon.

Is my understanding correct here, or am I way off base?

Thanks for your help.

Doug Brooks

Check out our resources at  http://www.ultracad.com 

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Danny Damhave | 1 Nov 2011 19:31

Re: How to solve short circuit issues in high dense pcbs

Hi Kiruba
If not already done it is also a good idea to check the orientation of all the ICs and that all land patterns for
the ICs are correct (right pitch etc.)
I have seen both causes shorts.
BR
Danny Damhave
On 31/10/2011, at 09.01, rskiruban wrote:

> Hi All,
> One of my board having a short circuit (Zero Ohms) across a power supply (That  supply connects to thousands
of decoupling capacitors and 44 BGAs) and Ground.  Is there any method to identify the route cause for the
short without removing any components?
> 
> Note:
> ####
> 1. The board is not yet powered on.
> 2. It was verified that the PCB doesn't contains any short across supplies before board assembly.
> 
> 
> Thanks and regards
> Kiruba Sankar
> Project leader
> Hardware Design & Development
> Email: rskiruban@...
> web: www.datapatternsindia.com
> **************** CAUTION - Disclaimer *****************This email may contain confidential and
privileged material for the
> sole use of the intended recipient(s). Any review, use, retention, distribution or disclosure by others
is strictly prohibited. If you are not the intended recipient (or authorized to receive for the
recipient), please contact the sender by reply email and delete all copies of this message. Also, email is
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Lee Ritchey | 1 Nov 2011 20:27
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Re: 10 Layer Stack-up board/TWR PCB

Way too many ground planes.

--------------------------------------------------
From: "Jory McKinley" <jory_mckinley@...>
Sent: Tuesday, November 01, 2011 9:02 AM
To: "Filion, Marc-Andre" <marc-andre.filion@...>
Cc: <si-list@...>
Subject: [SI-LIST] Re: 10 Layer Stack-up board/TWR PCB

> My post are showing up either without content or partial?   Hopefully this 
> one post correctly.  This is the stack-up I would consider for Jayasuryan 
> board:
>
> TOP
>
> GND
> DVDD1_2/D2VDD1_2/DVDD1_8
>
> GND
>
> SIG1/SIG2
>
> SIG3/SIG4
>
> GND
>
> DVDD5/DVDD3_3
>
> GND
>
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Orin Laney | 1 Nov 2011 21:11
Picon

Re: Mode conversion question

The two modes have different impedances, velocities of propagation, and
propensities to radiate.

Orin Laney

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of Doug Brooks
Sent: Tuesday, November 01, 2011 11:01 AM
To: si-list@...
Subject: [SI-LIST] Mode conversion question

Assume I have a differential trace pair. Assume there is a slight offset in
the two signals.

My understanding of mode conversion is that the signal pair will become two
components --- an odd mode component and an even mode component.

In trying to understand WHY that happens I have come to believe there is no
physical change in the signals. What we do is MODEL the signals as two
separate components, an odd mode component and an even mode component, which
combine together to equal the actual signal. Thus mode conversion is a
mathematical (and physical) model that allows us to deal with the analysis,
rather than an actual physical phenomenon.

Is my understanding correct here, or am I way off base?

Thanks for your help.
(Continue reading)

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Gmane