Ajay G | 1 Aug 10:16 2011
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Job opening, Freescale India.

**
**
**
*Package Signal Integrity Power Integrity (PISI) Design Engineer:*
  *Department Description *

World Wide Design.

*Job Location *
  Noida, India

*Scope of Responsibilities/Expectations *

- Develop and drive Package Design activities in Networking group of
Freescale.

- Drive Flip Chip Package designs for High Performance SOCs.

- Drive Wire Bond Package designs for Cost sensitive SOCs.

- Package Signal Integrity and Power Integrity Analysis..

- Package model generation – S-parameter models, Broadband spice models, RLC
models

- Package Model Extraction with 2D and 3D field solvers.

- IBIS model generation and support to customers.

-System level Signal Integrity Simulation
(Continue reading)

Jason Young | 2 Aug 12:01 2011

SSO and load capacitance

Dear Experts,
I have read a couple of documents are from silicon IP vendors discussing the number of power/ground pads
needed to meet SSO requirements for a given number of output drivers. These documents mention that worse
case conditions for SSO are with the smallest output load capacitance. At first this seems counter
intuitive.  My initial reasoning would be that a larger capacitance would present a lower impedance load
and hence greater dI/dt, greater IR drop and greater supply rail bounce.  Could you please help me understand?
Regards,
Jason

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steve weir | 2 Aug 13:24 2011

Re: SSO and load capacitance

Jason, there are two possible sources of confusion.  The first is 
possible confusion between output load capacitance with die capacitance 
per output driver.  Your intuition is correct:  If we simplify the PDN / 
driver network to a switched capacitor representation, then we deposit 
Qload = Vdd*Cload on each output line that switches from low to high, 
and remove Qload from each output that switches from high to low.  For 
the low to high switching outputs: Qload comes from Qbypass = (Vdd - 
Vdroop)^2/2*Cbypass.

The second source of confusion comes from the fact that any loads that 
remain statically high can draw current from any load capacitance that 
connects to the driver outputs, supporting other outputs that switch 
from low to high.

Steve.

On 8/2/2011 3:01 AM, Jason Young wrote:
> Dear Experts,
> I have read a couple of documents are from silicon IP vendors discussing the number of power/ground pads
needed to meet SSO requirements for a given number of output drivers. These documents mention that worse
case conditions for SSO are with the smallest output load capacitance. At first this seems counter
intuitive.  My initial reasoning would be that a larger capacitance would present a lower impedance load
and hence greater dI/dt, greater IR drop and greater supply rail bounce.  Could you please help me understand?
> Regards,
> Jason
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
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steve weir | 2 Aug 13:40 2011

Re: SSO and load capacitance

Oops the second formula was energy not charge.  It should have read 
Qload comes from Qbypass = Vdroop*Cbypass.

Steve
On 8/2/2011 4:24 AM, steve weir wrote:
> Jason, there are two possible sources of confusion.  The first is
> possible confusion between output load capacitance with die capacitance
> per output driver.  Your intuition is correct:  If we simplify the PDN /
> driver network to a switched capacitor representation, then we deposit
> Qload = Vdd*Cload on each output line that switches from low to high,
> and remove Qload from each output that switches from high to low.  For
> the low to high switching outputs: Qload comes from Qbypass = (Vdd -
> Vdroop)^2/2*Cbypass.
>
> The second source of confusion comes from the fact that any loads that
> remain statically high can draw current from any load capacitance that
> connects to the driver outputs, supporting other outputs that switch
> from low to high.
>
> Steve.
>
>
> On 8/2/2011 3:01 AM, Jason Young wrote:
>> Dear Experts,
>> I have read a couple of documents are from silicon IP vendors discussing the number of power/ground pads
needed to meet SSO requirements for a given number of output drivers. These documents mention that worse
case conditions for SSO are with the smallest output load capacitance. At first this seems counter
intuitive.  My initial reasoning would be that a larger capacitance would present a lower impedance load
and hence greater dI/dt, greater IR drop and greater supply rail bounce.  Could you please help me understand?
>> Regards,
(Continue reading)

mfc programming | 2 Aug 16:03 2011

sfp cage holes to chassis ground

Hi,
I`m trying to add a SFP pressfit cage to my layout. This cage has a lot of
holes and ground tabs which are connected by the aluminium case of the
product and therefore directly connected to the chassis ground. That means
every hole of this sfp cage should be connected to the chassis ground, too.
Within the case there`s the sfp connector located with 20 signal
connections. These signals and grounds belong to the system ground.

Do you know a good application note with screenshots how to route these
signals to the sfp connector as well as routing the chassis ground
connection? Because the sfp cage holes are around the sfp connector located,
I have only one small gap to route all 20 signals to the connector with the
system ground. The other solution would be to leave the three sfp cage holes
located behind the connector unconnected.

best regards
Hans

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Larry Smith | 2 Aug 17:18 2011

Re: SSO and load capacitance

Jason - the comment is correct: the worst case SSN waveforms will be found with minimum load capacitance. 
But some explanation is required.

First, SSN can be broken down into two components: inductive coupling and PDN.  Steve is referring to the PDN
part in his response. But usually the greatest SSN noise amplitude measured at the far end of a signal
transmission line comes from inductive coupling, not PDN.

Inductive coupling is related to mutual inductance between aggressor signals and the victim signal.  It
only happens during the rise (fall) time of the driver because that is when the di/dt takes place.  To a first
approximation, the voltage noise that gets launched into a victim transmission line (under the BGA that
makes the SSN) is proportional to m*di/dt where m is the sum of the mutual inductance from all the
aggressors to the victim and i is the current in the aggressors.  Mutual inductance occurs in the wire
bonds, package vias, balls and PCB vias and to a first approximation is proportional to the length of these structures.

These days, the aggressor rise time is on the order of 200pSec, which is the time that it takes signals to
travel about an inch down a transmission line.  The capacitance load in question is down at the far end of the
transmission line, let's assume 6 inches.  The 200pSec rise time aggressors launch an SSN noise pulse into
the victim signal net that is approximately 200pSec wide and it arrives at the capacitance load about
1000pSec later.  The load capacitance at the far end will have no effect on the SSN event that launches the
SSN glitch into the victim transmission line.

When the SSN glitch arrives at the far end of the transmission line, it often finds a 50 ohm termination.  The
noise measured at the far end is identical to the glitch launched into the near end, assuming lossless
lines.  Now if there is any capacitance load at the far end, glitch energy goes into charging up the load.  The
measured SSN glitch voltage amplitude will be less with more load capacitance.

Regards,
Larry Smith

-----Original Message-----
(Continue reading)

Scott McMorrow | 2 Aug 18:17 2011

Re: SSO and load capacitance

Larry

Be careful.  Load capacitance looks like a momentary reflected short 
circuit to the driver.  If the driver is not well matched (for example 
low output impedance drive on a DDR driver), we have effectively two low 
impedance discontinuities on either end of the line, setting up a 
half-wave resonant circuit.  Now, you are quite right that the reflected 
discontinuity back from the load capacitance can never be larger than 
the initial SSO charge up of the line at the driver, however, it is 
possible to tune the delay such that the reflection reaches the driver 
at exactly the wrong time - when the driver switches during the next 
cycle.  With the right bit rate, a standing wave can occur, causing SSO 
to peak.

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC

On 8/2/2011 11:18 AM, Larry Smith wrote:
> Jason - the comment is correct: the worst case SSN waveforms will be found with minimum load capacitance. 
(Continue reading)

jfhasson | 2 Aug 18:45 2011
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Use of non specific connectors for ethernet 10/100 communication

Hi,

I am currently working on a project involving a 10/100 BASE TX link. It is intended to route this bus through
non specific connectors ie connectors for which differential impedance and return loss are not
guaranteed. Is it valid to consider impedance as not being a problem as the impedance discontinuity
length due to the connector is not more than 2 cm long which is small compared to the significant wavelength
of the 100 BASE TX signal ? Regarding crosstalk we can separate the RX and TX signals significantly so we
don't believe it would be an issue knowing we would only have this full duplex ethernet bus inthe
connector. We don't have to show compliance to the 802.3 standard but we need to have an operating link over
up to 15 meters. We would be using shielded cables of a quadrax type. What issues could we meet in terms of EMI
or SI if the previous statements are valid ?

JF Hasson

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Larry Smith | 2 Aug 20:55 2011

Re: SSO and load capacitance

Scott - You are correct about the reflection phenomenon with transmission lines that are not perfectly
terminated.  We will definitely get a bounce off the load capacitance and energy coming back towards the
place where SSN originated.  I consider that to be more of a bus termination problem than an SSN problem.

I have a very narrow definition of SSN (simultaneous switch noise).  It is the waveform launched into a
victim (quiet-high or quiet-low) signal line when aggressor signals switch simultaneously.  As
mentioned before, there is an inductive coupling portion to the signal that is only launched during the
aggressor rise (fall) time and there is a longer wavelength PDN component (that Steve referred to) that is
initiated by the SSN event.  The inductive coupling component tends to be about 200 pSec long (~ .35/.2 =
1.75 GHz content) and the PDN component tends to be at about 100MHz.

I consider the reflections that you have discussed to be part of the "system response" to the SSN event.  Yes,
this is very important but I find it useful to divide things up into the initial noise stimulus and then the
system response to that stimulus because you may choose to manage each of these independently.  As a
component house, we can only manage the initial stimulus.  The system house needs to manage the
board/reflection/termination/load issues.  And of course, we need to provide the system houses with
components that they can live with on their boards.  :)

Another point to be made is that the inductive coupling glitch (1.75MHz frequency content) fortunately
suffers significant loss on its journey to the load and back to the source. This tends to damp out system
resonances at least to some degree.  When we go to measure inductive coupling SSN, we have to account for the
loss in our measurement fixture (possibly 18 inches of board transmission line) and use de-embedding to
find out the SSN amplitude that our customers are likely to see at some distance away from the SSN source.  In
this case, loss is our friend..

Regards,
Larry

-----Original Message-----
From: si-list-bounce@...
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Scott McMorrow | 2 Aug 21:18 2011

Re: SSO and load capacitance

larry
The question was about SSO, not SSN.  SSN, as you have defined it is 
merely the inductive coupling component of the noise within the package. 
However, SSO noise (by my definition) extends throughout the system, and 
is influenced by all aspects of the system design.  One thing that you 
fail to take into account is the possibility that your driver design 
might have an impact on the overall SSO noise.  Even with the best end 
of line termination, capacitive loads will still kick back to the driver 
and interact with it's dynamic impedance - which is an aspect of the 
silicon design.  Simultaneously, there is the additional interaction of 
the power system with the driver.  This leads to some interesting 
practical considerations.

    * Some drivers have excessively low output impedance during
      transient switching and can be problematic in this regard. 
      Clearly this can be a silicon issue, that I've seen way too many
      times to count.
    * Other drivers have dynamic slew rate control circuits (that can
      generally only be modeled in Spice, and are often not modeled at
      all)  that can act unfavorably and turn off prematurely when these
      reflected waves travel back to the driver.  I've seen this on
      numerous occasions across various memory interface types.
    * These are not "just" system issues, but are instances of the
      silicon interacting with the system in interesting ways.

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
(Continue reading)


Gmane