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Moran, Brian P | 1 May 2011 02:03
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Re: DDR-Length matching

Hi Aubrey,

Point well taken. A well optimized design would length match to the point where
additional margin is no longer free for the taking. At that point, if margins
are adequate for the design objectives you are done. I certainly would not
advocate adding layers if the deisgn does not require.

Brian Moran
Signaling Development Group
Client Platforms
Intel Corporation

-----Original Message-----
From: Aubrey Sparkman [mailto:asparky@...] 
Sent: Saturday, April 30, 2011 2:41 PM
To: Moran, Brian P; Loyer, Jeff; 'steve weir'
Cc: si-list@...
Subject: RE: [SI-LIST] Re: DDR-Length matching

Brian,

If you are doing a design where you have real estate to spare, I don't
disagree with what you have said.
On the other hand, you asked why I might leave margin on the table.  I would
ask you to consider the scenario where you working on a very small board and
are cramped for space.  Would you still recommend the extra serpenting if it
would cause you to add a pair of (you can't add just one) layers?

Thanks,
Aubrey Sparkman
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Lance Wang | 2 May 2011 04:24

European IBIS Summit Meeting Agenda - May 11, 2011

All:

The 14th European IBIS Summit is on Wednesday afternoon and

follows the IEEE Workshop on Signal Propagation on Interconnects:

  http://www.spi2011.unina.it/

Below is the meeting agenda.  The IBIS meeting is free.  If

you plan to attend, please register with Lance Wang and Antonio

Girardi, as noted at the end.

Antonio Girardi

Micron Technology (formerly Numonyx)

Lance Wang

IO Methodology

------------------------------------------------------------------

                AGENDA, EUROPEAN IBIS SUMMIT MEETING

                      Wednesday, May 11, 2011

                      Grand Hotel Santa Lucia
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Ken Wyatt | 3 May 2011 01:43
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EMC Newsletter Delivered - Spring 2011

Hi All,
I just mailed my Spring 2011 EMC Design Newsletter out to all current subscribers. This issue contains a
review article on the Smart Tweezers RLC meter, A case study on cable radiation due to poorly bonded I/O
connectors and a continuing series on bench-top troubleshooting of radiated emissions.

If you're not already subscribed, click below and you'll receive links to all the past issues. Sign up here: http://www.emc-seminars.com/Newsletter/Newsletter.html

Cheers, Ken
_______________________
Kenneth Wyatt
Wyatt Technical Services LLC
Woodland Park, CO
Email Me! | Web Site | Blog
Subscribe to Newsletter
Connect with me on LinkedIn

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Cheng, Chris | 3 May 2011 04:21
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Re: DDR-Length matching

My concern is there are company out there who use these ridiculous matching rules as a "get out of jail free
card" when things doesn't work.
I have personally seen a certain design where the clock to q coming out of the IC has clearly exceeded the
maximum spec by the vendor by over a 1ns. And yet when confronted with the problem, the application
engineer pull out the spec and claim because I exceeded the maximum length in design guide by 120mils, the
part is no longer guarantee to work and it's my own fault. I am lucky to still have my job but I have heard
people losing their job on these kind of bogus excuses.
The tin foil side of my brain thinks whoever wrote these rules knows how ridiculous they are but keep it
anyways just so if they run into real problems they can hide behind them to blame their customers.

Chris Cheng

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Moran, Brian P
Sent: Thursday, April 28, 2011 10:09 AM
To: Loyer, Jeff; steve weir
Cc: si-list@...
Subject: [SI-LIST] Re: DDR-Length matching

Hi All,
The tight +/-10 mil spec usually refers to matching within the DQS pairs and in some cases
between DQ and their respective DQS strobes.  +/-10 mils is reasonable for the diff pair
matching, but perhaps a bit tight for DQ to DQS. The tighter you match the better your margins.
Most designs have some margin to give, but on the other hand, once you start matching
traces you might as well match to the tightest reasonable guideline. Why leave margin on
the table.  But you can do the math as far as how much margin you give up by loosening the
matching. I agree its not a matter of pass/fail.  Its more a matter of optimization. 

Note that most controllers provide timing control per byte lane, so there is no
(Continue reading)

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steve weir | 3 May 2011 05:23

Re: DDR-Length matching

Chris, I think the rules are well-intended, but as your story and 
Aubrey's story both point-out, that while these ideas are guidelines 
that can be useful in many situations in other situations they are 
counterproductive.  Design guidelines and best practices should be 
clearly delineated from performance: specifications / requirements / 
rules.  I ask that the people who sit on specification committees avoid 
assumptions as much as possible.  Paraphrasing Bruce Archambeault:  "We 
are engineers.  We are supposed to think."

Best Regards,

Steve.

On 5/2/2011 7:21 PM, Cheng, Chris wrote:
> My concern is there are company out there who use these ridiculous matching rules as a "get out of jail free
card" when things doesn't work.
> I have personally seen a certain design where the clock to q coming out of the IC has clearly exceeded the
maximum spec by the vendor by over a 1ns. And yet when confronted with the problem, the application
engineer pull out the spec and claim because I exceeded the maximum length in design guide by 120mils, the
part is no longer guarantee to work and it's my own fault. I am lucky to still have my job but I have heard
people losing their job on these kind of bogus excuses.
> The tin foil side of my brain thinks whoever wrote these rules knows how ridiculous they are but keep it
anyways just so if they run into real problems they can hide behind them to blame their customers.
>
> Chris Cheng
>
>
> -----Original Message-----
> From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Moran, Brian P
(Continue reading)

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Kinger.cai-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org | 3 May 2011 06:13
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Re: DDR-Length matching

Chris's case might need a global length matching of the routing in both package and on board, while the
package routing length (or delay) table have to be provided together with the design guideline. 
Overall it is much easier to achieve a global length matching than local length matching particularly for
tight timing budget of higher DDR data rate.

Thx,

Sent from kinger's iPhone

On May 2, 2011, at 8:23 PM, steve weir <weirsi@...> wrote:

> Chris, I think the rules are well-intended, but as your story and 
> Aubrey's story both point-out, that while these ideas are guidelines 
> that can be useful in many situations in other situations they are 
> counterproductive.  Design guidelines and best practices should be 
> clearly delineated from performance: specifications / requirements / 
> rules.  I ask that the people who sit on specification committees avoid 
> assumptions as much as possible.  Paraphrasing Bruce Archambeault:  "We 
> are engineers.  We are supposed to think."
> 
> Best Regards,
> 
> 
> Steve.
> 
> On 5/2/2011 7:21 PM, Cheng, Chris wrote:
>> My concern is there are company out there who use these ridiculous matching rules as a "get out of jail free
card" when things doesn't work.
>> I have personally seen a certain design where the clock to q coming out of the IC has clearly exceeded the
maximum spec by the vendor by over a 1ns. And yet when confronted with the problem, the application
(Continue reading)

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Ben Chia | 3 May 2011 06:31

Re: forensic S-parameter analysis paper for download

Hi everyone,

Just so everyone knows, I'll be holding a hands-on workshop on practical fixture
de-embedding which will be held on May 17, the day after Eric Bogatin's SPSI 
class
held at the same location.

You can get more information on this workshop and download past presentations on
SATA, USB, and DisplayPort testing here:
http://graniteriverlabs.com/training-events/

-Ben

----- Original Message ----
From: Eric Bogatin <eric@...>
To: si-list@...
Cc: eric@...
Sent: Mon, April 11, 2011 1:50:50 PM
Subject: [SI-LIST] forensic S-parameter analysis paper for download

Hi folks-

I just gave a talk at the 5th annual Penn State SI Symposium that Aldo
Morales coordinates. Here is the link for the conference:
http://hbg.psu.edu/csi/agenda.php

My talk was on Forensic S-Parameter Analysis: data mining S-parameters to
determine the root cause for some SI problems.

If you would like a copy of my talk, you can download it from my web site
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Cheng, Chris | 3 May 2011 06:36
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Re: DDR-Length matching

No, that's just the case when certain company not willing to admit their common mode clock to q is out of spec
by 50% and when confronted with measured data their application engineer dig up ANY word in the spec that
doesn't match the actual design to run away from responsibility. 
Don't bring me up on those package skew numbers that are in the 1ps-5ps range in a DDR2 design that need to be
matched. That's just nuts.

Chris Cheng

 

-----Original Message-----
From: Kinger.cai@...
[mailto:kinger.cai@...] 
Sent: Monday, May 02, 2011 9:14 PM
To: steve weir
Cc: Cheng, Chris; Moran, Brian P; Loyer, Jeff; si-list@...
Subject: Re: [SI-LIST] Re: DDR-Length matching

Chris's case might need a global length matching of the routing in both package and on board, while the
package routing length (or delay) table have to be provided together with the design guideline. 
Overall it is much easier to achieve a global length matching than local length matching particularly for
tight timing budget of higher DDR data rate.

Thx,

Sent from kinger's iPhone

On May 2, 2011, at 8:23 PM, steve weir <weirsi@...> wrote:

> Chris, I think the rules are well-intended, but as your story and
(Continue reading)

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Dan Smith | 3 May 2011 07:03
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Re: DDR-Length matching

As engineers we need to keep holding the vendor's feet to the fire.  DDR "rules" are usually hogwash as most
typically they come from vendors that regurgitate what they did on their EVAl boards.  Hell, I even had a
vendor tell me once that "they don't recommend memory vendor-A but memory vendor-B"  I dove into this cause
and at the end of the day it was because there EVAl board had vendor-B.

That is absurd engineering!

There is nothing magical about DDR designs relative to timing (DDR2, DDR3...).  There is a flip flop on one
side with a delay relationship between the data out and the signal that is clocking it, and there is a
requirement needed at the far end with a setup and hold time relative to the clocking signal and the data. 
This is HW engineering 101.  Of course we know SI can eat into timing as well and is easily simulated for a
given topology.

As much as it can be a struggle, force the chip vendors who make memory controllers to provide this timing
information for their chips (across their transmission lines in their OWN package)!  Think about it, any
chip vendor who does not know this information about their DDR delivery should get out of the business!  It
then becomes a simple flip-flop timing math equation across the medium of transition (PCB).  That's just
part of the up-front engineering math.

Dan

"Make everything as simple as possible and no simpler" - Albert Einstein

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Cheng, Chris
Sent: Monday, May 02, 2011 9:36 PM
To: Kinger.cai@...; steve weir
Cc: Moran, Brian P; Loyer, Jeff; si-list@...
Subject: [SI-LIST] Re: DDR-Length matching
(Continue reading)

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Ciccomancini, Antonio | 3 May 2011 15:36
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CST Leading technology workshop

Dear All,
it's a short notice, but I would like to invite those of you living/working in Chicago area to attend the
following workshop: CST Leading Technology.
Details and full agenda are available here http://www.cst.com/Content/Events/Details.aspx?eventId16
Hope to see you there!
Kind regards, Antonio
Antonio Ciccomancini Scogna -
CST of America, Inc
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