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prasad | 1 Feb 2011 05:29
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relation between signal rise time and scope rise time

hi All,
i was going through one of the note from an oscilloscope vendor  saying

*oscilloscope rise time < signal rise time/5.*   its available at link
below
http://www.tek.com/Measurement/scopes/selection/pdf/55W_13768_2_rise.pdf

but when i looked at the howard Johnson's book for High speed Digital
Design, where the BW of a signal is calculated  as FKnee=  .5/Tr, and then
BW of scope is chosen as around 1.4 to 2 times of BW.

am i missing anything while trying to interpret what the  above highlighted
statment?  request your comments.

Thanks for taking time to read this....

Best Regards,
Hari....

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Saravanan | 1 Feb 2011 05:35

Re: relation between signal rise time and scope rise time

Dear Hariprasad,

 Thankyou very much

Thanks & Regards,
Saravanan.R
+91 8095134155

On Tue, 1 Feb 2011 09:59:04 +0530, prasad <hariprasad.palli@...>
wrote:
> hi All,
> i was going through one of the note from an oscilloscope vendor  saying
> 
> *oscilloscope rise time < signal rise time/5.*   its available at link
> below
> http://www.tek.com/Measurement/scopes/selection/pdf/55W_13768_2_rise.pdf
> 
> 
> but when i looked at the howard Johnson's book for High speed Digital
> Design, where the BW of a signal is calculated  as FKnee=  .5/Tr, and
then
> BW of scope is chosen as around 1.4 to 2 times of BW.
> 
> am i missing anything while trying to interpret what the  above
highlighted
> statment?  request your comments.
> 
> 
> Thanks for taking time to read this....
>
(Continue reading)

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Alfred Lee | 1 Feb 2011 06:20
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Re: relation between signal rise time and scope rise time

Here's my take.

With HJ's rule, at near the limit, what you see is not what you get, but you could figured out what it was.

With Tek's rule, who is in the interest of selling scopes, at the limit, what you see is for all practical
purposes  what you get.

-
Alfred

"prasad" <hariprasad.palli@...> wrote:

>hi All,
>i was going through one of the note from an oscilloscope vendor  saying
>
>*oscilloscope rise time < signal rise time/5.*   its available at link
>below
>http://www.tek.com/Measurement/scopes/selection/pdf/55W_13768_2_rise.pdf
>
>
>but when i looked at the howard Johnson's book for High speed Digital
>Design, where the BW of a signal is calculated  as FKnee=  .5/Tr, and
>then
>BW of scope is chosen as around 1.4 to 2 times of BW.
>
>am i missing anything while trying to interpret what the  above
>highlighted
>statment?  request your comments.
>
>
(Continue reading)

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Nijagunamurthy, Hithesh (GE Intelligent Platforms | 1 Feb 2011 06:36
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Favicon

CPU-Memory Termination


Hi Experts,

How do you terminate and what kind of termination to use when both the
CPU and Memory can drive the Address/Data bus. 
If CPU is the only driver, using series termination would make sense.
But when Memory is driving, the series termination resistor is not at
all near the driver.
Is the answer not to use termination at all?

Thanks,
-Hithesh
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Tom Dagostino | 1 Feb 2011 06:42

Re: relation between signal rise time and scope rise time

It all depends on how accurate you want your measurements to be.  You can do the math yourself by remembering
that the measured risetime = SQRT[(Scope system risetime)^2 + (DUT risetime)^2].  The scope system
includes the scope plus probe plus whatever is between the scope and the DUT.  

If DUT and scope have the same risetime the error will be 41.4%  If the scope is half the DUT the error is 11.8%. 
At one forth the risetime you are down to 3% and at 5 times faster you have 2% error when measuring from the
scope screen.

Tom Dagostino
Teraspeed Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@... 
www.teraspeed.com 

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827
www.teraspeed.com  

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Alfred Lee
Sent: Monday, January 31, 2011 9:20 PM
To: si-list@...
Subject: [SI-LIST] Re: relation between signal rise time and scope rise time

Here's my take.
(Continue reading)

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T, Raghavendra (Electrical Engineer | 1 Feb 2011 06:44
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Re: CPU-Memory Termination

Hello Hitesh,

As per my view Address is always generated from One Side - hence series termination would be better option.

When considering DATA for memory, it is usual to use, ODT which is inbuilt inside most of the CPU and DDR memories.

If your memory is not DDR based on the simulation results you can try Thevein or parallel termination.

Regards,
Raghavendra

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Nijagunamurthy,
Hithesh (GE Intelligent Platforms)
Sent: Tuesday, February 01, 2011 11:07 AM
To: si-list@...
Subject: [SI-LIST] CPU-Memory Termination 

Hi Experts,

How do you terminate and what kind of termination to use when both the
CPU and Memory can drive the Address/Data bus. 
If CPU is the only driver, using series termination would make sense.
But when Memory is driving, the series termination resistor is not at
all near the driver.
Is the answer not to use termination at all?

Thanks,
-Hithesh
(Continue reading)

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Chockalingam Selvaraj | 1 Feb 2011 06:46
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Re: CPU-Memory Termination

Hi,

For bidirectional data-bus, series termination at both ends make sense.
But the hitch comes with the double voltage drop in the signal line.

Its better you run a SI simulation to rule out the need for any termination as the decision depends on the
signal rise time and the length of the trace.

I am unable to comprehend memory driving the address bus though !!!

Thanks and regards
Chockalingam.S (Ck)
________________________________________
From: si-list-bounce@...
[si-list-bounce@...] On Behalf Of Nijagunamurthy, Hithesh
(GE Intelligent Platforms) [hithesh@...]
Sent: Tuesday, February 01, 2011 11:06 AM
To: si-list@...
Subject: [SI-LIST] CPU-Memory Termination

Hi Experts,

How do you terminate and what kind of termination to use when both the
CPU and Memory can drive the Address/Data bus.
If CPU is the only driver, using series termination would make sense.
But when Memory is driving, the series termination resistor is not at
all near the driver.
Is the answer not to use termination at all?

Thanks,
(Continue reading)

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steve weir | 1 Feb 2011 06:58

Re: relation between signal rise time and scope rise time

Effective rise time is roughly the sum of the rise-times squared, 
including the: signal, probe, and scope.  It would be exact if these 
were each first order systems, but they are not, so it is approximate.

If you have a 1ns rise time signal, a 1ns rise time probe and a 500ps 
rise time scope then the effective rise time you will see on the scope 
will be(1E-18+1E-18+.25E-18)^0.5= 1.5ns, a 50% error.

Decrease the probe and scope rise times each by 3X and the error is 
about 10%.

Steve

Alfred Lee wrote:
> Here's my take.
>
> With HJ's rule, at near the limit, what you see is not what you get, but you could figured out what it was.
>
> With Tek's rule, who is in the interest of selling scopes, at the limit, what you see is for all practical
purposes  what you get.
>
> -
> Alfred
>
> "prasad" <hariprasad.palli@...> wrote:
>
>   
>> hi All,
>> i was going through one of the note from an oscilloscope vendor  saying
>>
(Continue reading)

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Chris Johnson | 1 Feb 2011 07:18

Re: CPU-Memory Termination

Hithesh,

There is a paper at 
http://www.ultracad.com/mentor/mentor%20termination%20placement.pdf that 
argues that series termination resistor placement is not all that 
critical.  In that case, you could consider putting it in the middle of 
the net, if it isn't too long.

Chris

On 2/1/2011 12:36 AM, Nijagunamurthy, Hithesh (GE Intelligent Platforms) 
wrote:
> Hi Experts,
>
> How do you terminate and what kind of termination to use when both the
> CPU and Memory can drive the Address/Data bus.
> If CPU is the only driver, using series termination would make sense.
> But when Memory is driving, the series termination resistor is not at
> all near the driver.
> Is the answer not to use termination at all?
>
> Thanks,
> -Hithesh
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@... with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
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Nijagunamurthy, Hithesh (GE Intelligent Platforms | 1 Feb 2011 07:18
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Favicon

Re: CPU-Memory Termination


The Memory does not drive the Address bus, only the data bus.

-Hithesh

-----Original Message-----
From: Chockalingam Selvaraj [mailto:chockalingam.s@...] 
Sent: Tuesday, February 01, 2011 11:16 AM
To: Nijagunamurthy, Hithesh (GE Intelligent Platforms);
si-list@...
Subject: RE: CPU-Memory Termination 

Hi,

For bidirectional data-bus, series termination at both ends make sense.
But the hitch comes with the double voltage drop in the signal line.

Its better you run a SI simulation to rule out the need for any
termination as the decision depends on the signal rise time and the
length of the trace.

I am unable to comprehend memory driving the address bus though !!!

Thanks and regards
Chockalingam.S (Ck)
________________________________________
From: si-list-bounce@...
[si-list-bounce@...] On
Behalf Of Nijagunamurthy, Hithesh (GE Intelligent Platforms)
[hithesh@...]
(Continue reading)

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