Rose, Michael | 1 Nov 02:04 2010

Re: Gigabit ethernet placing and routing related question

I think he means that the line side is balanced and the phy side in unbalanced, referenced to "logic ground."

mike
________________________________________
From: si-list-bounce@...
[si-list-bounce@...] On Behalf Of Stefan Milnor [stefan.milnor@...]
Sent: Sunday, October 31, 2010 3:04 PM
To: Lee Ritchey; Peter zhu; si-list@...; jhasson <at> rockwellcollins.com
Subject: [SI-LIST] Re: Gigabit ethernet placing and routing related question

Chassis GND: the potential that your chassis is at
________________________________

From: si-list-bounce@... on behalf of Lee Ritchey
Sent: Sun 10/31/2010 9:52 AM
To: Peter zhu; si-list@...; jhasson@...
Subject: [SI-LIST] Re: Gigabit ethernet placing and routing related question

There is not such thing as "chassis ground".  What is really meant by this
statement?

> [Original Message]
> From: Peter zhu <yonghui.sky@...>
> To: <si-list@...>; <jhasson@...>
> Date: 10/30/2010 2:11:00 AM
> Subject: [SI-LIST] Re: Gigabit ethernet placing and routing related
question
>
> PHY output is analog signals, so keep them as short as possible.
> The trace between PHY and transformer refers to signal GND, and the trace
(Continue reading)

steve weir | 1 Nov 04:54 2010

Re: Gigabit ethernet placing and routing related question

There are two important points:

"Ground" is a misnomer.  At RF frequencies the chassis has no special 
relationship to any potential somewhere in the external environment.  
The chassis is just a node, and it forms a radiating antenna with all 
wires that penetrate it.  What makes the chassis special is that one 
with limited apertures is effective at blocking radiated energy from 
passing either direction between the inside and the outside.

Coupling differences between signals past the magnetics and the chassis 
result in mode conversion that aggravates EMI headaches.  Careful 
attention to mode conversion containment is effort well-spent.

Steve.

Rose, Michael wrote:
> I think he means that the line side is balanced and the phy side in unbalanced, referenced to "logic ground."
>
> mike
> ________________________________________
> From: si-list-bounce@...
[si-list-bounce@...] On Behalf Of Stefan Milnor [stefan.milnor@...]
> Sent: Sunday, October 31, 2010 3:04 PM
> To: Lee Ritchey; Peter zhu; si-list@...; jhasson <at> rockwellcollins.com
> Subject: [SI-LIST] Re: Gigabit ethernet placing and routing related question
>
> Chassis GND: the potential that your chassis is at
> ________________________________
>
> From: si-list-bounce@... on behalf of Lee Ritchey
(Continue reading)

Lee Ritchey | 1 Nov 16:29 2010
Picon
Picon

Re: Gigabit ethernet placing and routing related question

Let's call it a Faraday Cage, then so it is not confusing in the context of
EMI.

> [Original Message]
> From: steve weir <weirsi@...>
> To: Rose, Michael <mrose@...>
> Cc: Stefan Milnor <stefan.milnor@...>; Lee Ritchey
<leeritchey@...>; Peter zhu <yonghui.sky@...>;
si-list@...
<si-list@...>; jhasson@...m
<jhasson@...>
> Date: 10/31/2010 8:54:23 PM
> Subject: [SI-LIST] Re: Gigabit ethernet placing and routing related
question
>
> There are two important points:
>
> "Ground" is a misnomer.  At RF frequencies the chassis has no special 
> relationship to any potential somewhere in the external environment.  
> The chassis is just a node, and it forms a radiating antenna with all 
> wires that penetrate it.  What makes the chassis special is that one 
> with limited apertures is effective at blocking radiated energy from 
> passing either direction between the inside and the outside.
>
> Coupling differences between signals past the magnetics and the chassis 
> result in mode conversion that aggravates EMI headaches.  Careful 
> attention to mode conversion containment is effort well-spent.
>
>
> Steve.
(Continue reading)

steve weir | 1 Nov 16:52 2010

Re: Gigabit ethernet placing and routing related question

I'm good with calling the chassis the chassis.  It's definitely not got 
anything special to do with the earth, and it's only a decent Faraday 
cage if it has been designed properly.

Best Regards,

Steve.
Lee Ritchey wrote:
> Let's call it a Faraday Cage, then so it is not confusing in the context of
> EMI.
>
>
>   
>> [Original Message]
>> From: steve weir <weirsi@...>
>> To: Rose, Michael <mrose@...>
>> Cc: Stefan Milnor <stefan.milnor@...>; Lee Ritchey
>>     
> <leeritchey@...>; Peter zhu <yonghui.sky@...>;
> si-list@...
<si-list@...>; jhasson <at> rockwellcollins.com
> <jhasson@...>
>   
>> Date: 10/31/2010 8:54:23 PM
>> Subject: [SI-LIST] Re: Gigabit ethernet placing and routing related
>>     
> question
>   
>> There are two important points:
>>
(Continue reading)

Dan | 1 Nov 19:52 2010
Picon

Concatenating S-paramter touchstone file in HSPICE

Hi All
I have touchstone s-parameter (.s4p) files of my input connector, via, trace
and output connector. Now i want to unite these in HSPICE. I used to do a
complete model in HFSS, but since it is a 3d modelling tool, it will take a
long time. That's why i have decided to use HSPICE.

So can anyone help me out in concatenating these touchstone files to a
single touchstone file (.s4p) in HSPICE?

Thank You
Dan

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Siming Pan | 2 Nov 00:10 2010
Picon

design of on-chip PDN

Hi All,
   I have a basic question related to on-chip PDN design. Usually the supply
voltages are designed to be isolated for core, SERDES

 digital, analog, termination, etc. This design may isolate the SSN
couplings among each net. However, usually large on-chip decoupling

 capacitances are used for VDD core circuit. In the board design, we connect
the power nets of VDD_core together with VDD_digital¡£

Thus, switching noises generated from SERDES digital are suppressed by large
on-chip decaps designed for core circuit. However,

package inductances  still play a bad role here to block the conducted path
between noise source formed by digital circuit and core

capacitances. Then why not use one common power net as the supply power for
all the IC circuits, so that large on-chip decaps can be

shared, if the voltage levels are the same?

Regards,

Siming Pan

--

-- 
Siming Pan

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steve weir | 2 Nov 00:23 2010

Re: design of on-chip PDN

Common impedance.

Steve.
Siming Pan wrote:
> Hi All,
>    I have a basic question related to on-chip PDN design. Usually the supply
> voltages are designed to be isolated for core, SERDES
>
>  digital, analog, termination, etc. This design may isolate the SSN
> couplings among each net. However, usually large on-chip decoupling
>
>  capacitances are used for VDD core circuit. In the board design, we connect
> the power nets of VDD_core together with VDD_digital¡£
>
> Thus, switching noises generated from SERDES digital are suppressed by large
> on-chip decaps designed for core circuit. However,
>
> package inductances  still play a bad role here to block the conducted path
> between noise source formed by digital circuit and core
>
> capacitances. Then why not use one common power net as the supply power for
> all the IC circuits, so that large on-chip decaps can be
>
> shared, if the voltage levels are the same?
>
> Regards,
>
> Siming Pan
>
>
(Continue reading)

Xu, Catherine (ICS | 2 Nov 00:36 2010
Picon

Re: design of on-chip PDN

Hi, Siming,

Steve answered well. Using common power net in package design increase risk of:

1) conducted noise due to common impedance coupling - especially for blocks contain tens to a couple
hundred kHz freq
2) increased coupling due to higher mutual inductance 
3) reduced controllability if all power net are tied together

Using dedicated power island with careful decoupling and PDN control is a much better design methodology.

Catherine Xu
__________________________________
Lead HW Design Engineer, Ph.D
HP ICS  CHIL - San Diego
__________________________________ 

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of steve weir
Sent: Monday, November 01, 2010 4:24 PM
To: Siming Pan
Cc: si-list@...
Subject: [SI-LIST] Re: design of on-chip PDN

Common impedance.

Steve.
Siming Pan wrote:
> Hi All,
(Continue reading)

Iliya Zamek | 2 Nov 00:50 2010
Picon

Re: design of on-chip PDN

Siming, 
Core capacitances are not an ideal; therefore, there are still some part of an 
impedance  common  for both power nets that causes the problems. 
Using  common power on PCB for Core and SERDES increases the common impedance 
part more, as Steve noted.

Iliya Zamek 

----- Original Message ----
From: steve weir <weirsi@...>
To: Siming Pan <pansiming86@...>
Cc: "si-list@..." <si-list@...>
Sent: Mon, November 1, 2010 4:23:48 PM
Subject: [SI-LIST] Re: design of on-chip PDN

Common impedance.

Steve.
Siming Pan wrote:
> Hi All,
>    I have a basic question related to on-chip PDN design. Usually the supply
> voltages are designed to be isolated for core, SERDES
>
>  digital, analog, termination, etc. This design may isolate the SSN
> couplings among each net. However, usually large on-chip decoupling
>
>  capacitances are used for VDD core circuit. In the board design, we connect
> the power nets of VDD_core together with VDD_digital¡£
>
> Thus, switching noises generated from SERDES digital are suppressed by large
(Continue reading)

Cosmin Iorga | 2 Nov 01:01 2010
Picon

Re: design of on-chip PDN

Siming,
The on-chip VDD_core capacitance decouples high-frequency spectral components of 
the digital core transient currents that see too much impedance into the PDN 
path to the package and PCB where other decoupling capacitors are placed.   

The incoming noise form the PCB through the power distribution (noise frequency 
components that can make it through the inductive PDN path on the 
chip-package-PCB interface) are typically at enough lower frequency for the 
on-chip core capacitance to be able decouple them efficiently, so they are seen 
almost directly by the core circuits.  

So a common power net would make things worse for the digital core since lower 
frequency spectral components of noise would now pass through the PDN impedance 
into those circuits.  In the same time the core on-chip capacitance will not be 
able to help with decoupling the SERDES injected noise due to the inductance of 
the chip-package-PCB interconnect.

Just a few thoughts...

Cosmin Iorga,
NoiseCoupling.com
http://www.noisecoupling.com

________________________________
From: Siming Pan <pansiming86@...>
To: "si-list@..." <si-list@...>
Sent: Mon, November 1, 2010 4:10:15 PM
Subject: [SI-LIST] design of on-chip PDN

Hi All,
(Continue reading)


Gmane