Amit Agrawal (amiagra2 | 1 Aug 10:33 2010
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Senior Signal Integrity Jobs at Cisco, San Jose, CA

We are looking for a senior level signal integrity engineer in
Enterprise Switching Technology Group (ESTG), Cisco, San Jose. The
position is located in San Jose, CA. The description of the job
requirements are given below. If you are interested, please send your
resume or contact me directly.

Best Regards,

Amit P. Agrawal, Ph.D.

Senior Manager, Hardware Engineering

Enterprise Switching Technology Group

Cisco, San Jose, CA

amiagra2@...

(408) 424-2732 (Office)

__________________________________________________________

JOB DESCRIPTION FOR TECHNICAL LEAD/SENIOR SIGNAL INTEGRITY ENGINEER

An experienced signal integrity engineer is being sought for design and
analysis of high speed interfaces and power distribution network. The
successful candidate will be part of signal integrity technology team
and participate in the definition of chip, package, printed circuit
board (PCB), and system interconnects.  Within a concurrent engineering
environment, the individual will be part of a larger team with system
(Continue reading)

Ramesh N | 2 Aug 07:32 2010
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Re: 6 Layer PCB

Hi Jon,
This link may be useful for you....
http://www.sunmantechnology.com/resources_ec.html
Besides this, I recommend you to get PCB stack-up from your PCB fab house..
Hope this helps you.
Regards,
Ramesh
On Sat, Jul 31, 2010 at 9:15 PM, Jon Bean <jbean@...> wrote:
> Hi
>
>
> Can anyone give me a stack up for a 6 layer pcb of 1.6mm thickness?
>
> I know the layer order I want to use but require the dielectric thickness
> to
> give 50 ohm signals on the signal layers. Ideally I would like the signal
> width to be no more than 0.2mm on those layers and using ½ oz copper for
> the
> signals and 1 oz for the planes.
>
>
>
> Top
>
> Gnd
>
> Sig
>
> Sig
>
(Continue reading)

bala | 2 Aug 14:18 2010
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Re: 6 Layer PCB

Hi Jon,
Use any 2D field-solver,cadence or Mentor's Hyper lynx.You will get the
answer.

On Mon, Aug 2, 2010 at 11:02 AM, Ramesh N <n.rameshhwde@...> wrote:

> Hi Jon,
> This link may be useful for you....
> http://www.sunmantechnology.com/resources_ec.html
> Besides this, I recommend you to get PCB stack-up from your PCB fab house..
> Hope this helps you.
> Regards,
> Ramesh
> On Sat, Jul 31, 2010 at 9:15 PM, Jon Bean <jbean@...> wrote:
> > Hi
> >
> >
> > Can anyone give me a stack up for a 6 layer pcb of 1.6mm thickness?
> >
> > I know the layer order I want to use but require the dielectric thickness
> > to
> > give 50 ohm signals on the signal layers. Ideally I would like the signal
> > width to be no more than 0.2mm on those layers and using ½ oz copper for
> > the
> > signals and 1 oz for the planes.
> >
> >
> >
> > Top
> >
(Continue reading)

Ken Cantrell | 2 Aug 17:07 2010

Re: 6 Layer PCB

Jon,
The only cautionary that I would add to Steve's advice is that board vendors
typically use less advanced software.  Some take frequency effects into
account, some don't.  If you are working below 1GHz, it shouldn't make any
difference.  If you are working at >= 1GHz you will need to choose a vendor
that has the appropriate modeling software.

Ken

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...]On Behalf Of steve weir
Sent: Saturday, July 31, 2010 10:20 AM
To: Jon Bean
Cc: si-list@...
Subject: [SI-LIST] Re: 6 Layer PCB

Jon, there isn't a single answer.  In order to get to a particular
impedance, you need a combination of:

1. Transmission line configuration:  microstrip, symmetric stripline, or
offset stripline
2. Material properties of your dielectric:  primarily eR.
3. Acceptable range of trace widths.
4. Acceptable range of dielectric thicknesses.

Skinnier traces over thinner dielectric will allow you to pack more
traces per linear inch at a given amount of cross-talk. As microstrips,
they will also emit less.  But, they will have more etching variability,
and more skin loss than wider lines of the same impedance.  You need to
(Continue reading)

Chi Tu | 2 Aug 18:16 2010

Re: Netlist or W Elements for HSpice from Cadence Allegro

Hello Mani, 

To clarify, HSPICE does have the ability to use s-parameter models in
simulation by using an S-element. 

1)Here's an example of how to do this for a differential pair s-par
model in Touchstone format:

Sdiffpair inp inn outp outn GND mname=tracemodel

.MODEL tracemodel S TSTONEFILE='../diffpair.s4p' INTDATTYP=RI
INTERPOLATION=LINEAR FMAX <at> GIG FBASE=9.765625Meg

The FMAX is the max frequency point in your touchstone model.

The FBASE relates to the sampling frequency that you tell HSPICE to use
for doing an IFFT to get time-domain data.

There is a nifty S-parameter Appnote on Solvnet that covers this in more
detail.

https://solvnet.synopsys.com/retrieve/017600.html

You can also refer to Chapter 2 of the "hspice_si.pdf manual to learn
about the other s-element options.

2)Also, the W-element does have an option to reference an s-par model
instead of an RLGC file.

Wdiffpair inp inn gnd outp outn gnd smodel=tracemodel 
(Continue reading)

Scott McMorrow | 2 Aug 18:39 2010

Re: Netlist or W Elements for HSpice from Cadence Allegro

chi

I would like to correct you.  You said

'The FMAX  is the max frequency point in your touchstone model.'

This would be incorrect.  FMAX in HSPICE is the maximum frequency used 
in the IFFT to transform from frequency domain back to time domain.  
This is not well documented by Synopsys, but can be verified through 
experimentation.  It is generally related to the final time domain delay 
resolution by 1/FMAX.  Generally FMAX must be set much higher than the 
maximum bandwidth used in your touchstone files, otherwise you will 
obtain incorrect time domain simulations.  The simulator will use an 
undefined algorithm to window and pad the frequency domain data that is 
beyond the bandwidth of your touchstone file.

Sparameter cascading in HSPICE, or any other tool for that matter, is 
problematic at best.  I'd suggest that you perform experiments with 
multiple lengths of transmission lines transformed to touchstone files 
to determine if you have any interactions between Fmax,  Fbase, 
s-parameter sampling, number of segments in the cascade, and ultimately 
the unit impulse response.

regards,

Scott

--

-- 

Scott McMorrow
(Continue reading)

Inmyoung Song | 3 Aug 01:44 2010
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Re: Netlist or W Elements for HSpice from Cadence Allegro

Hello Mani,
How about use spc2spc in cadence?
After that command we can get the main_gen.spc which is spice netlist.
You can edit or open the text editor and can't miss the .subckt syntax...
If you more information let me know, I show you an example...

2010/8/3 Chi Tu <Chi.Tu@...>

> Hello Mani,
>
>
> To clarify, HSPICE does have the ability to use s-parameter models in
> simulation by using an S-element.
>
>
>
> 1)Here's an example of how to do this for a differential pair s-par
> model in Touchstone format:
>
>
>
> Sdiffpair inp inn outp outn GND mname=tracemodel
>
> .MODEL tracemodel S TSTONEFILE='../diffpair.s4p' INTDATTYP=RI
> INTERPOLATION=LINEAR FMAX <at> GIG FBASE=9.765625Meg
>
>
>
> The FMAX is the max frequency point in your touchstone model.
>
(Continue reading)

Karthik P | 3 Aug 19:02 2010
Picon

Difference between IC Package and HDI Packages


 Hi Si-list,

I would like to know the difference between IC package and HDI packages. I have worked lot of flipchip and
wirebond designs, PoP and 3D designs. but would like to know that is HDI package or normal Package layout.

 The constraint used for the flipchip design are trace width less than a mil, micro via size 110/60um and
bump pitch is about 160um. Whether these are the factors decide about the package layout is HDI package? or
it is about manufacturing process?

 I will be thankful if anyone share sample HDI package layout or layout guidelines

Regards
Karthik

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steve weir | 3 Aug 22:29 2010

Re: Difference between IC Package and HDI Packages

HDI is most often used as a PCB level term that loosely refers to Z axis 
interconnects that are not full through hole, ie include blind and 
buried Z axis interconnects.  You can download the HDI Handbook for free 
from PCB007

http://www.hdihandbook.com/

Steve.
Karthik P wrote:
>  Hi Si-list,
>
> I would like to know the difference between IC package and HDI packages. I have worked lot of flipchip and
wirebond designs, PoP and 3D designs. but would like to know that is HDI package or normal Package layout.
>
>  The constraint used for the flipchip design are trace width less than a mil, micro via size 110/60um and
bump pitch is about 160um. Whether these are the factors decide about the package layout is HDI package? or
it is about manufacturing process?
>
>  I will be thankful if anyone share sample HDI package layout or layout guidelines
>
> Regards
> Karthik
>
>
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@... with 'unsubscribe' in the Subject field
>
(Continue reading)

Doug Smith | 4 Aug 06:28 2010

website work and new webex class

I am preparing my new Technical Tidbit for the month and should have it 
posted in a day or so (things hectic around here with upcoming wedding 
of my daughter and youngest son home on leave from the Army).

In addition, I am holding a repeat s of my WebEx troubleshooting class 
as a number of people were on vacation the first time around. This is a 
90 minute WebEx session that is not a free advertising session but a low 
cost training session (I do not sell hardware or software) on finding 
PCB and IC weak spots in designs. If interested, the link to the 
description is:

http://emcesd.com/pdf/webexsem_082310.pdf

Doug

--

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      \          / )      P.O. Box 1457
       =========          Los Gatos, CA 95031-1457
    _ / \     / \ _       TEL/FAX: 408-356-4186/358-3799
  /  /\  \ ] /  /\  \     Mobile:  408-858-4528
|  q-----( )  |  o  |    Email:   doug@...
  \ _ /    ]    \ _ /     Website: http://www.dsmith.org
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Gmane