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steve weir | 1 Feb 2010 01:12

Re: follow up: Re: Query about Oscillator problem

Li, with all due respect you are wrong.  Type 1:  NPO/C0G capacitor 
dielectric has a much lower K, lower dielectric loss, and lower ESR for 
any like size and value capacitor compared to a capacitor made from Type 
2, or Type 3 dielectric.  The typical ESR difference is in the 4:1 to 
6:1 range.  That means that in addition to the temperature stability 
they are much higher Q for the same package size / value combination.

Steve

Li, Tianqi . (S&T-Student) wrote:
> Hi Steve
>
> NO. They primarily have very different TCC. Please check the Temperature
> Coefficient plot of NPO, X7R, Y5V, via following link
> http://www.koaspeer.com/pdfs/cap8.pdf
>
> In addition, to the PLL power capacitors, what you said may be true. But
> it should be analyzed based on specific case details. Actually one of my
> former design experienced a similar temp. problem (PLL lose lock every 3
> days during temp. variation test) and I changed to NPO on PLL power pins
> and the problem never come again.
>
> Tianqi Li
>
> -----Original Message-----
> From: steve weir [mailto:weirsi@...] 
> Sent: Sunday, January 31, 2010 5:21 PM
> To: Li, Tianqi . (S&T-Student)
> Cc: chundi srikanth; si-list@...
> Subject: Re: [SI-LIST] follow up: Re: Query about Oscillator problem
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Hany Fahmy | 1 Feb 2010 01:55
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Re: DDR2 to Virtex 5 heating up and a few other questions

To add for below: output drive strength should be programable on sdram side and also on Virtex side, do u have
drive strength Ron control on Virtex side?
On sdram side, u can even choose half drive strength which meant to be used for low-power operation. 

Hany Fahmy

----- Original Message -----
From: si-list-bounce@... <si-list-bounce@...>
To: charlene radtke <chuckiesanchez@...>;
si-list@... <si-list@...>
Sent: Sun Jan 31 12:44:07 2010
Subject: [SI-LIST] Re: DDR2 to Virtex 5 heating up and a few other questions

Hi Charlene,

If outputs are driving into terminated lines, which I presume they are, then more power will be dissipated
in the output driver if the drivers are configured as class-II drivers versus class-I drivers. The
"class" has to do with the drive strength. Furthermore, the series resistors that you used in your first
design would limit output current, leading to reduced power dissipation. 

Both of these factors - use of class-II drivers and removal of series resistors - would lead to higher power
dissipation in the second design.

Regards,

Frank

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of charlene radtke
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LIU Luping | 1 Feb 2010 03:26
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Re: The necessity of Pull-up resistors in DDR2

Hi Hirshtal,
   I  totally agree with the reply  above ,and with some additional words on the timing effect of VTT.

The VTT can improve the skew between signals, may  be not a big issuse in  DDR2 CMD/ADD,but will be critical in 

other high speed interfaces, like TCAM.

Best Regards, 
LIU Luping 
CAD/SI Engineer 

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chundi srikanth | 1 Feb 2010 09:50
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Decoupling capacitors selection

Hi Friends,
Iam little bit confused in the selection of right decoupling capacitor for
my application. Iam using Freescale Coldfire MCF5208 processor. The
processors core is running at 166.66MHz and its Memory bus is operating at
83.33MHz. In my board i have a Virtex-5 FPGA for CPRI protocol and
interfaces to high-speed DAC, ADC. And i have a RF circuitry also. So my
question is Whats the main criteria for selecting decoupling capacitors for
this processor?Is there any formula to calculate the capacitance for this.
Please give me your suggestion on this. And shall i keep a capacitor per pin
or otherway?

And i have seen the MCF5208 processor evaluation board which theye are using
in Zigbee environment but they have placed very few caps of 0.1uF. Nothing
else. Can i follow the same?

Thanks & Regards
Sree

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Hirshtal Itzhak | 1 Feb 2010 10:02
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Re: The necessity of Pull-up resistors in DDR2

Ted,

You're right regarding the timing issue.

The reason I'm quite sure about timing is that the bus is supposed to
work with the low frequency of 200MHz Clock

Itzhak

-----Original Message-----
From: Todd Westerhoff [mailto:twesterh@...] 
Sent: Sunday, January 31, 2010 4:52 PM
To: Hirshtal Itzhak
Cc: si-list@...
Subject: Re: [SI-LIST] The necessity of Pull-up resistors in DDR2

Hirshtal,

Signal integrity is all about getting an adequately clean signal to a 
receiver input in time to meet setup and hold requirements. 

DDR2 drivers have active pullup/pulldown stages; you don't _need_  a 
resistor  in the circuit to drive the signal high and low.

DDR2 address and control lines are often multi-drop, termination is used

to maintain signal integrity by controlling reflections.  The signal is 
terminated to VTT (=VDD/2) to minimize duty cycle distortion. 

If your signal integrity simulations suggest termination isn't needed,
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steve weir | 1 Feb 2010 10:27

Re: Decoupling capacitors selection

Sree, there is no pat answer.  Books have been written on this.  If you 
think that the evaluation board is physically representative of your 
application:  You are going to copy it's stack-up and power layout, and 
you are going to exercise the chips the same on your board almost the 
same as on the evaluation, and you are confident that the evaluation 
board is reliable across your application environment, then you can copy 
that implementation.  Otherwise you have work to do that companies like 
Sigrity or Mentor would love to assist you with by selling you $50K of 
software per seat.

To intelligently address your question, for power delivery only you 
would want to know the impedance profile versus frequency required at 
the chip attachment to the PCB.  Then you could apply some physics and 
electrical engineering to meet that set of requirements.

To answer your question for signal returns, you need to know the spectra 
and amplitude of the return currents that must traverse your PDN.  Then 
again you can apply some physics and electrical engineering to arrive at 
an answer.

If you need to learn what to do yourself, and want to learn to do it 
properly you can begin with:

Istvan Novak's website:  www.electrical-integrity.com 
<http://www.electrical-integrity.com>  has a number of papers and book 
links.
You would do well to read almost anything on the topic written by Dr. 
Bruce Archambeault.
Xilinx offers "cookbook" power delivery network specifications for the 
Virtex 5 and later FPGAs.  It is useful, but deserves some caution and
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André M. Grabinski | 1 Feb 2010 10:32
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Deadline Extension - Signal Propagation On Interconnects (SPI 2010)

+++ Please consider the following announcement and accept our apologies 
in case of multiple copies. +++

============================
 >> DEADLINE-EXTENSION <<
CALL FOR PAPERS (SPI 2010)
============================

At the request of a great many of potential authors we have decided to 
extend the deadline for paper submission:

 >> The NEW DEADLINE for PAPER SUBMISSION is now FEBRUARY 15, 2010. <<

==================================================================================
14th IEEE Workshop On
SIGNAL PROPAGATION ON INTERCONNECTS
-----------------------------------
Sponsored by the IEEE Computer Society – Test Technology Technical 
Council (TTTC)
and by the IEEE Components, Packaging, and Manufacturing Technology 
(CPMT) Society
May 09-12, 2010 - “Van der Valk Hotel” - Hildesheim, Germany

=========================================
WEBSITE: http://www.spi.uni-hannover.de
=========================================

ABOUT THE SPI-WORKSHOP:
-----------------------
During the last thirteen years, the IEEE Workshop on Signal Propagation
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Hirshtal Itzhak | 1 Feb 2010 13:38
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Re: ILTAM- Seminar on EMC and Signal Integrity Considerations in the design of High Speed/High Density Printed Circuit Board 9/2/10

ùìåí çâéú

áùìá æä ìà ðøàä ùàåëì ìäùúúó áéåí äòéåï ò÷á äúçééáåéåú ÷åãîåú

úåãä

àéöé÷ äéøùèì

________________________________

From: Hagit - ILTAM [mailto:hagit@...] 
Sent: Monday, February 01, 2010 9:44 AM
To: Hirshtal Itzhak
Subject: ILTAM- Seminar on EMC and Signal Integrity Considerations in the design of High Speed/High
Density Printed Circuit Board 9/2/10

àéöé÷ ùìåí, 

áäîùê ìùéçúðå äèìôåðéú, îö"á úæëåøú ìéåí äòéåï ùðòøåê
áúàøéê 9/2/10 òí àéìéä éôä áðåùà:  

EMC and Signal Integrity Considerations in the design of High Speed/High Density Printed Circuit Board""

àðà áãå÷ äàí äðåùà øìååðèé òáåøê. 

àùîç áàí úåëì ìäòáéø ìòåáãéí ðåñôéí ùäðåùàéí äàìå
øìååðèééí òáåøí. 

ááøëä, çâéú
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Hirshtal Itzhak | 1 Feb 2010 14:51
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FW: FW: The necessity of Pull-up resistors in DDR2

Hello all

There has been some "private" discussion about this topic and I forward it to the forum, for your comments.

Thanks and Best Regards

Itzhak

________________________________

From: Hermann Ruckerbauer
[mailto:hermann.ruckerbauer@...] 
Sent: Monday, February 01, 2010 1:50 PM
To: Hirshtal Itzhak
Subject: Re: FW: [SI-LIST] The necessity of Pull-up resistors in DDR2

Hi Itzhak,

Your last comment is correct and exactly what I wanted to mention.

If you would provide a Midlevel voltage to an active receiver this could cause problems (I wouldn't see that
it will destroy anything, but cause some strange crosscurrent and some internal undefined switching). 
But the DRAMs do have a protection to switch the receivers only on if they are really needed (e. g. non power
down, or activation due to chipselect). 

So the midlevel is not a problem on a DRAM. 

regards

Hermann
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joe jose | 1 Feb 2010 16:52
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Split power plane crossing for high freq signal

Techies,
In one of my latest design we are using DDR3 and in the layout there is a
split power planes for the Data signals. Can any body suggest me how I can
choose the stitching cap for these application. Is there any articles for
these.

DDR3-1333 data rate.

-Joe

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