Dale Becker | 1 Oct 02:23 2009
Picon

EPEPS: Oct 19-21 Portland, OR


Dear Si-List,

Just a reminder that the 2009 IEEE EPEPS (Electrical Performance of
Electronic Packaging and Systems) is Oct. 19-21 in Portland, OR.

The program, registration and other conference information is at
http://epeps.org.

Please note the special programming for this year includes three
embedded tutorials.

Monday Tutorial
Fundamentals of Macromodeling for Signal Integrity Analysis
Presented by: Dr. Piero Triverio, Politecnico di Torino and Dr. Michel
Nakhla, Carleton University

Tuesday Tutorial
Fundamentals and Advances in Jitter Analysis of High-Speed Links
Presented by: Dr. Lei Luo, Rambus

Wednesday Tutorial
Challenges in Measuring High Speed Links
Presented by: Dr. Kathleen Melde, University of Arizona and Terry Burcham,
Cascade Microtech

In addition on Sunday afternoon, Oct. 18 is this year's edition of
FDIP (Future Directions in IC and Package Design) and the agenda for
that program is on the Courses/Workshop tab at the EPEPS website,
http://epeps.org.
(Continue reading)

Picon

Re: return planes in mixed analog/digital system

Hi Gene,

Please look at the article, http://www.analog.com/static/imported-files/analog_dialogue/5467026043687049331665676350Grounding.pdf
This paper talks about Analog / Ground planes separation especially when used with ADC / DACs.
Hope it helps.

Thanks,
Sriram SR

If you are unable to see the link, Google " GROUNDING IN HIGH SPEED SYSTEMS site: analog.com".

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of Gene Glick
Sent: Wednesday, September 30, 2009 9:02 PM
To: si-list@...
Subject: [SI-LIST] return planes in mixed analog/digital system

(resend, sorry if it's a duplicate)

I'm not quite sure how to write this in a way that makes sense, but here
goes -

This design contains a mix of audio and digital circuits.  Audio is
obviously low frequency stuff, but it is in particular meant to be high
quality audio, so cross-talk is very important.  The digital stuff is
primarily for the ADC and DAC circuitry running in the vicinity of 25 MHz.
Due to how the layout has progressed, I am at a crossroads in the power
and ground plane topology.  Without drawing pictures, this may be tough
to visualize.  Take the DAC circuitry for example.  It has separate
(Continue reading)

HU Jun | 2 Oct 15:36 2009
Picon

Updates of APEMC 2010 in Beijing: Paper Submission Deadline Extended to Oct. 26; Program of Workshops & Tutorials Announced.

Updates of APEMC 2010 in Beijing 
2010 Asia-Pacific  International Symposium on Electromagnetic Compatibility
(APEMC)

Beijing, China , April 12-16, 2010

As number of authors requested to push back the submission date, the
organising committee are pleased to announce the below notification: The
preliminary paper submission date has been extended to Oct. 26, 2009. Please
contribute your paper to the conference through the paper submission portal
when it is still open. DO NOT miss the great event of APEMC 2010.

 <https://www.apemc-beijing.ethz.ch/subm_portal.php>
https://www.apemc-beijing.ethz.ch/subm_portal.php

Or www.apemc2010.org/ paper submission

Or www.emc-zurich.org/ paper submission

The program of Workshops & Tutorials is available on the website. Please
visit the below address for details and contact with us if you have any
question.

www.apemc2010.org/ Symposium Programme

Or www.emc-zurich.org/ Symposium Programme

For more information, please visit the conference web:
<http://www.apemc2010.org/> www.apemc2010.org  or www.emc-zurich.org 

(Continue reading)

Karthik | 3 Oct 19:55 2009
Picon

Regarding setup procedure for Xtalk generation

Hi, folks,

 Can somebody help me in finding out the correct procedure for generating Crosstalk analysis using Cadence Allegro.

 I have generated the report, but not quite sure about the procedure what i have followed is right.

 In report, i would like to know the difference of HSOddXtalk  HSEvenXtalk  LSOddXtalk  LSEvenXtalk and which
value have to be considered and then it is right to choose Aggr XNet as source and have to increase the
spacing of neighbour nets?

 Next, while setting up the constraints, how to select fastest Driver of the net and in aggressor it should be
like odd mode or even mode.

Thanks
Karthik

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@... with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@... with 'help' in the Subject field

List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
(Continue reading)

Kenneth W. Egan | 3 Oct 20:06 2009
Picon

Re: Regarding setup procedure for Xtalk generation

Fastest way is contact your local Cadence support.

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of Karthik
Sent: Saturday, October 03, 2009 12:56 PM
To: si-list@...
Subject: [SI-LIST] Regarding setup procedure for Xtalk generation 

Hi, folks,

 Can somebody help me in finding out the correct procedure for generating
Crosstalk analysis using Cadence Allegro.

 I have generated the report, but not quite sure about the procedure what i
have followed is right.

 In report, i would like to know the difference of HSOddXtalk  HSEvenXtalk
LSOddXtalk  LSEvenXtalk and which value have to be considered and then it is
right to choose Aggr XNet as source and have to increase the spacing of
neighbour nets?

 Next, while setting up the constraints, how to select fastest Driver of the
net and in aggressor it should be like odd mode or even mode.

Thanks
Karthik

------------------------------------------------------------------
(Continue reading)

Michael Rose | 5 Oct 18:35 2009

f-domain to t-domain simulation

When I convert a f-domain channel to differential t-params (TDD11), I
notice the impedance rising along a transmission line segment as if the
tline is predominantly inductive. This tends to bias the impedance
higher for features towards the far end. The single-ended f-domain
channel includes the normal 50 ohm terminations. Is this a real
phenomena? How is it explained?

Thanks. Mike  
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@... with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@... with 'help' in the Subject field

List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
		http://www.freelists.org/archives/si-list
or at our remote archives:
		http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
 		http://www.qsl.net/wb6tpu

Scott McMorrow | 5 Oct 18:45 2009

Re: f-domain to t-domain simulation

Michael

Yes, it is real, as any TDR of a channel will tell you.  It is a 
combination of increasing DC channel resistance, and increasing loop 
inductance at lower frequencies - as the signal penetrates more deeply 
into the conductors.

regards,
Scott

-- 
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC

Michael Rose wrote:
> When I convert a f-domain channel to differential t-params (TDD11), I
> notice the impedance rising along a transmission line segment as if the
> tline is predominantly inductive. This tends to bias the impedance
> higher for features towards the far end. The single-ended f-domain
> channel includes the normal 50 ohm terminations. Is this a real
> phenomena? How is it explained?
(Continue reading)

Bob Ross | 5 Oct 21:03 2009

Asian IBIS Summit (Japan) Third Announcement

To All:

The IBIS Open Forum will hold its fourth Asian IBIS Summit (Japan)
Meeting on November 6 in Tokyo, Japan.  This year we are starting
Friday afternoon, but still expect a full program.  We have moved
the check in time to 13:30.

JEITA (Japan Electronics and Information Technology Industries
Association) is the primary event sponsor with several companies,
to be listed below, acting as co-sponsors.  The event will held
at JEITA headquarters in Tokyo.  Several experts from outside of
Japan are expected to participate.

We encourage technical contributions from Asia.

Note that we are also holding a Summit in Shanghai, People's Republic
of China on November 4.  You may want to consider this in your travel
plans.

Bob Ross
Teraspeed Consulting Group

Takeshi Watanabe
NEC Electronics Corporation

-----------------------------------------------------------------------
                          ASIAN IBIS SUMMIT (JAPAN)
                               THIRD CALL FOR
                       PARTICIPATION AND PRESENTATIONS
-----------------------------------------------------------------------
(Continue reading)

BO-LIAO | 6 Oct 02:24 2009
Picon

Re: AW: Control Impedance testing

Dear All,
 
Thank you for your response and advise.
 
We had verified both coupon and on-board testing control impedance. It was not easy to test on actual board,
as the board did not have proper test pads. Nevertheless, the result come close to 2%, which is acceptable
for us.
 
We have requested 4x coupons around the panel, hoping for better representation of the actual boards.
 
Will monitor further to comment.
 
Thank you!
 
Best regards,
Liao Bo
--- On Tue, 15/9/09, Leonard Dieguez <ldieguez@...> wrote:

From: Leonard Dieguez <ldieguez@...>
Subject: [SI-LIST] Re: AW: Control Impedance testing
To: "Istvan Novak" <istvan.novak@...>, "Lee Ritchey"
<leeritchey <at> earthlink.net>, "si-list@..." <si-list@...>
Date: Tuesday, 15 September, 2009, 8:17 AM

Istvan,

While your statements have good advice, if you compare test coupons to integrated test traces to be
functionally used as test coupons, I would vote for the integrated PCB test traces.

In general you can get more coverage and design the test traces to have various angles a routing that will
(Continue reading)

Istvan Novak | 6 Oct 02:47 2009
Picon
Picon

Re: f-domain to t-domain simulation

Michael,

In addition to the fact that losses will result in a rising impedance 
profile, artifacts and conversion
errors can also create similar effects, so you need to sanity check the 
numbers you get.  The
TDR-like time-domain response requires an integral of the impulse 
response, and any residual
plateau in the impulse response (if the translation from frequency to 
time domain is done
incorrectly) will result in a similar monotonic rise of the calculated 
impedance profile.

Regards,

Istvan Novak
SUN Microsystems

Michael Rose wrote:
> When I convert a f-domain channel to differential t-params (TDD11), I
> notice the impedance rising along a transmission line segment as if the
> tline is predominantly inductive. This tends to bias the impedance
> higher for features towards the far end. The single-ended f-domain
> channel includes the normal 50 ohm terminations. Is this a real
> phenomena? How is it explained?
>
> Thanks. Mike  
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@... with 'unsubscribe' in the Subject field
(Continue reading)


Gmane