Robert Sefton | 1 Feb 01:38 2009

Re: Dividing a low jitter clock by 2

This is not directly applicable to Marc's situation but close enough that I
thought I'd share it. I'm currently working on a design involving a PLL that
synthesizes the RF carrier for a satellite modem. The phase noise
requirements are extremely tight. An FPGA is involved to tune the PLL (a
Hittite fractional-N synthesizer chip) and control a bunch of filters, etc.,
but the initial design also used the FPGA to divide a clock and do some
muxing to select the reference clock for the PLL. The FPGA does not use a
PLL internally - just flip flops and gates to divide and mux the reference
clock. So you would not expect the FPGA to inject a lot of noise. But it
ended up that the miniscule amount of phase noise the FPGA did introduce
resulted in a 10 dB degradation in the phase noise on the RF carrier out of
the PLL (in the GHz range). We are now moving those dividers and muxes to
discrete logic outside the FPGA.

This is one of those things that was impossible to quantify beforehand.
There are no data to base the analysis on. You just have to try it and see
how it turns outs. We're pretty confident that the external logic will do
the trick (this is more along the lines of Marc's original question). As a
side note, the clock we're dividing is between 150-200MHz and we have to do
a /3, which requires both edges of the clock to fix the duty cycle. So the
flip-flops need to be rated for well over 300MHz. This is basically
impossible to do with any discrete CMOS logic family. But we came across a
new company called Potato Semiconductor (potato chips - get it?), who make
an incredible CMOS logic family they call "GHz 74 Series Logic". Thought I'd
toss that out there because nobody I've mentioned this to has heard of
Potato Semi.

Good luck, Marc. I agree with your approach below.

Bob S.
(Continue reading)

Zhangkun | 1 Feb 02:39 2009

答复: Failed Tantalum capacitors - package hermeticity compromised

Steven

Which kind of product or board do you apply the Tantalum capacitors in? I
have met two kind of cases in whch the Tantalum capacitor failed.
   1. The backplane. When the connector is pressed on the backplane, the
capacitor catches great stress.
   2. The power module. Because the PCB is too small, several PCB are
assembled together and are seperated later. While seperating, the capacitor
catches great stress.
Hope this is helpful for you.

Best Regards

Zhangkun
2009.2.1

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Recently we have had some tantalum capacitors rated at 16V fail on turn of
in a 12V circuit. While some percentage of low ESR capacitors experience a
high surge infant mortality on first turn on unless serrated by 50% or more,
(Continue reading)

Barry Katz | 1 Feb 15:36 2009

SiSoft at DesignCon 2009

Hi All,

If you are planning to attend DesignCon, we would like to make you aware 
of the presentations SiSoft will be delivering at DesignCon and hope you 
will be able to set aside some time in your schedule to join us.

Technical Panel:
"Power Distribution Planes: To Split or Not to Split?"
http://www.sisoft.com/dc09_1_tp_m3.htm -  February 2, 2009

Papers:
"Comparison of BER Estimation Methods That Account for Crosstalk"
http://www.sisoft.com/dc09_8_tp_1.htm - February 3, 2009

"A Simple Via Experiment"
http://www.sisoft.com/dc09_5_tp_2.htm - February 3, 2009

DesignCon 2009 IBIS Summit
http://www.eigroup.org/ibis/events.htm - Thursday, February 5, 2009
"Creating Broadband Analog Models for SerDes Applications"

--

-- 

Barry Katz
President/CTO
Signal Integrity Software, Inc. (SiSoft)
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Tel: 978 461-0449 ext. 19
Fax: 978 461-5092
(Continue reading)

Bharathi | 2 Feb 04:39 2009

Re: Dividing a low jitter clock by 2

Marc,

Looks like the link is not working. 

Points to be noted:

1. When the junction temperature of the IC goes up, it will introduce
jitter. So please look for an IC whose jitter spec is characterized across
temperatures
2. Digital traces terminated and shielded.
3. Place the D FF close to the PLL
4. No via's or test points on  the clock pins (FF clock, PLL clock)
5. Use an EMI filter for Power supply stability 

Hope this helps

Regards
Bharathi
Tessolve Services Pvt. Ltd
11/7, 10th Street, Dr VSI Estate
Thiruvanmiyur
Chennai 600041
Tel: +91-44-43357111
bharathi@...

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of Marc Battyani
Sent: Sunday, February 01, 2009 1:17 AM
(Continue reading)

Hirshtal Itzhak | 2 Feb 16:03 2009
Picon

Allowed Crosstalk on DDR2 Strobe (DQS)

Hello all,

I would like to ask if there is any specification which claims the
amount of allowed crosstalk on the (single-ended or differential) DQS of
the DDR2 interface.

As I understand it, assuming the signal is generally well behaved (no
significant overshoot or ringing and is monotonic throughout its
threshold region), then the crucial thing is what happens if and when a
noise from another signal happens to ride on top of the DQS signal -at
the time of its threshold transfer region. This event may cause the
signal to be non-monotonic and this seems to me the worst threat to the
signal functioning.

But what level of crosstalk will cause such non-monotonicity to disrupt
the signal functionality? At principle, any level should be dis-allowed,
even 1mV! But this seems to be un-reasonable, as on embedded
applications the routing is so dense this isn't an achievable goal.

Could anyone answer this question - from the DDR2 specification or from
any electrical reasoning?

Thanks in advance

Itzhak Hirshtal

 The information contained in this communication is proprietary to Israel Aerospace Industries Ltd.,
ELTA Systems Ltd. 
and/or third parties, may contain classified or privileged information, and is intended only for 
the use of the intended addressee thereof. If you are not the intended addressee, please be aware 
(Continue reading)

Peter zhu | 2 Feb 19:46 2009
Picon

Re: Allowed Crosstalk on DDR2 Strobe (DQS)

The DQS in DDR2 become differential, it means it is better immune from
crosstalk.  DQS and DQS# always can get clean data strobe signal.
I think you may never find the allowable crosstalk level on DQS signal,
digtal system is not analog system. Usually, design guide will specify 3H or
higher (H-distance form signal to reference plane) spacing requirement to
reduce the adjacent crosstalk. For board designer, this is the most
important way to reduce the crosstalk.
Peter
Emerson

On Mon, Feb 2, 2009 at 11:03 PM, Hirshtal Itzhak <ihirshtal@...>wrote:

> Hello all,
>
> I would like to ask if there is any specification which claims the
> amount of allowed crosstalk on the (single-ended or differential) DQS of
> the DDR2 interface.
>
> As I understand it, assuming the signal is generally well behaved (no
> significant overshoot or ringing and is monotonic throughout its
> threshold region), then the crucial thing is what happens if and when a
> noise from another signal happens to ride on top of the DQS signal -at
> the time of its threshold transfer region. This event may cause the
> signal to be non-monotonic and this seems to me the worst threat to the
> signal functioning.
>
> But what level of crosstalk will cause such non-monotonicity to disrupt
> the signal functionality? At principle, any level should be dis-allowed,
> even 1mV! But this seems to be un-reasonable, as on embedded
> applications the routing is so dense this isn't an achievable goal.
(Continue reading)

Mirmak, Michael | 2 Feb 23:09 2009
Picon

Call for IBIS 5.0 parser development bids!


The IBIS Open Forum has recently approved the IBIS 5.0 specification.  To aid industry adoption, the Open
Forum would like to release a "golden parser" for IBIS 5.0 models, as it has for IBIS 4.2 and previous
versions.  We are therefore soliciting bids from software developers to upgrade the existing parser to
support IBIS 5.0 syntax.

Alterations to IBIS are approved through BIRDs (Buffer Issue Resolution Documents) which describe the
changes in detail.  The new parser must support the updates in IBIS 5.0 as described in the BIRDs below:

	BIRD74.6      EMI Parameters
	BIRD95.6      Power Integrity Using IBIS
	BIRD98.3      Gate Modulation Effect (Table Format)
	BIRD103.1     [Model Spec] DDR2 Overshoot/Undershoot Parameters      
	BIRD104.1     Algorithmic Modeling API (AMI) Support in IBIS
	BIRD106       Clarification on Signal_pin Parameters
	BIRD107.2     Update to Algorithmic Modeling API (AMI) Support in IBIS

The full text of each of the BIRDs can be found at:

    http://www.eda.org/ibis/birds/

Please refer to the IBIS Version 5.0 specification for the final text of these features.  The document can be
found at:

    http://www.eda.org/ibis/ver5.0/

We are seeking an estimate of the time and cost of developing an IBIS 5.0 parser, plus additional modules,
according to these requirements.  Compatibility with previous versions is required and the use of
current parser source code is assumed.  Note that the source for the parser is not distributed except under
paid license from the IBIS Open Forum. 
(Continue reading)

Ritesh @ Reliant EDS | 3 Feb 10:34 2009

Request for IBIS models

Dear All,

We need IBIS models for the following components:

54HC00J_M : 54HC00/74HC00

54HC166_M: 54HC166/74HC166

54HC244_12: 54HC244/74HC244

54HC4049_M: 54HC4049/74HC4049

54HC4050_M: 54HC4050/74HC4050

54HC74A_M : 54HC74/74HC74

54HC is Space grade while 74HC is commercial grade. Any one will do.

We also require for:

74AC126/SO

DS90C031_FP

M67204E_M

Pl. send us incase you have any of the above mentioned models,

Thanks in advance,

(Continue reading)

Ralf Brüning | 4 Feb 15:14 2009
Picon

European IBIS Summit <at> DATe 2009 - First Call for Participation

 European IBIS Summit  <at>  DATe 2009 - First Call for Participation

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Ralf Brüning | 4 Feb 16:35 2009
Picon

European IBIS Summit <at> DATe 2009 - First Call for Participation

To All: 
 European IBIS Summit  <at>  DATe 2009 - First Call  for Participation
 ================================================================

We have been holding successful European IBIS Summit Meetings for more then 10 years.  This year we are again
holding a meeting along with DATe 09 on Thursday, April 23rd, 2009.  The purpose is to promote
communication among users and developers of IBIS models in Europe. 

The meeting is free and open to everyone.

Below is some information on the IBIS Summit and some related events. Even despite the current economic
situation you are hereby invited to register to attend and also to submit presentation proposals.

  Ralf Bruening
  Product Manager High Speed Design Solutions
  ZUKEN EMC Technology Center 

-----------------------------------------------------------------
      E U R O P E A N   I B I S   S U M M I T   M E E T I N G 
          F I R S T   C A L L   F O R  P A R T I C I P A T I O N
----------------------------------------------------------------- 

Time/Date:     8:30 - 12:30, Thursday, April 23rd, 2009  
               (this year on Thursday morning, NOT on Friday !).

Location:  Novotel Nice Centre
               (Across the street from Nice-Acropolis Congress and Exhibition Center)
               Meeting-Room: "to be announced"
               8/10 Parvis de l'Europe
               06300 NICE
(Continue reading)


Gmane