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Dimiter Popoff | 1 Sep 2008 15:20
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Will a DPAK (TO263) hang on?

Not the most sophisticated of all SI issues, but one I wonder about
at the moment.
Does anyone know if a DPAK, TO263 (a MOSFET inside) will 
stick to the board bottom side during reflow because of the surface
tension of the solder alone?

Dimiter 

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Dimiter Popoff               Transgalactic Instruments 

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Mohamad Haghtalab | 1 Sep 2008 16:32
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SPICE model extensions

Hi all
 
I have many files that are called Spice model files,*.sp (HSPICE),*.cir,*.spc,*.inc .....
 
What's the differece between them?,for example between spice macro model and other type of spice models?
 
what's the application of each type?
 
Thanks and Regards 

      
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steve weir | 1 Sep 2008 21:45

Re: Will a DPAK (TO263) hang on?

The solder paste s/b enough for DPAK and D2PAKs.

Steve.
Dimiter Popoff wrote:
> Not the most sophisticated of all SI issues, but one I wonder about
> at the moment.
> Does anyone know if a DPAK, TO263 (a MOSFET inside) will 
> stick to the board bottom side during reflow because of the surface
> tension of the solder alone?
>
> Dimiter 
>
> ------------------------------------------------------ 
> Dimiter Popoff               Transgalactic Instruments 
>
> http://www.tgi-sci.com 
> ------------------------------------------------------
> http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@... with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
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Andrew Ingraham | 1 Sep 2008 22:07
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Re: SPICE model extensions

> I have many files that are called Spice model files,*.sp
> (HSPICE),*.cir,*.spc,*.inc .....
>
> What's the differece between them?,for example between spice macro model
> and other type of spice models?

In SPICE, the file extension or type is relatively unimportant.  People use
what they feel comfortable with, and are often free to change the file
extension, though some programs might insist on certain file extensions.

*.sp, *.spi, *.cir usually refer to SPICE input files (*.spc might be
another one of them), and there may be no difference between them.  A full
SPICE input file would contain, in human-readable format, a full description
of the circuit to be simulated, including any necessary model definitions,
plus SPICE directives to tell it how and what to simulate.

*.inc is a portion of a SPICE input file, perhaps containing subcircuits or
models, meant to be included (or called by) another SPICE input file.

*.lib is a library or collection of models or subcircuits, but different
simulators may use them in specific ways.  A *.lib file might be just like
a *.inc file, or it might have a certain structure, depending on the
particular SPICE simulator using it.  (Consult your simulator's manual.)

*.spo, *.lis, *.out usually refer to SPICE output files that are readable
text.

*.raw may be an output file that contains raw or binary data.  It might be a
binary file, or perhaps ASCII but with the data packed in a format not meant
to be human-readable.  Usually meant to be read by some sort of
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Lynne D. Green | 2 Sep 2008 01:01
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Re: SPICE model extensions

Hello, Mohamad,

INC files are included as lines in the SPICE file.  In other words, the
entire INC file replaces the one INC line.  The file extension is typically
inc or mod, as in "include1.inc" or "include2.mod".  The LIB statement works
the same way; model library files often have an extension of .lib.

The other extensions you list apply to SPICE netlist files.  A tool's
"standard" extension can be left off when sending the file to simulation.
As you noted, one can use "hspice x.sp" or "hspice x" with the same results.
Other SPICE flavors use .cir, .spc, or other extensions in the same way.

If one uses a personal preferred extension, such as cir, with a tool such as
HSPICE,, the only requirement is to submit it with the full file name, such
as "hspice x.cir".  (Of course, one should also double-check that the model
parameters and parameter names are correct for the selected simulator.)

"Model" is used for many things.  A "macromodel" is a model built from other
components.  Also, "model" can refer to an "element" provided with the
simulator, or the parameters and equations that define that model, or the
parameter values for a specific component.  Circuit designers sometimes call
a circuit netlist a model.  (NOTE: model parameters and parameter values are
generally NOT portable between SPICE flavors.)

Regards,
Lynne

"IBIS training when you need it, where you need it."
Next public IBIS seminar is Oct 9-10 in Fremont, CA.
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Roy Leventhal | 2 Sep 2008 03:20
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Advanced notice: The IEEE EMC Society is interested in practical design!

All,

Recently I attended the IEEE EMC Society's annual symposium in Detroit, 
Michigan. Many sessions and papers have been devoted to Signal Integrity 
(SI) and Power Integrity (PI), and their effects on EMI-EMC. I thought 
the time had come to suggest soliciting papers that are oriented to 
practical design in SI, PI and EMI-EMC. This idea was well received by 
TC10, the technical committee charged with the task of putting together 
sessions in this subject area.

The session papers and speakers would be focused on the application of 
formulas and EDA tools to design problems rather than their derivation 
or verification. Just enough on their derivation and verification would 
be given to put the design methods in context. The main effort would be 
in explaining how limitations in the methodology were successfully 
overcome and how manufacturing variability was managed.

The session could be organized in different ways. Four papers in a four 
hour session would be the right amount. Two way I am thinking of 
organizing a session are:
1. Four papers that take a design development from start to completion. 
Each would explain how Signal Integrity, Power Integrity, EMI-EMC, and 
manufacturing variability was design for.

Or,

2. One paper each on Signal Integrity, Power Integrity, EMI-EMC, and 
manufacturing variability with explanations of effects on, and from, the 
other three areas.
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Doug Smith | 3 Sep 2008 02:19

Unshielded loops as useful as shielded ones for many uses in SI and EMC

 Hi All,
Just posted my latest article. This is the first one that includes an
embedded video to expand the subject (one of the three I released a few
weeksago before my latest heavy travel schedule).

I took about an hour and 20 minutes of video at the recent IEEE EMC
Symposium. The videos include short clips on products I thought were novel
orinteresting in the exhibits hall. I will edit them and post some videos
from the Symposium soon.

The Square Shielded Loop - Part 5, Measurements in the Time Domain
(For Shielded and Unshielded Magnetic Loops)

Abstract: Shielded loops are often used to minimize electric field
(capacitive) coupling. A case is shown where using both unshielded and
shielded magnetic loops to inject signals into a path on a circuit board
results in an injected signal that is about the same for both loops.
Unshielded wire loops are thus shown to be as useful as shielded loops for
pulse injection.

Doug
-- ------------------------------------------------------- ___ _ Doug Smith
\/ ) P.O. Box 1457 ========= Los Gatos, CA 95031-1457 _ / \ / \ _ TEL/FAX:
408-356-4186/358-3799 / /\ \ ] / /\ \ Mobile: 408-858-4528 | q-----( ) | o |
Email: doug@...[1] \ _ / ] \ _ / Website: http://www.dsmith.org[2]
------------------------------------------------------- 

--- Links ---
   1 mailto:doug@...
   2 http://www.dsmith.org
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Roy Leventhal | 3 Sep 2008 03:43
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Re: Advanced notice: The IEEE EMC Society is interested in practical design!

Patrick,

Yes, August a year from now.

I should have mentioned that ideas on subjects and speakers are welcome 
even now since it gives me extra time to work the issues.

Best,

Roy

Carrier, Patrick wrote:
> Hey Roy--
> This sounds like a great idea...
> Did you really mean mid-August?  Like, a year from now?
>
> Thanks.
> --Pat 
>
>
> Patrick Carrier
> ph. 512-425-3015
>
> -----Original Message-----
> From: si-list-bounce@... [mailto:si-list-bounce@...]
> On Behalf Of Roy Leventhal
> Sent: Monday, September 01, 2008 8:21 PM
> To: si-list
> Subject: [SI-LIST] Advanced notice: The IEEE EMC Society is interested
> in practical design!
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Axcon/Rolf V. Ostergaard | 4 Sep 2008 09:35
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Lee Ritchey 3 day SI training in Copenhagen, Denmark, Oct 7-9

Announcement:

Axcon is hosting a 3 day "Signal Integrity and High Speed System Design"
course featuring Lee Ritchey of Speeding Edge. 

Where: Copenhagen, Denmark. Only 20 minutes from the airport with cheap
flights from most of Europe.

When: October 7-9, 2008. 

Why would you want to go?

* Create stable transmission lines and power subsystems (PDS)
* Select IC packages that support the technology
* Design PCB's that work first time
* Pass EMC tests
* A unique opportunity to spend a full day on nothing but PDS design
* Pre-submit questions for Lee to prepare and answer on the last day
* Two sponsor nights with networking opportunities
* In the end you design with better margins - and ask better questions :-)

For full details and sign-up please go to www.axcon.dk/lee

I am looking forward to see some of you there!

// Rolf

--
Rolf V. Ostergaard, M.Sc.EE.
Axcon ApS - The FPGA Power House.
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yinhongcheng | 4 Sep 2008 10:36
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PCI IO buffer problem?

Hi, All,
     Some vendor or foundry provides special PCI(33Mhz or 66Mhz) IO buffer in their IO buffer
library during ASIC design,but some not. 

     So I want to know what is the difference between common CMOS logic IO and special PCI IO, if
we can use commom IO buffer replace special PCI buffer during ASIC design?if do so, what factor
(such as Hot-plugging and so on) should be take into account? thanks!

Best Regards
HongchengYin

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Gmane