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Doug Smith | 2 Mar 2008 04:30

Measuring and interpreting the relative phase of common mode currents


Hi All,

I have been busy writing again and have the March 2008 Technical Tidbit
ready. The link to the article is the picture with two current probes at the
bottom of the page at http://emcesd.com[1] .  This technique should be
applicable to a wide range of system cables from LVDS cables (one of my
favorite of late) to more mundane cables like power, mouse, and keyboard
cables.

Technical Tidbit - March 2008 
Measuring and Interpreting the Relative Phase of Common Mode Currents
(an EMC emissions troubleshooting technique) 
This month's Technical Tidbit discuses how to measure the relative phase of
two common mode currents with a spectrum analyzer and how to interpret the
results to help fix EMC problems. 
Abstract: Common mode currents have long been used to predict emissions from
cables. However, the relative phase between common mode currents on two
cables can yield useful information for troubleshooting EMC problems. A
simple method for determining the relative phase between two common mode
currents using a spectrum analyzer is given along with an example.

Doug
-- ------------------------------------------------------- ___ _ Doug Smith
\/ ) P.O. Box 1457 ========= Los Gatos, CA 95031-1457 _ / \ / \ _ TEL/FAX:
408-356-4186/358-3799 / /\ \ ] / /\ \ Mobile: 408-858-4528 | q-----( ) | o |
Email: doug@...[2] \ _ / ] \ _ / Website: http://www.dsmith.org[3]
------------------------------------------------------- 

--- Links ---
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Ralf Brüning | 2 Mar 2008 18:47
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European IBIS Summit at DATe 2008 - Third Call for Call for Paticipation


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Bob Ross | 2 Mar 2008 23:13

Re: European IBIS Summit at DATe 2008 - Third Call for Call for Paticipation

Contents missing from SI list announcement and resent to IBIS Lists
because of some system downtime.

Sorry, if duplicate.

Bob

------

To All:

        We have been holding successful European IBIS Summit Meetings
        for the past 10 years!  This year we are again holding a
        meeting along with DATe 08 on Friday, March 14th, 2008.

        The purpose is to promote communication among users and
        developers of IBIS models in Europe. The meeting is free and
        open to everyone.

        We tentatively have six persentations so far as noted in the
        Agenda portion of the Announcement, but we expect a few more.

        The meeting this year is sponsored (so far) by:

            Agilent Technologies
            Infineon
            Mentor Graphics
            Nokia-Siemens Networks
            Sigrity
            ZUKEN
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icer world | 4 Mar 2008 05:33
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Why PDS impedance exceeds target impedeance in low frequency less than 1kHz is OK ?

It's said that PDS impedance  exceeds  target impedeance in low frequency less than 1kHz is OK , can anyone
give me some explains?Thanks!

      ____________________________________________________________________________________
Never miss a thing.  Make Yahoo your home page. 
http://www.yahoo.com/r/hs

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icer world | 4 Mar 2008 05:48
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How to decide the frequency of reaching target impedance of PDS?

I don't know when the value of the frequency of reaching  target impedance is OK? Can anyone give me some advices,Thanks!

      ____________________________________________________________________________________
Never miss a thing.  Make Yahoo your home page. 
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Tom Dagostino | 4 Mar 2008 05:53

Re: Why PDS impedance exceeds target impedance in low frequency less than 1kHz is OK ?

If your DC target impedance is set by the allowed IR drop then if the target
impedance at DC is exceeded you don't get the desired power to the chip.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
503-430-1285 FAX
tom@...
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of icer world
Sent: Monday, March 03, 2008 8:34 PM
To: SI LIST
Subject: [SI-LIST] Why PDS impedance exceeds target impedeance in low
frequency less than 1kHz is OK ?

It's said that PDS impedance  exceeds  target impedeance in low frequency
less than 1kHz is OK , can anyone give me some explains?Thanks!
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olaney | 4 Mar 2008 06:32
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Re: Why PDS impedance exceeds target impedeance in low frequency less than 1kHz is OK ?


On Mon, 3 Mar 2008 20:33:34 -0800 (PST) icer world <icermail@...>
writes:
> It's said that PDS impedance  exceeds  target impedeance in low 
> frequency less than 1kHz is OK , can anyone give me some 
> explains?Thanks!
> 
>       
Below 1 KHz, you are in the bandwidth of the power supply regulator loop.
 By holding the voltage constant, the regulator acts as a very low
impedance (z<<1 ohm).  If the supply has remote sense leads, you can use
those to compensate for the voltage drop in the feeding cable, making the
regulated point be at the PCB.  At audio frequencies, the wavelengths are
so long that the PCB is just an itty bitty stub, and the PDS impedance is
dominated by supply regulation and by copper resistance, not by the
distributed values at HF that are the nominal focus of this forum.

Orin Laney
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Eric Bogatin | 5 Mar 2008 00:11
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www.BeTheSignal.com

Hi folks-

I've had a number of folks who have taken my Essential Principles class come
back and tell me they thought I should offer more of our online lectures to
the SI community.

So, here's the offer this month: everyone on the SI list is invited to view
OLL-180 Rules of Thumb, for free. All you need to do is visit
www.BeTheSignal.com <http://www.bethesignal.com/> , open the online lecture
tab and add OLL-180 to your cart. 

Use the coupon code EPSIAPR and the charges will show a balance of 0. If you
are not a member of the web site, you will be asked to register to set up an
account, and the lecture will be moved into your account for viewing. 

You will be able to download a pdf copy of the slides and then watch the
lecture streamed through your browser. This coupon code will expire on March
18, so you only have 2 weeks to use it.

I hope you enjoy it. We love feedback, so please let me know what you think
and if you have ideas for other topics. We are working on a series of
lectures that will be posted over the next few months. 

There is still room in some of our public classes offered in San Jose in
early April. I look forward to seeing you there!

--eric

**************************************
Dr. Eric Bogatin, President
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Joel Brown | 5 Mar 2008 19:41
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Questions about interplane capacitance

Interplane capacitance is frequently cited as the only effective bypass
capacitance on a PCB at frequencies above 200 MHz.
I am currently working on a design which brings up some questions regarding
interplane capacitance.

1. Power planes normally carry "standard" voltage rails that are used
throughout a board such as +5V and +3.3V.
High speed ICs usually have core voltages that are local to the IC and are
provided by a local regulator which converts the standard rail to the core
voltage (example 3.3 to 1.8V).
The local core voltage is distributed on a plane area that is local to the
IC and therefore is small in area (0.25 sq in or less) which results in a
very small amount of interplane capacitance.
Is this very small amount of capicitance effective for bypassing the IC? I
am sure it depends somewhat on the current waveform being drawn by the IC
but this can only be estimated because semiconductor manufacturers do not
provide current consumption profile as a function of frequency. To make
matters worse, some ICs have several different VCC pins which the
manufacturer recommends connecting to separate networks of bypass caps and
ferrite beads. This cuts the power distributuion up even more resulting in
less (practically zero) interplane capacitance. It is somewhat ironic that
the the voltages such as +5V and +3.3V which are required at points across
the whole board and therefore have the most interplane capacitance are also
the voltages which have least requirement for interplane capacitance because
they do not directly supply high speed rails.

2. There has been a lot of emphasis on reducing the mounted inductance of
bypass capacitors. Even with this reduced inductance they are still only
effective up to several hundereds of MHz at which point the interplane
capacitance becomes the only bypass capacitance mechanism. However there is
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steve weir | 6 Mar 2008 02:53

Re: Questions about interplane capacitance

Joel,

1. The frequency at which plane capacitance dominates over bypass cap 
impedance is approximately:  F = 1/(2pi(Lbypass*Cplane)^0.5).  If for 
example you are using 4 mil planes then with no perforation, you've got 
55pF in your 0.25"sq.  Lspread depends on the thickness of the plane and 
the IC power pin pattern.  For a 4mil dielectric and an IC with a 
healthy number of power pins it is typically somewhere between 10pH and 
50pH ( usually leaning towards 50pH ).  The point of diminishing returns 
for the bypass caps is where Lbypass = Lspread.  So, you get bang for 
your buck out of the bypass caps down to 10pH - 50pH mounted 
inductance.  The resulting PRF is well over 1GHz.

2. It depends on the application as indicated above.  The way that this 
extends to systems with multiple ICs is that the plane area that is 
exclusive to a given IC is the plane area that you should be calculating 
PRF against.  So, if you've got BGA's on a 2"x2" pitch, you've got a 
little less than 4"sq of plane that "belongs" to each IC.  In 4 mil 
dielectric that's 0.9nF.  For spreading plus bypass inductance in the 
20pH - 100pH range, that sets the PRF between 500MHz and 1GHz.  If you 
use thin dielectric, you can either yield lower impedance to each IC, or 
use fewer capacitors for the same nominal maximum impedance which will 
then occur at a lower frequency.  There are six things that you can do 
to reduce the number of bypass caps needed in a design:

1) Design using the right metrics.  Over designing or improper design 
costs a lot of money.  The idea behind tools like Sigrity's PI Optimizer 
is to avoid over-design that often results from ad-hoc methods.
2) Use a stack-up optimized for power delivery.  Putting the first plane 
cavity in PCB layers 2/3 instead of 5/6 improves capacitor mounted
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Gmane