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Scott McMorrow | 1 Sep 2007 01:10

Re: How to properly simulate signal integrity across PCBs interconnected by Flex?

To add to this, Samtec has a line of connectorized Flex and Cable 
interconnects that are designed specifically to handle high speed 
signals.  Any application information that you need is available either 
on-line and through them.  Also, for some of the assemblies, spice 
models are available.

http://www.samtec.com/high_speed_connectors/2006/SI_C2B.asp?m=hs#HSF

By way of a disclaimer, we are associated with and do work for Samtec.  
However, we have designed and characterized quite a few of these flexes 
and cables.

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC

Curt McNamara wrote:
> The answer to shipping clocks across flex:
> Don't do it if possible. Reconsider the system, perhaps distributed
> clocking would work, or even clock recovery from data. If you absolutely
> had to ship clock across flex, do it differentially on two layer flex.
> Next best would probably be two layer flex with ground plane under clock
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Scott McMorrow | 1 Sep 2007 01:31

Re: How to properly simulate signal integrity across PCBs interconnected by Flex?

I should have said:

"By way of a disclosure, we are associated with and do work for Samtec.  
However, we have designed and characterized quite a few of these flexes 
and cables."

I need a beer!

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC

Scott McMorrow wrote:
> To add to this, Samtec has a line of connectorized Flex and Cable 
> interconnects that are designed specifically to handle high speed 
> signals.  Any application information that you need is available 
> either on-line and through them.  Also, for some of the assemblies, 
> spice models are available.
>
> http://www.samtec.com/high_speed_connectors/2006/SI_C2B.asp?m=hs#HSF
>
> By way of a disclaimer, we are associated with and do work for
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Yuriy Shlepnev | 1 Sep 2007 17:34
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Re: Conductor loss reduction at High Frequency

We also did some investigations of the roughness effect in
http://pcdandm.com/cms/content/view/3620/95/  RMS value for roughness was 1
um in the PCB example both for the strip and plane. In the packaging
example, planes and one side of the strip had 1 um RMS. The top strip
surface (that is closer to the plane) was assumed to be flat. Dielectric
polarization losses and dispersion were not included in the analysis to
focus only on the conductor-related effects. Though we did also computations
for the same configurations taking into account the polarization loss and
dispersion effects and it correlated well with the published experimental
data.

Yuriy Shlepnev
Simberian Inc.
www.simberian.com

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of olaney@...
Sent: Friday, August 31, 2007 9:50 AM
To: hreidmarkailen@...
Cc: si-list@...
Subject: [SI-LIST] Re: Conductor loss reduction at High Frequency

Here is a link to the paper that Dr. Bogatin pointed out:
http://www.gouldelectronics.com/papers/CopperSurfaceLoss.pdf

Orin

On Thu, 30 Aug 2007 18:26:43 -0700 agathon <hreidmarkailen@...>
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Dmitriev-Zdorov, Vladimir | 3 Sep 2007 19:18
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hapice simulation of Z_tdr

Hi ZHENGGANG,

Unfortunately, this does not seem as a correct approach.
By definition, you need to measure Z(t) in time domain by applying the
unit step current and measure the voltage response. In frequency domain,
you can reverse the ratio by swapping nominator and denominator.
However, this operation does not correspond to swapping nom/denom in
time domain.

What you do is good for measuring conductance profile. Apply voltage
step, measure the current response. Then, go into frequency domain by
FFT. You will also need to divide on 1/s to get the conductance. Then,
inverse it and get impedance in frequency domain. After that, if you
need time domain profile, apply IFFT - you will get Dirac response. If
you need impedance step response just integrate this in time domain.

But if you simulate in HSPICE there should be no problem applying
current step and measure voltage.

Vladimir

=20
>Date: Fri, 31 Aug 2007 15:50:40 -0700
>From: "ZHENGGANG CHENG" <zhenggang.cheng@...>
>Subject: [SI-LIST] hapice simulation of Z_tdr
>
>Hi all,
>Thanks for your clear explanations!
>
>I have another interesting question about my hspice simulation deck for
(Continue reading)

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tao xu | 4 Sep 2007 02:58
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Re: the difference of current profile between power supply path, signal path and return path in a circuit loop

Hi, Zhengrong,
I think the key for this question is if this component can be treated as a
node in your analysis. If the answer is yes, the description above is
correct. but if it is not, we should think more.

for one buffer case, I guess it is easy to simplify it as a node since power
pin, group pin and signal out pin is assumed at same location. and a quick
solution can be drawn that output current in signal path is same as one in
return path. (input current is too small to be ignored)

But for a whole chip, we always can not treat it at node in current signal
speed and must considered its distribution characters. no such ONE node as
above can be created.

Thanks and Regards
Tao ( Helen )

On 8/31/07, xuzhengrong <xuzhengrong@...> wrote:
>
> Benny,
> I know my question is so basic and seems to be ridiculous.
> What I interest is how to get the current profile for voltage noise
> simulation associated with PDN, for it is hard to get the current =
> profile of
> ICs in the power rail from IC supplier.
> Though there's a method to get current profile by voltage tests =
> indirectly,
> I'm still interested in getting it by direct tests.
> So I ponder upon the problem whether it exits a path I can test simply =
> and
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xuzhengrong | 4 Sep 2007 04:42
Favicon

Re: the difference of current profile between power supply path, signal path and return path in a circuit loop

Helen,
I have realized that I confuse current in the main path and that in the
branch. =20
Kirchhoff's current law is right for all circuit .
It is important to recognize whether it is the main path or not. =20
Thanks for your advice.

Best Regards,
Zhengrong

-----=D3=CA=BC=FE=D4=AD=BC=FE-----
=B7=A2=BC=FE=C8=CB: si-list-bounce@... =
[mailto:si-list-bounce@...]
=B4=FA=B1=ED tao xu
=B7=A2=CB=CD=CA=B1=BC=E4: 2007=C4=EA9=D4=C24=C8=D5 8:58
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=B3=AD=CB=CD: Benny Yan; si-list@...
=D6=F7=CC=E2: [SI-LIST] Re: the difference of current profile between =
power supply
path, signal path and return path in a circuit loop

Hi, Zhengrong,
I think the key for this question is if this component can be treated as =
a
node in your analysis. If the answer is yes, the description above is
correct. but if it is not, we should think more.

for one buffer case, I guess it is easy to simplify it as a node since =
power
pin, group pin and signal out pin is assumed at same location. and a =
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praveen | 4 Sep 2007 10:09
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Reg: Single sided PCB Antenna

Hi,

I have to design one single sided PCB loop antenna for contact less smart
card reader. As per our requirement the trace should have 50 ohm impedance
and 1.27uH inductance. In the internet I can't find any calculator for
calculating trace impedance and inductance of single sided PCB. Can any one
give suggestion for this?

Thanks and regards,

Praveen

e-con Systems India Pvt. Ltd.
No.17, 54th Street
Ashok Nagar, Chennai - 600 083
Tel : +91-44-42033691,42029443, 42033689 
Fax : +91-44-42033600
mail id:   <mailto:praveen@...> praveen@...
 <http://www.e-consystems.com> www.e-consystems.com

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steve weir | 4 Sep 2007 11:11

Re: Reg: Single sided PCB Antenna

praveen, I think it sounds confusing to you because you are probably 
thinking transmission line where the idea is to convey the energy from 
one end to the other, instead of antenna where the idea is to launch the 
energy into space.  You should get a hold of a book on antenna design.  
You should also be asking questions about that spec.  You need to know 
things like:  the frequency the antenna will be working at, the 
radiation pattern, the gain requirements, etc, etc.  Once you have a 
viable spec for what the antenna needs to do you can try and map it to 
any of the well known antenna designs and your packaging restrictions.

If you don't have field solver software or a canned design to work from, 
I seriously recommend you farm the antenna design out to an RF house 
with the tools and experience to do this job properly.

Steve.
praveen wrote:
> Hi,
>  
>
> I have to design one single sided PCB loop antenna for contact less smart
> card reader. As per our requirement the trace should have 50 ohm impedance
> and 1.27uH inductance. In the internet I can't find any calculator for
> calculating trace impedance and inductance of single sided PCB. Can any one
> give suggestion for this?
>
>  
>
> Thanks and regards,
>
> Praveen
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Andrew Morley | 4 Sep 2007 11:16
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USB full-speed (*not* high-speed) layout and stubs.

Hi all,

There are plenty of guidelines for high-speed (480Mb/s) USB PCB
layout, but I can't find any for full-speed (12Mb/s).  Obviously
full-speed is much less demanding, and for what I'm considering doing,
it will need to be.  

I would like to provide a standard USB 'B' socket (full-speed, *NOT*
high-speed).  That all sounds pretty straightforward. However I'd also
like to connect the same USB transceiver to a proprietary connector
(that carries USB and other signals).  The system would be
(mechanically) arranged so that it would not be possible to use both
sockets.  With the proprietary connector disconnected, the user would
be able to use the standard USB; with the proprietary connector mated,
USB would be carried over the connector and the user will not be able
to use the standard connector.  It is important that the standard USB
'B' port should pass USB compliance.  

What I'm considering doing is having the transceiver connected to each
port by a set of impedance-matching resistors (i.e. each port has its
own resistors).

For high-speed (480Mb/s) USB, paralleling-up the two ports in this way
would be completely unacceptable.  For full-speed (12Mb/s) and below,
I have been unable to find a reason why this shouldn't work.  However
I'm still rather uneasy about it.

Has anyone tried this?  Did it work?  Were there any problems
(especially passing compliance)?  Any thoughts?
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RameshK Cozerv IN HO | 4 Sep 2007 11:32

Single sided PCB Antenna

Content-Type: text/plain;
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Hi Praveen,

Check the site called Rf Electronics.com,you will find plenty of information
related
to your above subject topic.

 
Regards

Ramesh

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