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Kenny Frohlich | 1 Dec 2006 01:21
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DDR2 IMPEDANCE

Hi All,
Can someone please tell me where I can find information on DDR2 impedances (ie. what is the impedance of CLK?
Data? Address? Command?)? 
We use PowerPC PPC440EP and on-board DDR2 SDRAMs.
  Thank you.

  Regards,
Kenny

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Jory McKinley | 1 Dec 2006 03:22
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Re: DDR2 IMPEDANCE

Hello Kenny,
Are you designing this type interface?  If so then take a look at the AMCC spec:
https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440EP/PPC440EP_DS2002_v1_24.pdf

There should be some board guideline information for the DDR interface.  You will have to simulate.

Simulating an existing interface?  If you can obtain a board file then the traces (impedances) can be
extracted for the interface.

-Jory

 Kenny Frohlich <kenny_frohlich@...> wrote: Hi All,
Can someone please tell me where I can find information on DDR2 impedances (ie. what is the impedance of CLK?
Data? Address? Command?)? 
We use PowerPC PPC440EP and on-board DDR2 SDRAMs.
  Thank you.

  Regards,
Kenny

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tao xu | 1 Dec 2006 15:58
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Re: DDR2 IMPEDANCE

kenny, what kind of impedance did you ask? Buffer output impedance for
interface or normal trace impedance on board?

On 12/1/06, Jory McKinley <jory_mckinley@...> wrote:
> Hello Kenny,
> Are you designing this type interface?  If so then take a look at the AMCC spec:
> https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440EP/PPC440EP_DS2002_v1_24.pdf
>
> There should be some board guideline information for the DDR interface.  You will have to simulate.
>
> Simulating an existing interface?  If you can obtain a board file then the traces (impedances) can be
extracted for the interface.
>
> -Jory
>
>
>  Kenny Frohlich <kenny_frohlich@...> wrote: Hi All,
> Can someone please tell me where I can find information on DDR2 impedances (ie. what is the impedance of
CLK? Data? Address? Command?)?
> We use PowerPC PPC440EP and on-board DDR2 SDRAMs.
>  Thank you.
>
>  Regards,
> Kenny
>
> ---------------------------------
> Access over 1 million songs - Yahoo! Music Unlimited.
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
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tao xu | 1 Dec 2006 16:07
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Re: DDR2 IMPEDANCE

for trace impedance. it is normally 50 or 60 ohm based on my previous
experince. Clock singal sometimes has lower impedance trace than other
signal groups.

On 12/1/06, tao xu <helen.tao.xu@...> wrote:
> kenny, what kind of impedance did you ask? Buffer output impedance for
> interface or normal trace impedance on board?
>
> On 12/1/06, Jory McKinley <jory_mckinley@...> wrote:
> > Hello Kenny,
> > Are you designing this type interface?  If so then take a look at the AMCC spec:
> > https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440EP/PPC440EP_DS2002_v1_24.pdf
> >
> > There should be some board guideline information for the DDR interface.  You will have to simulate.
> >
> > Simulating an existing interface?  If you can obtain a board file then the traces (impedances) can be
extracted for the interface.
> >
> > -Jory
> >
> >
> >  Kenny Frohlich <kenny_frohlich@...> wrote: Hi All,
> > Can someone please tell me where I can find information on DDR2 impedances (ie. what is the impedance of
CLK? Data? Address? Command?)?
> > We use PowerPC PPC440EP and on-board DDR2 SDRAMs.
> >  Thank you.
> >
> >  Regards,
> > Kenny
> >
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tao xu | 1 Dec 2006 16:23
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Re: trace length matching

pornchai
Putting serie termination in different position while keep total trace
length same will effect flight time a little.
I have run a simulation before to see different jitter showed on
receiver waveform by only moving serie termation R along trace.
So keep each segment same is most safe way.
But this kind of fligh time difference is very small value. Running a
simulation will give you more indicate on if you can only matching
total length

On 12/1/06, Jory McKinley <jory_mckinley@...> wrote:
> Hello Pornchai,
> If the net constraint for your particular application requires matched t-line lengths (diff or single
ended) within a net class which also includes a series termination for each net I would attempt to match
each net segment to and from the series termination.  Of course if you can simulate the topology you will be
able to determine the variation you are allowed within each net segment.
> -Jory
> p_pornchai <ppornjaturapak@...> wrote: Hi All,
>
> When do the PCB routing for high speed design from point to point. There
> is a requirement that we need to match the trace length for each net in the=
>
> group. If there is a serie termination between the two point, is it require=
>
> that each segment(each net before the termination should equal and each
> net after the termination should be equal) to be match in length or can we
> only match the total length of the trace(lenght of segment of trace before
> the termination + lenght of segment of trace after the termination).
>
> Thanks in advance for all your help.
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Dev Malladi | 2 Dec 2006 01:34
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Product engineer position at PLX

All, Please contact me

Sr. Product Engineer

PLX is a leader in PCI Express products in the Semiconductor industry.
We hire highly talented individuals who will continue PLX leadership in
delivering products and solutions that help customers achieve their
business goals.

Responsibilities:

Act as a central resource and expert for all product related issues.
This includes, but is not limited to, release of new products to
manufacturing, device qualification, electrical characterization,
product sustaining, yield enhancement, and vendor interface.

*	Oversee product qualifications.
*	Perform device characterization
*	Validate and release ATE programs to manufacturing.
*	Interface with Design/Applications Engineering to resolve
product related issues.
*	Implement and optimize manufacturing flows.
*	Drive yield enhancement and maverick lot programs.
*	Coordinate cost reduction projects.
*	Maintain reliability audit programs.
*	Participate in new vendor selections.
*	Drive package development efforts.
*	Resolve customer & production yield problems.
*	Failure analyze customer returns and drive improvement plans.
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Madhusudanan K Sampath | 2 Dec 2006 06:16
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Spectre S-parameter based modeling- Stability issues

Hi All, 
I am using n-port component in spectre to perform time domain simulation
using touchstone s-parameter files for power planes which are obtained from
measurement/full wave tools. In many cases, the simulation explodes due to
stability reasons. What are the possible causes of this and how can one
solve this issue. I think Spectre n-port component uses convolution methods
to perform time domain simulation from frequency domain s-parameter data and
hence are prone to convergence issues. If so how does it enforce passivity
in the model. I verified the s-parameter matrix for eigenvalues and it
proves the data is not passive. I would like to compensate for passivity and
then re-try the time domain simulation. There are quite a few interesting
passivity enforcements techniques in literature by Dr. B. Gustavsen and Dr
S.G. Talocia . However they are applied on the rational functions which are
obtained by vector fitting the data. My question is  if I vector fit the
data, enforce the passivity using these techniques and then calculate  the
S-parameter matrix for each frequency point from the passive rational
function model.  Will spectre give stable results with this new data ? 

Please share your ideas and views on this. Thanks in advance. 

Madhu 

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Zabinski, Patrick | 2 Dec 2006 13:20
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Re: Spectre S-parameter based modeling- Stability issues

Madhu,

Enforcing passivity is a good step, but it might not be
enough.  You should also consider causality constraints,
which are bit more challenging to enforce.

When you're enforcing passivity or causality, there are
two things to keep in mind:=20

1) the fact that your S-parameter data is not well behaved
(i.e., non-passive, non-causal) suggests that it is likely
incorrect/inaccurate.  Minor violations can often be tolerated,
but "minor" is a relative term that is difficult to quantify
in a general sense.

2) When enforcing passivity and causality, you are changing
the data, and thus you are modifying the behavior of the
model.  The issue is if you're modifying the file in the
correct/better direction, or are you making the model
worse.

When you get files that have convergence problems, the first
step is to go back to the source to double-check where
the raw S-parameter data file is coming from and do what you
can to make it passive/causal right out of the box.

If that is not possible (most often the case), then the
plan you outline sounds reasonable with the caveats/concerns
I mention above.
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Ihsan Erdin | 2 Dec 2006 17:25
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Re: Spectre S-parameter based modeling- Stability issues

Madhusudanan,
If you're dealing with the power planes there's a good chance the port loads
are linear (decoupling caps and their parasitics, etc.) Then why bother with
the time domain simulations and painful data constraintment? Just use a
linear frequency domain simulator and get the time domain results by DFT in
a straightforward manner.

Regards

Ihsan

On 12/2/06, Madhusudanan K Sampath <mkeezhve@...> wrote:
>
> Hi All,
> I am using n-port component in spectre to perform time domain simulation
> using touchstone s-parameter files for power planes which are obtained
> from
> measurement/full wave tools. In many cases, the simulation explodes due to
> stability reasons. What are the possible causes of this and how can one
> solve this issue. I think Spectre n-port component uses convolution
> methods
> to perform time domain simulation from frequency domain s-parameter data
> and
> hence are prone to convergence issues. If so how does it enforce passivity
> in the model. I verified the s-parameter matrix for eigenvalues and it
> proves the data is not passive. I would like to compensate for passivity
> and
> then re-try the time domain simulation. There are quite a few interesting
> passivity enforcements techniques in literature by Dr. B. Gustavsen and Dr
> S.G. Talocia . However they are applied on the rational functions which
(Continue reading)

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Doug Smith | 3 Dec 2006 05:36

Measuring signals in the presence of significant noise - part 2

Hi All,

In November I published a Technical Tidbit on my website on how not to 
measure signal voltages in the presence of significant noise. This 
month I show one possible solution - a passive differential probe.

Measuring Signals in the Presence of Severe EMI - Part 2, A 
Differential Solution (differential measurement using a passive 
differential probe)

Abstract: A passive differential probe can be very useful for making 
voltage measurements in the presence of severe interference such as 
nearby ESD. In such a situation, active differential probes cannot be 
used because of common mode input voltage limitations. Data is 
presented to show typical effectiveness of a passive differential probe.

The link to the article is:

http://emcesd.com/tt2006/tt120106.htm

And for the November article:

http://emcesd.com/tt2006/tt110106.htm

Doug
--

-- 
-------------------------------------------------------
     ___          _       Doug Smith
      \          / )      P.O. Box 1457
       =========          Los Gatos, CA 95031-1457
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