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Grasso, Charles | 1 May 2006 06:59
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Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation)

You get what you pay for..
________________________________

From: si-list-bounce@... on behalf of Oscar Lang
Sent: Sat 4/29/2006 10:43 AM
To: SI-LIST
Subject: [SI-LIST] Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation)

I went to there website just out of curiosity and saw
thses are mostly 2D and spice like software that one
can get for free.

Why will someone pay $695 for a software like this?

--- Faraydon Pakbaz <pakbazf@...> wrote:

> Drew;
>
> My apology for asking this...You probably had enough
> of
> "assist@...".
> I also was contacted to try this software. Just out
> of curiosity, have you
> or anybody in
> SI-LIST tried this software and can give "high" or
> "low" of this software.
> I have tried it but
> only the examples that is coming with the 30 day
> trail down load. I have
> not done my own
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Ing. Giancarlo Guida | 1 May 2006 10:58
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Re: Effects of solder layer on exposed traces

Hi Sean,
you can very easily take in account thie effect of this extra layer of 
dielectrics on the performances
of  your patch antenna
by using an EM simulator.

I work with ADF EMS a simulator produced by my company IDS (www.ids-spa.it)
but we do not have a student version at the moment.

You amy find very useful student version from many Vendor
I am sure Ansot and Sonnet have student version free to download

Hope this helps
Giancarlo

Sean McDevitt ha scritto:
> My question is in reference to previous posts that asked about the
> effects of solder mask (or silkscreen) on the impedance of lines for
> high frequency ( >2 GHz) lines.  The general consensus I took was that
> solder mask could greatly effect the expected impedance of the traces
> as another dielectric is introduced.
>
> In my application we have etched antennas on a 60mil FR4 board.=20
> Normally, I have made antennas in house using a simple acid etch bath
> (crude but effective).  However, when we order boards from a PCB
> house, any exposed traces are normally covered in a layer of solder
> (including our antennas, but there is no soldermask on the antennas).
>
> Now given that solder is not copper and thus it will have different
> electrical properties, how will this effect the expected performance
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Ken Cantrell | 1 May 2006 16:30

Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation)

All -
I bought the package.  If you have a 3D solver and HSPICE capability, there
is no value add.  If you do not, it may be worth looking in to.  I spent
some time qualifying the software before purchase.  One of the things that I
did was to compare SAMTEC's high frequency lab data for the QTH/QTS 0.5mm
series(PCI_Express app note) to AS/SIST simulation.  Correlation was very
good.  I did another benchmark with multiple grounds similar to a
motherboard with multiple daughter cards which produced good eye
correlation.  It is easy to use and inexpensive.  I am not recommending it
to anyone, and I am not affiliated with the group in any way.  My contact
with the group has been positive and helpful when I ran into
issues/questions.  From that contact, my guess is that they are unaware of
the no advertising rule on SI List.  I have sent them a separate e-mail
informing them of this.

Ken

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...]On Behalf Of Faraydon Pakbaz
Sent: Saturday, April 29, 2006 1:42 AM
To: drew3rdof3@...
Cc: SI-LIST; si-list-bounce@...
Subject: [SI-LIST] Re: E-mail address harvesting (WAS; Re: Signal
integrity and simulation)

Drew;

My apology for asking this...You probably had enough of
"assist@...".
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Faraydon Pakbaz | 1 May 2006 16:56
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Re: E-mail address harvesting (WAS; Re: Signal integrity and simulation)

Ken;

Thank you very much for taking time and explaining your experience. It is
very valuable to me,
I am also in process doing similar testing like you did before purchasing
it. Thanks again.

Regards;

Don Pakbaz

Silicon Solutions Engineering
IBM Systems & Technology Group
Email: pakbazf@...
Voice: (802) 769-5638  Tieline: 446-5638   Fax: (802) 769-5722

                                                                           
             "Ken Cantrell"                                                
             <Ken.Cantrell <at> src                                             
             computers.com>                                             To 
                                       Faraydon                            
             05/01/2006 10:30          Pakbaz/Burlington/IBM <at> IBMUS,        
             AM                        <drew3rdof3@...>           
                                                                        cc 
                                       "SI-LIST" <si-list@...>,  
                                       <si-list-bounce@...>      
                                                                   Subject 
                                       RE: [SI-LIST] Re: E-mail address    
                                       harvesting (WAS; Re: Signal         
                                       integrity and simulation)
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liz_m_mooney | 1 May 2006 17:10
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Re: FPGA SI Issues in Space Applications

Hi Sammit,

This is my first time posting to the list and I just wanted to add a 
couple of things that I have learned about designing for space 
applications.

First of all, there are several different ways that a part in space 
can be affected by radiation including SEU, SEU latchup, high 
radiation doses over a short period of time, and low radiation doses 
over a long period of time.  Just because a part can handle MRads of 
radiation at once doesnt neccessarily mean it can withstand lower 
radiation levels over a 7 year mission.  

What makes a part RADHard is the different type of doping materials 
used in the part.  Some materials can withstand more radiation than 
others but because the manufacturing process is just different and 
produces less parts from the die, its more expensive. Not only that, 
some designs (FPGA specific) are actually slower but they are bullet 
proof.

Some of the things that you can use in your design:
1.  Design triple modular code.  This can usually be done by a 
setting in the design software you are using, compiler setup, or you 
can just do it yourself.  If you let the tool do it for you, it will 
make everything redundant including things like "or" gates which 
arent a big deal, but a flip flop is.  So if you design the 
redundancy yourself, your code will take up less space.

2.  Implement a WDT in the code. This will force the code to 
constantly be doing something.
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Taha Amiralli | 3 May 2006 16:55
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Impedance Matching in SPICE

Dear All,

Does anyone know of an effective method of mirroring  the impedance of
a particular node onto another node in the same spice file?

Specifically, I have a CMOS mosfet configuration and I would like to
ensure that the current passing through the PMOS and NMOS transistors
is at a certain maximum level by placing
a load at the source and the drain's of the PMOS and NMOS transistors
that is equal to the impedance that is currently being felt at another
node.

I gave the Z parameters (Z11 etc) a try but unfortunately, It did not
seem to work out. It would be really nice if there was someway of
saving a current/voltage/parameter and then being able to look up and
use values from that saved list during the simulation of another
circuit. This would also have the same end effect that I am trying to
achieve.

Thanks in advance for the help,

Sincerely,

-------------------
Taha Amiralli
thamiral [A] uwo [D] ca
thamiral [A] gmail [D] com

MESc Candidate 2007, Computer Engineering
The University Of Western Ontario
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Taha Amiralli | 3 May 2006 19:57
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Impedance Matching in SPICE

Dear All,

My apologies if this appears as a double post.... The previous message
bounced :(...

Does anyone know of an effective method of mirroring  the impedance of
a particular node onto another node in the same spice file?

Specifically, I have a CMOS mosfet configuration and I would like to
ensure that the current passing through the PMOS and NMOS transistors
is at a certain maximum level by placing
a load at the source and the drain's of the PMOS and NMOS transistors
that is equal to the impedance that is currently being felt at another
node.

I gave the Z parameters (Z11 etc) a try but unfortunately, It did not
seem to work out. It would be really nice if there was someway of
saving a current/voltage/parameter and then being able to look up and
use values from that saved list during the simulation of another
circuit. This would also have the same end effect that I am trying to
achieve.

Thanks in advance for the help,

Sincerely,

-------------------
Taha Amiralli
thamiral [A] uwo [D] ca
thamiral [A] gmail [D] com
(Continue reading)

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Doug Smith | 3 May 2006 22:41

Routing Signals Between PWB Layers - Part 2

Hi All,

I have been writing and recording again and have posted part 2 of my 
article on signals that change layers in a PWB.

Abstract: Printed wiring board, PWB, signal paths must often change 
layers in a board stackup. Under some conditions this can cause 
problems. An emissions example is used to illustrate the conditions 
where changing layers can cause problems.

The link to the article is the picture of the emissions plot at the 
bottom of the home page at http://emcesd.com .

There is also an audio discussion of this article on my podcast site: 
http://emcesd-podcast.com where the direct link to the article is:

http://emcesd-podcast.com/2006/may/2006-0503.mp3

Can't download mp3 files? Download the following instead:

http://emcesd-podcast.com/2006/may/2006-0503.dcs

After download, change the extension from .dcs to .mp3 and the file 
will then be able to play on most computers. Since the last HFNews 
there have been two new podcasts posted.

Doug
--

-- 
-------------------------------------------------------
     ___          _       Doug Smith
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Geoff Stokes | 4 May 2006 11:45

Re: Routing Signals Between PWB Layers - Part 2

Hi Doug

In this experiment, you appear to have no plane vias adjacent to the
signal vias.  What would happen if a few plane vias were added around
the transitions and fairly close by?

Geoff Stokes
Systems Engineer
Zetex Semiconductors plc
Zetex Technology Park
Chadderton
Oldham
OL9 9LL
UK
=20
+44-161-622-4857
www.zetex.com
www.zetex.cn
=20

=20
-----Original Message-----
From: si-list-bounce@... [mailto:si-list-bounce@...]
On Behalf Of Doug Smith
Sent: 03 May 2006 21:41
To: SI-List
Subject: [SI-LIST] Routing Signals Between PWB Layers - Part 2

Hi All,
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Istvan Novak | 4 May 2006 15:10
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Re: Routing Signals Between PWB Layers - Part 2

Geoff, Doug,

This example nicely shows the importance of proper power distribution 
design.

The emission peaks correspond to the modal resonances of the PCB planes.
As Doug points out in the article, moving the planes closer would reduce the
emission about proportionally.  However, if one wants to stay with a 
four-layer
construction, reducing the plane separation is not a viable solution: it 
would
either result in an unmanageably thin board, or if we add the tickhness 
back to
the top/bottom dielectrics, in a dramatically reduced routing density.

Nearby grounding vias would help, but in practical cases the two planes 
are at
different DC potentials, so it must be a bypass capacitor rather than a 
stitching
via.  A single bypass capacitor will do little in the hundreds of MHz 
frequency range,
even if it serves only one signal.  Also, if we have wide busses instead 
of a single
trace, trying to provide a return path locally to all of the layer 
transitions becomes
much harder to implement.

A more realistic and straightforward solution is to design the 
power-distribution
network in such a way that it does not exhibit large resonances.  In
(Continue reading)

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