steve weir | 1 Apr 11:30 2006

Re: How to simulate length mismatch of PCB traces

Yongjin,  for the situation that you describe, W will work for the 
common parallel runs.  Beyond that you can cascade on any:  LC, LRC, 
U (RCRD), or 4O RLCG sections depending on just how accurate you 
would like to be.  If the assumption is that the coupling on that 
final segment is weak, then the simplest answer would be a single LRC 
stage or the 4O model.  You can derive the L and C values from the 
telegrapher's equations.  R is going to be quite small.  Your segment 
is quite small at 1mm even compared to 100ps rise time.

When you are done, what you are going to see is a simple delay of 
1mm*eR^-.5/C.  For an eR of 4.0, that translates to 1mm/150E9mm/s or 
6.7ps.  L is going to be about 325pH, and C is going to be about 0.13pF.

If you go with a cascade of RLCGs or 4O elements, you can estimate 
the line to line coupling with a field solver.  Likely you will be in 
the 5-10% range.

Regards,

Steve.

At 07:49 AM 3/31/2006, yc2158 wrote:
>Steve,
>Thanks for pointing me out my wrong answer(don't work at midnight!!).
>You are totally right.
>I am considering if I have "a line with a little extra segment on the
>end that the other coupled lines don't" like what you wrote.
>To simplify the problem, I am not considering eR variation and don't
>have meander. My simulation purpose is to see the length mismatch
>effect as waveforms at each line end.
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Mark Apton | 1 Apr 23:32 2006
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H.264 Video Compression Asic Design, new Yahoo group;

Please visit our new Yahoo group for technical discusion of H264RTL 
video Compression, Asic Design.

This group is for technical discussion of the technical issues invloved
with SoC design for H.264 video compression. Subjects like Verilog,
functional verification, RTL, formal verification, SOC design in the
areas of SOC architecture, bandwidth calculation, peripheral design and
integration and industry standard SOC busses and platforms.

Sorry, no job postings here. Please post your jobs at;

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Mark Apton | 1 Apr 23:33 2006
Picon

H.264 Video Compression Asic Design, new Yahoo group;

Please visit our new Yahoo group for technical discusion of H264RTL 
video Compression, Asic Design.

This group is for technical discussion of the technical issues invloved
with SoC design for H.264 video compression. Subjects like Verilog,
functional verification, RTL, formal verification, SOC design in the
areas of SOC architecture, bandwidth calculation, peripheral design and
integration and industry standard SOC busses and platforms;

http://groups.yahoo.com/group/H264RTL/

Sorry, no job postings here. Please post your jobs at;

http://groups.yahoo.com/group/h264JOBS

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Ing. Giancarlo Guida | 2 Apr 19:59 2006
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Re: Theory v. practice, following Re: DesignCon quote

Hi folks,
I'd like to add my two cents to this interesting discussion.
 From my point of view the most important quality of a model ( and 
therefore simulation)
it is not its accuracy...
but its simplicity.

A smart engineer is able to create a simple model to have a look at 
complex reality
because he knows which variable count more than other
what effects are more important than the details
and will understand from simple model how to manage the reality.

A "bad" engineer will be afraid of everything and will not be able to 
eliminate
unnecessary details form his model
he will always look for super fast machine and super accurate simulator
just because he is not sure what really counts in the reality he is studying
and is better to wait a couple of days of calculation time that think 
about his design...:-)))))

A good model will never be simple enough

Giancarlo

Mark Randol ha scritto:
> Time to test my new Out of the Office Reply filter...
>
> My fave is rather old. =20
> "The reason circuits don't work as designed is paper doesn't conduct
(Continue reading)

Faraydon Pakbaz | 2 Apr 20:18 2006
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Re: Theory v. practice, following Re: DesignCon quote

Giancarlo;

Very well put together. I buy your description. Good insight!!

Regards;

Don Pakbaz

Silicon Solutions Engineering
IBM Systems & Technology Group

                                                                           
             "Ing. Giancarlo                                               
             Guida"                                                        
             <gianguida <at> alice.                                          To 
             it>                       Mark.Randol@...              
             Sent by:                                                   cc 
             si-list-bounce <at> fr         si-list@...               
             eelists.org                                           Subject 
                                       [SI-LIST] Re: Theory v. practice,   
                                       following Re: DesignCon quote       
             04/02/2006 04:59                                              
             PM                                                            

                                                                           
             Please respond to                                             
                 gianguida                                                 

Hi folks,
I'd like to add my two cents to this interesting discussion.
(Continue reading)

Mark Randol | 3 Apr 17:55 2006

Re: Theory v. practice, following Re: DesignCon quote

I'd expand on that model a little...

A good engineer starts with the simplest model to prove the idea, then
adds factors that in  their judgment says will be a problem.  Normally
only a couple things at MOST at a time, to reduce the degrees of freedom
when it breaks and needs correcting.

The best use the 'extra' effects as a feature in the design when the
effect is understood well enough to be predictable and manufacturable
enough to be repeatable. =20

I don't remember if it's been requoted here or not, but one attributed
to Einstein was "The supreme goal of all theory is to make the
irreducible basic elements as simple and as few as possible without
having to surrender the adequate representation of a single datum of
experience." =20

I prefer the pithier if inaccurate translation , "Everything should be
made as simple as possible, but no simpler."  It's a simpler model...

--
Mark Randol, RF Evaluation & Application Engineer
ON Semiconductor
901 S. Mopac Expressway
Barton Oaks IV, Suite 343
Austin, TX 78746
512-329-5640 (voice), 512-329-8151 (FAX)
=20

> -----Original Message-----
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Faraydon Pakbaz | 4 Apr 14:20 2006
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Re: Theory v. practice, following Re: DesignCon quote

Noticeable expand ...... but Einstein is also a fallen Angel....
He spent last 30 yeas of his life trying to unify the theory of
Weak forces, Strong forces, gravitational and electromagnetic
force. He essentially violated his own saying of :
"Everything should be made as simple as possible
, but no simpler."

He tried to make it simpler by an illusion of
unification.

He also said:

"God doesn't play Dice with nature"
Quantum mechanic theory proved that, indeed
the Dice has been played. Hisenberg uncertainty
principal proved that even observations of real
experiment is not the reality. We do see this when
we do time domain and frequency domain analysis. As
we try to detect exact frequency the notion of time becomes
inaccurate and as we try to detect at what time precisely
the frequency component came to existence then the exact
value of frequency becomes fuzzy ( and no the short time
Fourier transform or wavelet method do not resolve this)
There are lots of "Monday Morning" quarterbacking
involved in "Modeling" and "Simulations" which leads
erroneously calling them all wrong. Nothing is crisp
here.

"What is above is below and what is below is above"

(Continue reading)

Ray Anderson | 4 Apr 19:13 2006

Future Directions in IC and Package Design Workshop, FDIP'06

SI Community:

At the request of Alina Deutsch, one of the co-chairs of this year's
Future Directions in IC and Package Design Workshop, I have placed the
official announcement of the event on the si-list.org web site.

Please go to this URL for the announcement:
http://si-list.org/files/fdipann06.pdf

The workshop will be held October 22, 2006 in Scottsdale, Arizona.

Any questions related to the workshop should be directed to the event
organizers, not me.

Raymond Anderson

Senior Signal Integrity Staff Engineer

Product Technology Department

Advanced Package R&D

Xilinx Inc.

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Aaen Peter-r40889 | 4 Apr 20:24 2006

Testing


-- 
Peter Aaen                        Freescale Semiconductor 
Peter.Aaen@...          RF Division
(480) 413-6505 (phone)            RF Design Operations
pager: 4807970593@...            

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James Van | 4 Apr 20:28 2006

Signal Integrity Lead Position Available in San Jose, CA (perm/fulltime)


Hi, I posted this job a little while ago, this position is still open.
Please contact me if interested.
I have a client that is a small startup company that is looking to fill
a signal integrity lead as soon as possible! A short copy of the job
description is listed below. 
Please contact James Van at Trinite Inc if interested.

 
Signal Integrity Lead
o       10+ years experience in signal integrity and 3D modeling
o       Deep knowledge of high speed interconnects and I/O circuit
design, power delivery, package design, high speed board design, and EMI
analysis
o       Develop voltage and timing budgets for high speed interconnects
o       Work closely with circuit designers and ASIC engineers on
silicon timing, clock jitter, and signal skews
o       Model power supply distribution and recommend decoupling methods
o       Familiarity with HSpice, ADS, VNA, and TDR
o       Extensive experience with SI tools such as Sigrity and AnSoft
o       MSEE or Ph.D desired

 
~~~~~~~~~~~~~~~~~~~~~~~~
James Van-Recruiter
Trinite Inc.
Office: (650) 210-2010//(888) 872-3526
Mobile: (650) 823-2125
f (650) 210-8989
jvan@...
(Continue reading)


Gmane