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Jim Antonellis | 2 Jan 2006 22:12

Test PCB structures


Hello,

I am planning a PCB test structure board, primarily
to validate my tools, models and design rules for
PCB xtalk, discontinuities (e.g. via backdrilling)
various SMA connector types, impedance controlled
vias, etc. etc. 

Any suggetions, hints or bits of wisdom you may wish
to send me is appreciated as this is my first dedicated
test fab and I would like to minimize the "should-have,
could-have, would-have" effect (notice I did not say
eliminate, but minimize %^)

Thx,
Jim

-
Jim Antonellis   janton@...
Sandburst Corp   www.sandburst.com
Office: 978.689.1669 
Cell: 978.618.4745

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Istvan Novak | 3 Jan 2006 13:46
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Re: Test PCB structures

Jim,

Just a few quick thoughts:
- because of the huge number of possible permutations of possible 
topologies,
geometries and material properties, try to make a best estimate of what
you think you will end up using eventually and grow the number of
permutations around those seed values as your schedule and budget permits
- measurement errors/uncertainties around the connections may kill you;
unless you already have a proven optimized connector launch fitting
your geometry, go for connector less probing directly the traces/features
(see e.g., the IBM publications on the topic).

Regards, and HAPPY NEW YEAR to all of the list members!

Istvan Novak
SUN Microsystems

Jim Antonellis wrote:

>Hello,
>
>I am planning a PCB test structure board, primarily
>to validate my tools, models and design rules for
>PCB xtalk, discontinuities (e.g. via backdrilling)
>various SMA connector types, impedance controlled
>vias, etc. etc. 
>
>Any suggetions, hints or bits of wisdom you may wish
>to send me is appreciated as this is my first dedicated
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Zabinski, Patrick J. | 3 Jan 2006 13:56
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Re: Test PCB structures

Jim,

To ease deembedding and later analysis, it is important
to ensure the probe/coax launches are identical across
all test structures.  Small variations in launch design
can muddy the waters enough that it becomes impractical
to extract the effects/parasitics you're after.

Along these lines, I've found the following set of
structures to be useful in calibration/deembedding/validation:

* Open
* Short
* Through
* Load

In designing these structures, keep their effective
lengths to be identical.  Meaning, from the probe pads
(or coax connector pads), the vias, lines, planes, voids,
etc. need to be identical between all these structures to
the point of the DUT (where DUT can be the open ended
line, or short to ground, or 50 Ohm load, ...).

If you include these structures as baselines, then
your other structures of interest (vias, bends, ...)
should have the same identical launches and lengths
up to the same reference plane of interest.

In doing so, deembedding routines (for VNA measurements)
and port extensions (built into VNAs) and peeling algorithms
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Sanchayan Sinha | 3 Jan 2006 17:32
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Re: PCI-X 1.0a simulation

I have one question regarding this, does an IBIS which is generated from DC
simulations can accurately reflect the dynamic  voltage behaviour that our
I/O's undergo.
Thanks,
Sanchayan

On 12/30/05, Chris Cheng <Chris.Cheng@...> wrote:
>
> 100% in agreement.
> Happy New Year.
> Chris
>
> -----Original Message-----
> From: Aubrey_Sparkman@... [mailto:Aubrey_Sparkman@...]
> Sent: Thursday, December 29, 2005 11:43 AM
> To: Chris Cheng; si-list@...
> Subject: RE: [SI-LIST] Re: PCI-X 1.0a simulation
>
>
> Chris,
> We're probably talking about two different cases.  I was discussing a
> controller to an empty slot; the customer can put in anything, so the
> spec must be the limit.  If you have the case of a chip to chip bus
> where the customer can't make changes, it would be much safer to view
> the spec as more of a guideline and do whatever you can
> to boost the throughput.
>
> Good luck with the competition!
>
> Aubrey Sparkman=20
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Lynne D. Green | 3 Jan 2006 19:08
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Re: PCI-X 1.0a simulation

Hello,  Sanchayan,

IBIS contains both DC and switching information.

The IBIS Waveform (V-t) tables contain the switching waveform data.

Regards,
Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@...

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of Sanchayan Sinha
Sent: Tuesday, January 03, 2006 8:32 AM
To: si-list@...
Subject: [SI-LIST] Re: PCI-X 1.0a simulation

I have one question regarding this, does an IBIS which is generated from DC
simulations can accurately reflect the dynamic  voltage behaviour that our
I/O's undergo.
Thanks,
Sanchayan
(Continue reading)

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Brent Rogers | 3 Jan 2006 19:36

SI Jobs in Austin, TX

Dear Group,
I am presently looking for Signal Integrity Engineers and a Signal
Integrity Manager for two Fortune 500 Companies in Austin, Texas.
Please contact me for more details.
Brent
Rogers@...
 <mailto:si-list@...> 

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Muranyi, Arpad | 3 Jan 2006 19:44
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Re: PCI-X 1.0a simulation

Sanchayan,

As Lynne pointed out, the V-t tables of the IBIS files
are used to describe the transient characteristics of
drivers.  Usually the V-t curves are used as a time
dependent scaling coefficient, scaling the I-V curves
from 0 to 1 or 1 to 0 as time goes by.  If you are
interested in how this works, you can look at my
presentation and a VHDL-AMS implementation of this
algorithm at:

http://www.eda.org/pub/ibis/summits/jun03b/muranyi1.pdf

pages 5, 8, 9, and the VHDL-AMS code is at:

http://www.eda.org/pub/ibis/summits/jun03b/IBIS_basic_IO.vhd=20

I hope this helps.

Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] =
On Behalf Of Sanchayan Sinha
Sent: Tuesday, January 03, 2006 8:32 AM
To: si-list@...
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James Van | 3 Jan 2006 19:47

SI Contract With Intel in Chandler, AZ


Hi,
My name is James Van, I recruit on behalf of Intel. I have a 6 month
contract available at Intel in Chandler, AZ. 
Please email me directly if interested.

Regards,
James

Assignment Information 
Project Location: AZ CH7
Project Name: MG  CHG CSC Tavor - Signal Integrity Engineer Desired
Start Date: ASAP Length of Engagement: 6 mths
How many positions on this SR:      1
Estimated hours per week:     40
Shift: 01
Primary Skill: Solid understanding of SI & Power Delivery concepts &
system timing (see below), OSCILLOSCOPE, writing test plan

Roles & Responsibilities
Position Title: Signal Integrity Engineer

Project Description:
Project is Tavor. Need signal integrity engineer to analyze and simulate
topologies for providing customer guidelines & take silicon measurements
to qualify guidelines and SI/PD design

Daily Responsibilities:
SI simulations and SIV/PDV measurements in lab
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nrpatel | 3 Jan 2006 22:56
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IBIS modelling in PSpice

Hello,
Is there a way to model IBIS in PSpice? If so can anyone show me how?
I am not looking for an exact representation. A behavioral model would be 
just as fine.

Thanks
Nikhil 

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Muranyi, Arpad | 3 Jan 2006 23:27
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Re: IBIS modelling in PSpice

I could be wrong, but I don't think there is an equivalent of
the HSPICE B-element in PSPICE.

However, you could still do it by putting together a bunch of
controlled sources, including some PWL ones.  But it is left
to the student as an exercise to show how this can be done... :-)

That's how I did it in HSPICE before the B-element came out.

Arpad Muranyi
Intel Corporation
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] =
On Behalf Of nrpatel@...
Sent: Tuesday, January 03, 2006 1:56 PM
To: si-list@...
Subject: [SI-LIST] IBIS modelling in PSpice

Hello,
Is there a way to model IBIS in PSpice? If so can anyone show me how?
I am not looking for an exact representation. A behavioral model would =
be=20
just as fine.

Thanks
(Continue reading)

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Gmane