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Boopathy J. | 3 Oct 2005 14:07
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ROHS Compliance

Hi,
   We are converting one of the old PCB to RoHS compliance standards.
I am not very much sure about the process in Rohs.

We have changed all the components footprints as new Rohs  mechanical
packages & I added a note in Fabrication  drawing that the board has to meet
the Rohs compliance standards as RoHS plays more only in PCB fabrication.

  My doubt is whether I need to take any special consideration for the
routing & DFM issues.

Our board is 5/5 trace & spacing. Will this affect any RoHS standards.

Please let me know whether I need to take any care to meet the standards in
PCB CAD designing.

Thanks in Advance.

Regards,
Boopathy J

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Kai Keskinen | 3 Oct 2005 23:34
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Re: ROHS Compliance

You more need to worry about what PCB substrate material you are using. ROHS
compliant solders use higher temperatures that some PCB materials cannot
tolerate for multiple reflow cycles. Many of the PCB fabricators have been
doing experiments with various substrate materials so you should talk to
whoever is building your bare PBCs and who is populating your boards.

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...]On Behalf Of Boopathy J.
Sent: Monday, October 03, 2005 8:08 AM
To: si-list@...
Subject: [SI-LIST] ROHS Compliance

Hi,
   We are converting one of the old PCB to RoHS compliance standards.
I am not very much sure about the process in Rohs.

We have changed all the components footprints as new Rohs  mechanical
packages & I added a note in Fabrication  drawing that the board has to meet
the Rohs compliance standards as RoHS plays more only in PCB fabrication.

  My doubt is whether I need to take any special consideration for the
routing & DFM issues.

Our board is 5/5 trace & spacing. Will this affect any RoHS standards.

Please let me know whether I need to take any care to meet the standards in
PCB CAD designing.

Thanks in Advance.
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Mark Alexander | 4 Oct 2005 00:14
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Jitter Webcast -- Presented jointly by Xilinx and Signal Consulting

Hey All,

Here's a quick reminder about the webcast we'll be putting on tomorrow.
Continuing the signal integrity theme of the previous Xilinx/SigCon
webcasts, this one starts into the topic of jitter.  Dr. Johnson
explores jitter fundamentals in the context of system and interface
design using example measurements from FPGA systems.

The broadcast starts tomorrow (Tuesday 10/4) at 11:00am PST.  To attend,
go to the following link:

http://www.techonline.com/community/home/38741

There's some good material in this one; hope to see you there!

-mark

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Kindl, Ludvikx | 4 Oct 2005 00:53
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Re: Jitter Webcast -- Presented jointly by Xilinx and Signal Consulting

Mark,

Where will you keep this presentation for latter viewing?

Ludvik Kindl
Ludvik@...

*********************************

-----Original Message-----
From: si-list-bounce@... [mailto:si-list-bounce@...]
On Behalf Of Mark Alexander
Sent: Monday, October 03, 2005 3:15 PM
To: si-list@...
Subject: [SI-LIST] Jitter Webcast -- Presented jointly by Xilinx and
Signal Consulting

Hey All,
=20

Here's a quick reminder about the webcast we'll be putting on tomorrow.
Continuing the signal integrity theme of the previous Xilinx/SigCon
webcasts, this one starts into the topic of jitter.  Dr. Johnson
explores jitter fundamentals in the context of system and interface
design using example measurements from FPGA systems.

=20

The broadcast starts tomorrow (Tuesday 10/4) at 11:00am PST.  To attend,
go to the following link:
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Mark Alexander | 4 Oct 2005 01:59
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Re: Jitter Webcast -- Presented jointly by Xilinx and Signal Consulting

Ludvik,

All of these webcasts can be accessed from the same web location (the
TechOnline website).  I think there's a lag of a day or two immediately
after the live broadcast, but then the programs can be viewed on-demand.

-mark

-----Original Message-----
From: Kindl, Ludvikx [mailto:ludvikx.kindl@...]=20
Sent: Monday, October 03, 2005 3:54 PM
To: mark.alexander; si-list@...
Subject: RE: [SI-LIST] Jitter Webcast -- Presented jointly by Xilinx and
Signal Consulting

Mark,

Where will you keep this presentation for latter viewing?

Ludvik Kindl
Ludvik@...

*********************************

-----Original Message-----
From: si-list-bounce@... [mailto:si-list-bounce@...]
On Behalf Of Mark Alexander
Sent: Monday, October 03, 2005 3:15 PM
To: si-list@...
Subject: [SI-LIST] Jitter Webcast -- Presented jointly by Xilinx and
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Ahmad Fallah | 4 Oct 2005 07:41
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Santa Clara Valley (SCV) EMC Chapter Meeting--11 October, 2005

Hello all, 
Please join us for the next meeting of the Santa Clara Valley EMC chapter, on Tuesday 10-11-05.

The meeting will start at 5:30 PM with a social that includes food and beverages. All chapter business and
other announcements will precede the technical presentation due to start at 7:00 PM.  

The October issue of the Spectrum Lines can be accessed at www.scvemc.org .  An abstract of the technical
presentation and the speaker bios are provided below. 

IEEE/EMC Society Meeting
October 11, 2005 
Time:     Social 5:30 p.m.  Presentation 7:00 p.m. 

Place:     Applied Materials Bowers Cafeteria

3090 Bowers Ave., Santa Clara, CA 95051-0804

Subject: Practical Shielding Theory and Design Fundamentals

Speaker:  Michael J. Oliver

It is important for electronic and hardware engineers to not only be knowledgeable of a products intended
function and performance, but also the ability of the product to perform within electromagnetic
compatibility (EMC) limits.  In this talk, practical shielding theory and design fundamentals are
introduced that includes crosstalk, electromagnetic fields, board level, and enclosure shielding.  A
segment on testing of board level shields is presented affiliated with an aperture attenuation modeling
program used to model attenuation characteristics prior to expensive FCC/CE compliance testing. 
Finally, honeycomb vent panels and respective plating attenuation comparisons are discussed.  

Not addressed in this talk, but as background information; standard EMC limits are maintained by the
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Doug Smith | 6 Oct 2005 06:02

controlling varialbles in test setups

Hi All,

I have been writing again and this month's Technical Tidbit on my 
website, http://www.dsmith.org , discusses the need to control stray 
parasitics in tests to avoid error and wasted troubleshooting time.

Abstract: It is imperative that test variables be controlled to avoid 
testing errors when looking for design problems or during compliance 
tests. Making measurements to characterize the test setup is one way 
to accomplish this.  Using an ESD example, the use of current probes 
during testing is demonstrated as a way to monitor and control 
variables in the ESD test setup and equipment.

The link to the article is the picture of the experimental test setup 
at the bottom of the home page at http://emcesd.com .

Doug
--

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     ___          _       Doug Smith
      \          / )      P.O. Box 1457
       =========          Los Gatos, CA 95031-1457
    _ / \     / \ _       TEL/FAX: 408-356-4186/358-3799
  /  /\  \ ] /  /\  \     Mobile:  408-858-4528
|  q-----( )  |  o  |    Email:   doug@...
  \ _ /    ]    \ _ /     Website: http://www.dsmith.org
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Christopher R. Johnson | 6 Oct 2005 22:41
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Problems with IBIS2SPICE

I am trying to the free (V1.4) version of IBIS2SPICE from Intusoft.  It 
seems to load the template file and IBIS model fine, but when I select 
GENERATE after selecting a model, no matter what I do, it generates a 
zero length ".lib" output file.  It does not generate any errors.  I 
know that it is reading the .mdl file because I added additional options 
and they show up in the options drop down.  Adding additional output 
lines to the .mdl file still results in a zero length file.  It is as if 
it is ignoring the commands in the .mdl file.  It definitely creates a 
new file each time because the time stamp changes, but the file is 
always blank.

Any input (actually any output) would be appreciated.

Chris Johnson

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Kamran Azizi | 6 Oct 2005 22:51
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s-parameter in cadence

I am having a lot of problem in using s parameter out of HFSS in cadence spectere.  Seems like there are some
tricky setups except fmax, step, ..... any help? I appreciate it

Kami
		
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Lynne D. Green | 7 Oct 2005 00:32
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Re: s-parameter in cadence

If it were me, I would contact Agilent and/or Cadence for Support.

- Lynne 

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of Kamran Azizi
Sent: Thursday, October 06, 2005 1:52 PM
To: si-list@...
Subject: [SI-LIST] s-parameter in cadence

I am having a lot of problem in using s parameter out of HFSS in cadence
spectere.  Seems like there are some tricky setups except fmax, step, .....
any help? I appreciate it

Kami

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Gmane