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TerenceHsieh | 1 Aug 2005 08:58
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true differential IBIS problem

Dear All
I have generated a truly differential IBIS .But there are some problem.

When I generate the IBIS's rising/falling waveform, I use 50 ohm

for R_fix and common mode voltage for V_fix. In the sig-xp, if I use

the IBIS to drive a 50 ohm resistor terminated to common mode voltage,
the 

waveform is exactly right .But I must use the IBIS to drive a
transmission

line without termination. When I use the IBIS to drive a pure
transmission

line the output waveform's DC level will change and common mode voltage
of 

D+ and D- is different too .How could I generate a truly differential
IBIS 

for pure transmission line network without termination?

B.R.

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Thomas M Tokar | 1 Aug 2005 09:33
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Thomas M Tokar/Cleveland/RA/Rockwell is out of the office.

I will be out of the office starting  08/01/2005 and will not return until
08/03/2005.

I will respond to your message when I return.

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Bi Han | 1 Aug 2005 15:24
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Question on ground trace in TL

Dear friends:

I did an experiment on TL simulation. The transmission line configuration is CPS.

There is no other ground on the chip.

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

                 +++++++++         +++++++++++++++++

DIEL          +  sig        +         +      GND                 +

                 +++++++++         +++++++++++++++++

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

SUB

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Case A:  I set GND trace as reference conductor in 2D solver.

Case B:  I set GND trace as signal trace, and place another reference conductor far away.

Both cases are simulated in .AC analysis. 

In case A, it is a 1 conductor case and the R_term is placed between SIG and ideal ground (node 0 in hspice).

In case B, it is a 2 conductor case and the R_term is placed between two conductors and does not connect to
ideal ground;
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steve weir | 1 Aug 2005 15:42

Re: Question on ground trace in TL

Mike,

Your results are correct.  Why would a large structure not resonate?  Your=
=20
confusion seems to be the fact that people in a number of situations=20
disregard these resonances.  Sometimes that is OK, other times it is not.

Steve.
At 09:24 PM 8/1/2005 +0800, Bi Han wrote:
>Dear friends:
>
>
>
>I did an experiment on TL simulation. The transmission line configuration=
=20
>is CPS.
>
>There is no other ground on the chip.
>
>
>
>++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>
>
>
>                  +++++++++         +++++++++++++++++
>
>DIEL          +  sig        +         +      GND                 +
>
>                  +++++++++         +++++++++++++++++
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Muranyi, Arpad | 1 Aug 2005 17:44
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Re: ??: Re: How to use Intel's model?

Abe,

Unfortunately no.  We do not have a standard verification
procedure for the entire company, each group does their=20
own thing, and I can't speak for everyone.

Arpad
----------------------------------------------------------

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] =
On Behalf Of ariazi
Sent: Friday, July 29, 2005 5:41 PM
To: si-list@...
Subject: [SI-LIST] Re: ??: Re: How to use Intel's model?

Dear Arpad,

Can you outline what verification tests are done on an Intel IBIS model
before releasing it to a customer?

Thank you,

Abe
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Bob Ross | 1 Aug 2005 18:50

Asian IBIS Summit First Announcement

To All:

The IBIS Open Forum is holding an Asian IBIS Summit Meeting in
Shenzhen, China, a major technology center near Hong Kong.  This
is an early initial announcement for longer term planning.

Several companies listed below are cp-sponsoring this large event
to be held at the luxurious Crowne Plaza Hotel.  We are planning for
about 200 attendees including several IBIS experts from the US.

We encourage Asian technical contributions.  We expect a full agenda
of relevant material.

Bob Ross
Teraspeed Consulting Group

Lance Wang
Cadence Design Systems

-----------------------------------------------------------------------
                              ASIAN IBIS SUMMIT
                               FIRST CALL FOR
                       PARTICIPATION AND PRESENTATIONS
-----------------------------------------------------------------------

http://www.eda.org/pub/ibis/summits/dec05/ASIAN_IBIS_SUMMIT_CHINESE.pdf

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

               A S I A N   I B I S   S U M M I T   M E E T I N G
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Mike S. | 2 Aug 2005 12:45
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Ground plane question

Hello to all
I'm designing a daughter card (more like a connector expansion card)
for digital low frequency PWM input/output. This daughter card
connects to the motherboard with 2 stack connectors (similar to PC104
but a lot smaller) separated by 1 inch. Both these connectors have
ground pins. One is only for input, and the other only for output. The
daughter card is a dual layer board. Since the trace routing is very
simple I will use the bottom layer as a ground plane. My question is:
Should the ground plane be connected to both connectors, or, to avoid
ground loops (with the motherboard) should I do two ground planes
(both in the bottom layer) one for each stack connector? One ground
plane would be under the input stack connector and the digital input
connectors. The other would be under the output stack connectors, the
digital output connectors (these are 3 way connectors to drive servos)
and an alternate power supply to drive the Vcc pin of each output
connector to the servos (possibly high currents).
Any pointers, suggestions, design examples?
Thanks in advance
Best Regards
Bruno
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Ivan Zhang | 2 Aug 2005 16:53
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回复： Re: Question on Obtaining Z parameter through VNA

Dear Zhangkun

First of all, I'd like to express my appreciation to you for your rapid feedback, but I was wondering how i can
get these papers written by Mr. Istvan Novak, or the whole name of his paper. Hope you can give me some clues. Thanks.

Best Regards

Ivan
Zhangkun <zhang_kun@...> дµÀ£º
Dear Ivan

There are several paper, written by Istvan Novak, are about this topic.

Best Regards

Zhangkun
2005.8.2
----- Original Message ----- 
From: "Ivan Zhang" 
To: 
Sent: Tuesday, August 02, 2005 11:30 AM
Subject: [SI-LIST] Question on Obtaining Z parameter through VNA

> Dear all. 
> I got to know this method by chance, however, the author of the paper doesn't mention how to deduce this
formula. Thus, hope someone can 
> help me. Thanks in advance.
> 
> 
> port1 port2
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Istvan Novak | 2 Aug 2005 17:08
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Re: »Ø¸´£º Re: Question on Obtaining Z parameter through VNA

Ivan,

You can download the manuscripts from http://home.att.net/~istvan.nov=
ak/

Best regards,
Istvan

Ivan Zhang wrote:
> Dear Zhangkun
> =20
> First of all, I'd like to express my appreciation to you for your r=
apid feedback, but I was wondering how i can get these papers written=
 by Mr. Istvan Novak, or the whole name of his paper. Hope you can gi=
ve me some clues. Thanks.
> =20
> Best Regards
> =20
> Ivan
> Zhangkun <zhang_kun@...> =D0=B4=B5=C0=A3=BA
> Dear Ivan
>=20
> There are several paper, written by Istvan Novak, are about this to=
pic.
>=20
> Best Regards
>=20
> Zhangkun
> 2005.8.2
> ----- Original Message -----=20
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Ray Anderson | 2 Aug 2005 17:01
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Re: 回复： Re: Question on Obtaining Z parameter through VNA

Ivan-

Most of Istvan's published papers can be found at this URL:

http://home.att.net/~istvan.novak/papers.html

Several of his papers deal with the measurement of plane impedances, =
however look at this one as a good starting place:

http://home.att.net/~istvan.novak/papers/DC03-East_HP-TF1_SUN.PDF

(see equation 4 on page 8 of the paper)

-Ray

Raymond Anderson
Senior Signal Integrity Staff Engineer
Product Technology Department
Advanced Package R&D
Xilinx Inc.

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] =
On Behalf Of Ivan Zhang
Sent: Tuesday, August 02, 2005 7:53 AM
To: Zhangkun; si-list@...
Subject: [SI-LIST] =BB=D8=B8=B4=A3=BA Re: Question on Obtaining Z =
parameter through VNA
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Gmane