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rajneesh.raveendran | 1 Feb 2005 07:32

- Difference between High Current Low Voltage and Low Current High Voltage circuits

Hello All,

My apologies as I feel this question may not be directly related to
SI-LIST.

Today's processors are using very low voltages at high currents (e.g.
currents in the range of 20-30 A at 1.2 to 1.5 V of core operation). I
would like to know whether the manufacturers of chips get any additional
benefit by going to high currents at low voltages. What will be the
situation like if you use low currents at high voltages (say 3.3V or
5V)? My premise is that the power consumption being the product of
voltage and current is the same (e.g. 20A  <at>  1.5V is the same as 9.09A  <at> 
3.3V).

Regards,
Rajneesh

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john | 1 Feb 2005 07:58
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Re: Input Clock phase noise and TX eye closurein SERDES

Sorry I didn't mean to remain anonymous.. just typed ctrl S before I'd 
finished writing:-)

Regards

John

johndp@... wrote:

>I'm trying to relate reference clock phase noise to eye closure in a TX SERDES application. At this time I'm
only interested in this area of the TX performance, as I'm trying to specify a clocking scheme for a much
larger design. Assuming a second order TX PLL I can come up with an expression that relates the reference
clock phase noise to the transfer characteristic of the PLL. However I'm stuck with an intergral to work
out the RMS jitter of the reference, the upper limit of which is set by the 3dB point of the PLL, I'm not sure
how to set the lower limit. I've read in a couple of places for example ref (1), a figure of 10KHz but can find
no analytical basis for this figure.
>
>
>Any pointers much appreciated
>
>
>ref (1) Random Jitter - What Is Really Going On?
>October 22, 2001 - CommsDesign.com 
>
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ahmad_s03 | 1 Feb 2005 08:28
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Favicon

a simple question


Hello friends,

Hope everyone is doing fine. Can anyone give me a jump start on how 
to use PLD (Programmable Logic design) in the PROTEL. What is it ... 

Is it the glue logic to minimize some software overhead ... Or is it 
something similar to Verilog (FPGA) .... 

Regards
Ahmad

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Stefan Ludwig | 1 Feb 2005 08:31

Re: - Difference between High Current Low Voltage and Low Current High Voltage circuits

Hi Rajneesh,

the low voltages used in today's processors are mainly due to two factors:

- power is related to capacitance times frequency times voltage 
*squared*, P = C*f*V^2, so if you half the voltage, you use 1/4 of the 
power.
- shrinking feature sizes: the smaller and closer together the 
transistors get, the lower the voltage has to be to not cause a 
malfunctioning of the devices.

Note: you could build a processor running at 5V in today's 90nm 
technology, but its transistors wouldn't have a 90nm feature size and it 
wouldn't run at 3GHz and it wouldn't be 250 million transistors per die 
(or the die would be *very* big!).

Regards,

Stefan

rajneesh.raveendran@... wrote:

>Hello All,
>
>My apologies as I feel this question may not be directly related to
>SI-LIST.
>
>Today's processors are using very low voltages at high currents (e.g.
>currents in the range of 20-30 A at 1.2 to 1.5 V of core operation). I
>would like to know whether the manufacturers of chips get any additional
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Gopalakrishnan Sethuraj | 1 Feb 2005 15:29
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PCB high Speed Design books

Hello Gurus,

Good evening..

Could you please refer the high speed design books related PCB design, Timing analysis, Signal Integrity
and related to  PCB stuff.This could be learning level, middle level, and advanced levels books.  I am
collecting all books related to PCB stuff. It will be really helpful for me

Pls do the needful

Thanks&Regards

Gopalakrishnan

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Andre Grabinski | 1 Feb 2005 15:57
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Deadline Extension SPI 2005

Please consider the following announcement and accept our apologies in case of multiple copies. 

<******************>       SUBMISSION       <******************> 
<******************>   DEADLINE EXTENSION   <******************> 
<******************>   February 08th, 2005   <******************> 

At the request of a great many of potential authors we have decided to extend the deadline for paper
submission. New deadline is now February 08, 2005. Accordingly the notification about acceptance will
be moved to March 22, 2005.

<****************************************************************>

Call for Papers
9th IEEE WORKSHOP ON
SIGNAL PROPAGATION ON INTERCONNECTS

Sponsored by the IEEE Computer Society -- Test Technology Technical Council (TTTC)
and by the IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society

May 10-13, 2005
Dorint Sporthotel, Garmisch-Partenkirchen, Germany

http://www.spi.uni-hannover.de

Deadlines ( - extended! - )
- Paper Submission: February 08, 2005 
- Notification of Acceptance: March 22, 2005 

Paper Submission 
Those who wish to contribute to the workshop should send (by e-mail only) a formatted paper of up to four
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johndp | 1 Feb 2005 16:56
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Re: Input Clock phase noise and TX eye closurein SERDES


Craig,

thanks for the reply.

Say for the CDR in a FC-AL system, this has a low frequency 3dB point of Dbaud/1667 which for a 1.0625Gb/s link
is 637KHz. If we combine this with the high pass function of the TX PLL we get a bandpass filter. Looking at
the noise envelope of a good quality source, I can see that it remains relatively flat at about 145dBc/Hz
above 1MHz, and so above the 3dB point of the TX PLL this is being attenuated at 20dB/decade. 

The low frequency point still bothers me. With the break point at 637Khz, the filtering effect is approx
-36dB <at> 10Khz, -56dB <at> 1KHz, -76db <at> 100Hz. The source phase noise is correspondingly -130dBc/Hz <at> 10KHz,
-100dBc/Hz <at> 1KHz and  -65dBc/Hz  <at> 100Hz compared to -145dB/Hz  <at> 1MHz. So down to 1KHz the Filter roll off is
faster than the rise in phase noise, but down at 100Hz, the phase noise is increasing faster than the roll
off. So I still don't quite see how the lower limit is set.

Regards

John

ctwardy@... wrote:
> Hi John;
> The lower limit will be defined by the bandwidth of the clock and data
> recovery (CDR)of the receiver.
> The 10Khz (or 14-20Khz often) lower limit is used as most oscillators
> exhibit a large increase of phase noise below this frequency. Check out any
> phase noise plot of a stable oscillator.
> Any CDR must deal with this.
> Another way to look at it is to compare noise power over various bandwidths.
> Compare the noise in
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Steve Corey | 1 Feb 2005 17:50

Re: capacitor impedance in time domain

Steve -- while I don't understand the details yet of your approach to 
the original problem, it looks like it may rely on applying a feedback 
equation such as Vo = Vin *1/( 1+G/H ) when Vo and Vin are time-domain 
signals.  While this type of equation is used for frequency-domain 
analysis, it's not generally applicable in the time domain unless G and 
H are constant, which would clearly not be the case for a transmission 
line terminated by a capacitor.  As you know, multiplication and 
division of frequency-domain transfer equations become convolution and 
deconvolution, respectively, in the time domain.  In order to apply in 
the time domain an equation derived in the frequency domain, you not 
only have to transform the signals, you also have to transform the 
operators.

This is the same reason why you can't compute what is commonly called an 
impedance by dividing two time-domain signals along the lines of 
Z=(dv/dt)/(di/dt).  At least it won't be closely related to impedance as 
the term is used in standard circuit theory.

Please let me know if I'm misinterpreting your approach to solving the 
original problem, but as I understand it so far, it doesn't look like it 
will give the right results or valid insight into the problem.

  -- Steve

-------------------------------------------
Steven D. Corey, Ph.D.
Time Domain Analysis Systems, Inc.
"The Interconnect Analysis Company."
http://www.tdasystems.com
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Thiago Wellington Joazeiro Almeida | 1 Feb 2005 18:52
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Re: - Difference between High Current Low Voltage and Low Current High Voltage circuits

 Hi Rajneesh

   The power is related to capacitance, frequence and voltage. P =3D =
C*f*V^2, so if you apply 1.5V the power will be much lower than if you =
apply 3.3V.

Regards,

Thiago Almeida

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...]On Behalf Of
rajneesh.raveendran@...
Sent: Tuesday, February 01, 2005 4:32 AM
To: si-list@...
Subject: [SI-LIST] - Difference between High Current Low Voltage and Low
Current High Voltage circuits

Hello All,

My apologies as I feel this question may not be directly related to
SI-LIST.

Today's processors are using very low voltages at high currents (e.g.
currents in the range of 20-30 A at 1.2 to 1.5 V of core operation). I
would like to know whether the manufacturers of chips get any additional
benefit by going to high currents at low voltages. What will be the
situation like if you use low currents at high voltages (say 3.3V or
5V)? My premise is that the power consumption being the product of
(Continue reading)

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Nicklas | 1 Feb 2005 20:03
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Re: Coupled & Lossy Line Model Validation Structure

Thanks Julian. This is a great reading and reference document for the SI 
design community.

In addition to IFS Pro, Microstripes, Ansoft, and Touchstone/HSPICE being 
benchmarked as part of this document, it would be great if other independent 
SI engineers could run Julian's model on other tools (e.g. Cadence and 
Mentor) and publish them in this forum. (I would offer to contribute, but I 
don't have any of the other products). Maybe Julian would be interested in 
incorporating this additional data into his document (providing a single 
unique SI benchmarking source!).

Nicklas
----- Original Message ----- 
From: "Julian Ferry" <julian.ferry@...>
To: <si-list@...>
Sent: Friday, January 28, 2005 15:00
Subject: [SI-LIST] Coupled & Lossy Line Model Validation Structure

>A few months back, I mentioned that we at Samtec were working on a paper
> about lossy line models.  We're still not completely finished, but we have
> some initial segments ready. They are available on our website now.
>
> The first part discusses a reference structure which we have been using
> for
> a few years for validating models and simulations. We have built the
> structure (which we call the Golden Standard) physically, and have used it
> to investigate and validate new test procedures.  We have found the Golden
> Standard to be so useful, that we thought other SI Engineers might be
> interested as well.  Its not rocket science, but we figured, why force
> people to re-invent the wheel?
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Gmane