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Raymond Anderson | 1 Jun 2004 17:34
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Passivity Enforcement Matlab Code

Any of the list members who are interested in passivity enforcement as 
it pertains to modeling may be interested in the Matlab code just 
released by Dr. Bjorn Gustavsen of SINTEF Energy Research in Trondheim, 
Norway.
He writes:

> Hi Raymond,
>  
> You may want to announce on your list-server that a package for
> passivity enforcement (QPpassive.zip) has now been added to the site
> http://www.energy.sintef.no/produkt/VECTFIT/home.asp
>  
> Best regards,
> Bjorn

This code utilizes quadratic programming techniques.

 From Bjorn's web page:
------------------------------------------------------------------------

This package contains a post-processing procedure for enforcing 
passivity of a model given on pole-residue form. This is done by 
introducing the passivity criterion as a constraint equation in the 
least squares problem. The routine requires the user to provide 
frequency samples for the least squares problem and the passivity 
constraint. A large number of options is available. 

Download: QPpassive.zip*

* <http://www.energy.sintef.no/produkt/VECTFIT/QPpassive.zip>
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Mahesh Krishnan | 1 Jun 2004 17:43
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Queries related to XTK

Hello all,
I am using epd XTK 3.1 for my simulations. I have 2 queries related to this tool.
1. How do we set up XTK to simulate the eye diagrams?

2. I have the model of a high density connector in MLM (multi-line model) spice format. It includes:
* conn.spi which is the main circuit file, containing pin mapping between the spice nodes and the connector
rows, subcircuits containing inductance, resistance and capacitance subcircuits for the various sections.
* Dat files containing piecewise linear and differential piecewise linear sources.
So far I have used IBIS models with XTK and NOT familiar with use of spice models. I would like to know how I
could interface this model to XTK?

Please let me know.

Thanks,
--mahe.
		
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Jon Powell | 1 Jun 2004 17:58
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Re: Queries related to XTK

Unless they have changed something recently, XTK does not have any direct
SPICE interface. The spice circuits and connectors would have to be changed
into QUAD XTK format. There is a tool in XTK (called spi2mod) that would
assist in translating the actual .spi circuit, but the other passive
circuits would have to be changed by hand. This would not be too hard if the
connection information does not involve coupled transmission lines (you
could create QUAD XTK subcircuit files).

Have you tried calling Mentor customer support?

What version of XNS are you using?

regards,
jon

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...]On Behalf Of Mahesh Krishnan
Sent: Tuesday, June 01, 2004 8:43 AM
To: si-list@...
Subject: [SI-LIST] Queries related to XTK

Hello all,
I am using epd XTK 3.1 for my simulations. I have 2 queries related to this
tool.
1. How do we set up XTK to simulate the eye diagrams?

2. I have the model of a high density connector in MLM (multi-line model)
spice format. It includes:
* conn.spi which is the main circuit file, containing pin mapping between
(Continue reading)

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Lynne Green | 1 Jun 2004 22:14
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Re: IBIS question!!

Answers inserted.
- Lynne

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On
Behalf Of ???
Sent: Monday, May 31, 2004 5:20 AM
To: si-list@...; akvarma@...
Subject: [SI-LIST] IBIS question!!

Dear All,
    I have some questions about creating IBIS file for PCIExpress(analog
signal).
1. Does the IBIS model is better when DC voltage sweep of VI table is
smaller??

-- Yes.  Better yet, a table has more points where the slope is changing
fastest, and fewer where is changing slowly.  (Generally, too many points
slows simulation; too few points reduces accuracy.)

2. If the output voltage swing of the pad is 0~3.3V, does it means the
voltage range(0V~3.3V) of the VI table is enough.

-- The reflection at the end of a transmission line could DOUBLE the signal
swing.  So you would need -3.3 to 6.6 (2*3.3) for each V-I table voltage
range.

Best Regards
Tina
(Continue reading)

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Kevin Khuu | 1 Jun 2004 22:41
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6-layer vs 7-layer PCB Stackup

Hi All,

I'm working on a backplane design and come up with the following 7-layer PCB 
stackup:

1) Signal (Single Ended Signals)
2) +5V
3) GND
4) Signal (Diffential Signals, high speed)
5) GND
6) +12V
7) Signal (Single Ended Signals and +3.3V trace)

I don't really need two GND planes, but the reason I added the second GND 
plane (layer 5) was because of symmetry and balancing PCB stackup.  How does 
this stackup compare to the 6-layer stackup (without the second GND layer on 
layer 5)?

Your comments/ideas would be greatly appreciated.

Thanks,
Kevin

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Mirmak, Michael | 1 Jun 2004 22:56
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Agenda - IBIS Open Forum Summit, June 8, 2004

------------------------------------------------------------------
                               =20
                    AGENDA, IBIS SUMMIT MEETING
                           June 8, 2004

                    Manchester Grand Hyatt Hotel
                       San Diego, California

                          Room: Edward AB
                       (check signs at site)

------------------------------------------------------------------

8:00 AM     Refreshments & Sign In

8:30 AM     Introductions
            - Welcome to Summit
            - Introductions
            - Opens for Issues, Discussion Topics

8:45 AM     IBIS Chair's Report
            Michael Mirmak, Intel Corp.

9:15 AM     The IBIS Model Review Committee
            Lynne Green, Green Streak Programs

9:45 AM     Election of IBIS Officers=20

10:00 AM    Break with Refreshments
(Continue reading)

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steve weir | 1 Jun 2004 23:10

Re: 6-layer vs 7-layer PCB Stackup

Kevin,

I would not reference signals with any kind of rise time under 5ns against 
a 12V supply that has nothing to do with your logic.

For a six layer backplane with very directional routing where you need a 
whole plane for each +5V and 12V, I would put both of those in the middle:

1 Ground
2 Signal / 3.3V
big space
3 +12
4 +5
big space
5 High speed differential
6Ground

The routes on layer 2 can be denser than before so hopefully you would not 
need to go to eight layers.

Steve
At 01:41 PM 6/1/2004 -0700, Kevin Khuu wrote:
>Hi All,
>
>I'm working on a backplane design and come up with the following 7-layer PCB
>stackup:
>
>1) Signal (Single Ended Signals)
>2) +5V
>3) GND
(Continue reading)

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Moran, Brian P | 1 Jun 2004 23:07
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Re: 6-layer vs 7-layer PCB Stackup

Kevin,

Your 7 layer stackup may look symetrical but if you fill in the pre-preg
and core designations
it becomes clear that its not actaully symetrical. Not unless you have
back to back pre-pregs in
the center of the stackup.  I'm not a PCB fab guy but it doesn't look
kosher to me. You'd be better
off going with 6 layers, or if neccessary to a truly symetrical 8 layer.
Money spent on backplanes
is usually money well spent.=20

Brian P. Moran=20
Calistoga SIE Kit Leader=20
Intel Corporation=20
brian.p.moran@...=20

-----Original Message-----
From: si-list-bounce@... [mailto:si-list-bounce@...]
On Behalf Of Kevin Khuu
Sent: Tuesday, June 01, 2004 1:42 PM
To: si-list@...
Subject: [SI-LIST] 6-layer vs 7-layer PCB Stackup

Hi All,

I'm working on a backplane design and come up with the following 7-layer
PCB=20
stackup:
(Continue reading)

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Kevin Khuu | 2 Jun 2004 00:55
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Re: 6-layer vs 7-layer PCB Stackup

How about this 8-layer stackup?

1) Signals (Single Ended)
2) GND
3) Signals (Differential)
4) +5V
5) +12V
6) Signals (Single Ended)
7) GND
8) Signals (Single Ended)

Thanks.
Kevin

>From: "Moran, Brian P" <brian.p.moran@...>
>To: <kevin98146@...>, <si-list@...>
>Subject: RE: [SI-LIST] 6-layer vs 7-layer PCB Stackup
>Date: Tue, 1 Jun 2004 14:07:28 -0700
>
>Kevin,
>
>Your 7 layer stackup may look symetrical but if you fill in the pre-preg
>and core designations
>it becomes clear that its not actaully symetrical. Not unless you have
>back to back pre-pregs in
>the center of the stackup.  I'm not a PCB fab guy but it doesn't look
>kosher to me. You'd be better
>off going with 6 layers, or if neccessary to a truly symetrical 8 layer.
>Money spent on backplanes
>is usually money well spent.
(Continue reading)

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Salkow, Steven | 2 Jun 2004 00:55
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Re: 6-layer vs 7-layer PCB Stackup

Kevin:
In practice, there is no such thing as a seven layer board as it would
be pointless to leave a laminate with nothing on one side. The laminator
wants to see copper on both sides to balance the process.
You should check out the cost of a six layers versus eight. There may be
little cost difference but the added ground plane can help with EMI and
reduce noise on power planes. The rise time of your signals and the
number of lines simultaneously switching make a very significant
difference.
Steve's stackup below would likely be quiet for EMI but if the board in
going into an enclosure anyway, the outside Microstrip layers are not
being used well. Keep in mind, Microstrip propagates faster than
stripline. Steve's stackup has only two trace layers which may make it
tough to route signals.
The differential layer, as shown in Steve's  stackup is not symmetrical

I started with your original stackup of seven and added one more GND
layer. It may make sense to swap the +3.3V plane with the +5V plane. I
would guess there is more +3.3V.

	
	1) Signal (Single Ended Signals and High-speed Microstrip)
	2) +5V
	3) GND
	4) Signal (Diffential Signals, high speed)
	5) GND
	6) +12V and +3.3V trace
	7) GND
	8) Signal (Single Ended Signals and High-speed Microstrip)
(Continue reading)

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Gmane