timoceous | 12 May 2004 22:36
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Cascading PLL

Hi Guru,

   I have a question on the one PLL driving another
PLL.  I know that if both PLL has the same bandwidth
it is not a good idea.  So my questions is what should
the 1st PLL bandwidth should be, should be be narrow
band and the 2nd PLL to be a wideband PLL?  Or is it
the
other way around?  Is there any articles discussion
this
issue.  Thanks in advance.

Regards,

Tim

	
		
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Doug Smith | 13 May 2004 01:38

a simple EMI source

I have posted the May Technical Tidbit on emcesd.com based upon a 
design from one of this list's members, Edward Witte. The article 
describes a simple to build EMI generator for debugging circuits.

Abstract: An easy to build and use EMI generator designed by Edward 
Witte is described. "Home brew" test equipment such as this can be 
very useful in troubleshooting equipment problems.

Doug
-- 
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     ___          _       Doug Smith
      \          / )      P.O. Box 1457
       =========          Los Gatos, CA 95031-1457
    _ / \     / \ _       TEL/FAX: 408-356-4186/358-3799
  /  /\  \ ] /  /\  \     Mobile:  408-858-4528
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Bashir, Shiraz (MED | 13 May 2004 01:46
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Re: 800MHz Radiated Emissions

interestingly we found that a serial 9-pin connector was floating i.e.,
it was not connected to ground.
When we connected it to ground we got like ~7db margin below class A.

Then we removed that connector (we dont need that for production),
radiated emissions become worse ..less than 1 db from Class A limit.
then we removed RS232 IC which was feeding signal to that connector
(thought that lines may be acting as antenna)..it become more worse...>
3 db from Class A limit ..

Anybody has clue why it is happening...

also on separate experiement we changed termination scheme from series
(33 ohm) to parallel (50 ohm to ground) at load..we supress 800MHz but
900MHz failed test...any idea why ?
as parallel termination draws enormous amount of current so we try 100
ohm to Vcc and 100 ohm to ground termination at load..it matches 50 ohm
transmission line but results at 800Mhz are worse...

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...]On Behalf Of Bashir, Shiraz (MED)
Sent: Wednesday, April 28, 2004 7:37 AM
To: 'si-list@...'
Subject: [SI-LIST] 800MHz Radiated Emissions

Hi,

We are using a MPC9448 Clock Fanout buffer (1:12) whose input is 100MHz
+/-
(Continue reading)

Michael Poimboeuf | 13 May 2004 01:48
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Re: Cascading PLL

The answer regarding bandwidths is: It depends.

In fact you can cascade PLLs even of the same bandwidth if you specify
the amount of peaking you allow. Multiple PLLs are allowed in SONET,
AES3, and many other interfaces. The key design parameters to keep in
mind for PLLs used for computers and communications are the peaking
frequency =3D omega_p (wp), and the peaking magnitude Hp (usually
specified in dB). If Hp is small enough, then wp can be whatever your
application needs. [see Wolaver, Ref1, below]

Applications that need tight coupling between clocks and data need wide
bandwidth (large wp), applications that require low jitter need narrow
bandwidth (small wp) to reject out of band phase noise.

The rule of thumb about not cascading PLLs comes from experience with
under or critically damped PLLs which exhibit high peaking magnitude
(large Hp). Since identical under, or critically damped PLLs that peak
at the same frequency will exhibit peaking gain of NxHp, where N is the
number of cascaded PLLs, you can see that cascading two such critically
damped PLLs yields an underdamped system and cascading a relatively
small number of such underdamped PLLs yields an unstable system.

One example of multiple PLLs cascaded comes from AES3 (aka AES/EBU),
where up to 10 PLLs of the same bandwidth and peaking can be cascaded
and still meet spec.

--
mkp@...
Michael Poimboeuf

(Continue reading)

Rajesh Anantharaman | 13 May 2004 02:32
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definition of ports

Hi,
I am working on building a PCIX interconnect and have been studying the spec for it. Can somebody explain
what an upstream and downstream port/Lane means? Thanks

Raj
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databits | 13 May 2004 03:49
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Re: 800MHz Radiated Emissions

When you "removed the connector....  Did you plug the hole that was in =
the
chassis??
ap

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] =
On
Behalf Of Bashir, Shiraz (MED)
Sent: Wednesday, May 12, 2004 6:46 PM
To: 'si-list@...'
Subject: [SI-LIST] Re: 800MHz Radiated Emissions

interestingly we found that a serial 9-pin connector was floating i.e., =
it
was not connected to ground. When we connected it to ground we got like =
~7db
margin below class A.

Then we removed that connector (we dont need that for production), =
radiated
emissions become worse ..less than 1 db from Class A limit. then we =
removed
RS232 IC which was feeding signal to that connector (thought that lines =
may
be acting as antenna)..it become more worse...> 3 db from Class A limit =
..

Anybody has clue why it is happening...
(Continue reading)

Shiraz Bashir | 13 May 2004 05:06
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EMC Engineer Job

Hi,

There is opening in our company for job with following
requirements. If you are interested or you know any
body who is interested in , please send me resume
asap.

This is located in Milwaukee, WI, USA..

thanks,
shiraz

Analyze  and  direct  designs  and  solutions  for 
EMC  compliance  for  medical  and  ITE  products. 
-Work  closely  with  varied  design  teams 
-Perform  training  in  printed  board  design 
techniques,  grounding  bonding  and  shielding  for 
RF  design 
-Perform  training  to  end  users  of  EMC  labs 
-Develop  and  maintain  automated  test  solutions 
-Develop  control  plans  for  EMC  compliance 
requirements 

 Qualifications/Requirements:  
BSEE  with  a  background  in  RF  design 
Knowledge  of  EMC  medical/ITE  standards  and  test 
methods 
Effective  team  player  and  contributor 
Ability  to  drive  improvements  in  product  design 

(Continue reading)

Muhammad azam | 13 May 2004 06:46
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suggestions for routing fpbga of 1152 pins

Dear all,
I want to design a card consists of 1152pins,an FpBGA,it is .8mmpitch bga.
Anyone plz may suggest about the specifications of routing.
Thanks
azam
wuby <r92101@...> wrote: 
Dear all:
How to simulate the kvco using spice?

Is there any other tool to simulate it?

And how !?

Thank you a lot!

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Tayyab Jamil | 13 May 2004 07:06

Re: suggestions for routing fpbga of 1152 pins

You can use 18/10 mil (pad/hole) via with 4/4 mil (track/clearance) routing
to escape the BGA. Row count in the package will determine the minimum
number of rows required to escape the BGA.

Tayyab

-----Original Message-----
From: Muhammad azam [mailto:azam_si_engr@...]
Sent: Thursday, May 13, 2004 9:47 AM
To: si-list@...
Subject: [SI-LIST] suggestions for routing fpbga of 1152 pins

Dear all,
I want to design a card consists of 1152pins,an FpBGA,it is .8mmpitch bga.
Anyone plz may suggest about the specifications of routing.
Thanks
azam
wuby <r92101@...> wrote: 
Dear all:
How to simulate the kvco using spice?

Is there any other tool to simulate it?

And how !?

Thank you a lot!

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To unsubscribe from si-list:
si-list-request@... with 'unsubscribe' in the Subject field
(Continue reading)

Amar Othman | 13 May 2004 05:22
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"Sigrity's PowerSI tool"

Hi All,

I am looking at Sigrity's PowerSI tool for board level power integrity analysis. I was
wondering if any one had used this tool and can comment on its performance, and ease of use. 

Also, I was wondering if there are other similar tools to explore. 

Thanks,

Amar

		
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Gmane