Bob Ross | 22 Oct 01:38 2014

Asian IBIS Summit (Yokohama) - Third Announcement

To All:

The IBIS Open Forum will hold its ninth Asian IBIS Summit Meeting

on Thursday, November 20, 2014 in Yokohama, Japan.  We have a full

program and are starting the meeting on Thursday afternoon.

JEITA (Japan Electronics and Information Technology Industries

Association) is the primary event sponsor.  An Embedded Technology

Conference and Exhibition on November 19-21, 2014 is co-located with

the IBIS Summit.

Note that we are also holding two other Asian IBIS Summits:

  Shanghai, China   Friday, November 14, 2014

  Taipei, Taiwan    Monday, November 17, 2014

Bob Ross

Teraspeed Labs

Yukio Masuko

Cadence Design Systems

(Continue reading)

VenugopalUllerahally, Venu | 21 Oct 23:07 2014

DDR3 Memory Power Measurement

Hi Experts,
I am trying to measure DDR3 total power consumption and needed some help.

The challenge is to measure only the power consumed by DDR3 excluding memory controller. We don't have FB or
other means to control power only to DDR(We have 1.5V plane).I thought of measuring the power through
decaps,but that doesn't seems to cover the total power.

Any help is really appreciated.

Thanks,

Venu

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Felton, Mickey | 21 Oct 22:14 2014

Best groups to join for IEEE

Hello, I was wondering what were the best groups to join within IEEE to get a focus on the Signal Integrity
topics being discussed. It seems they are scattered across many different groups, but if there were 3 or 4
major ones it would be great to know. Clearly if the focus was just SI on packages that would be the group to
join but would like a more broader focus if possible.
Thanks in advance..
Mick 

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Grasso, Charles | 21 Oct 22:05 2014

With Apologies - RE: [Recrafted] Serpentining of Differential Pairs

Hello and thank you to all that have responded -.
I left out an important piece of detail:

Due to space constraints the concept of the double curve approach is
not feasible and some other designs (a large bulge in one pair or  little bulges
along the length of one pair) are being proposed.

Has anyone done a study of the "non- serpentine" alternatives for skew control.?

[I don't have access to a 3M modeling tool :()

Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t) 3032042974@...
(e) charles.grasso@...
(e2) chasgrasso@...

From: Grasso, Charles
Sent: Tuesday, October 21, 2014 1:22 PM
To: si-list@...
Subject: [Recrafted] Serpentining of Differential Pairs

[Recrafted - Sorry!]
Hello all,

I have a question on how to achieve length symmetry  of differential pairs using serpentine designs.
(Continue reading)

Grasso, Charles | 21 Oct 21:22 2014

[Recrafted] Serpentining of Differential Pairs

[Recrafted - Sorry!]
Hello all,
I have a question on how to achieve length symmetry  of differential pairs using serpentine designs.
What is the "best" (or "least worst"!) serpentine design that can be used to minimize the
mode conversion that is the inevitable result of having a serpentine in the first place?

(I have a wealth of information on the effects of vias (placement/symmetry and so on)
but I seem to be coming up short on the relative merits of the different types/styles  of
serpentine design.)

Thanks!

Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t) 3032042974@...<mailto:3032042974@...>
(e) charles.grasso@...<mailto:charles.grasso@...>
(e2) chasgrasso@...<mailto:chasgrasso@...>

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Grasso, Charles | 21 Oct 20:55 2014

Serpentining of Differential Pairs

Hello all,
I have a question on how to achieve symmetry  of differential using serpentine design.
What is the "best" (or "least worst"!) serpentine design for matching differential pairs?
I am concerned primarily in minimizing the emissions profile of our designs - but
any and comments will be appreciated!

(I have a wealth of information on the effects of vias (placement/symmetry and so on)
but I seem to be coming up short on the relative merits of the different types/styles  of
serpentine design.)

Thanks!

Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t) 3032042974@...
(e) charles.grasso@...
(e2) chasgrasso@...

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Chen, Sherman | 21 Oct 16:07 2014

time domain simulation w/ PDN planes

Hello experts,
I'm trying to evaluate the impact of power plane noise on the HS signals. The sim setup would require to apply
a noise source on the PDN (somewhere btw power plane and ground plane), also a PRBS source at the initial end
of the t-line. To my knowledge it looks only Cadence Sigrity Speed2000 can run such SI/PI combined sim
since the feedback I got from Keysight and ANSYS both said that neither ADS nor SIWave can handle such sim
case where time domain sim needs to be run w/ the noise coupled from power/ground plane. Note the coupling
needs to be from the whole plane rather than injected at one point for the latter we can simply use a sparam
model of the PDN as the means of noise injection but this would not be the equivalent of the plane coupling, right?
Any suggestion will be appreciated.

Best Regards,

Sherman Chen
Signal Integrity
EMC Global Hardware Engineering
Tel: +86 21 60951100-3329

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Mallikarjun K | 21 Oct 02:41 2014
Picon

Point to point simulation results

Hi,
I am trying to simulate a topology.
it consists of driver --> 0 ohm resistor --> MS line (length varied from
1000 mils to 10000 mils) ---> DDR2 dq 533 io(receiver).

I am just simulating to findout how much can be the maximum length, before
signal degrades badly.

As i am increasing the length, i am seeing more degradation at the Driver
than at the receiver. there is degradation at the receiver , but it is OK.

I have uploaded 3 files 1000mils,4800mils and 10000mils
 <at>  10000mils there is delay between input and output but still output
quality and input quality are good compared to 4800 mils case.

why is this? 10000mils case should have more degradation

http://s3.postimg.org/q6wi1e283/ddr2_io_0000_dq_533_MS3_1000.png

http://s2.postimg.org/4qw22kazt/ddr2_io_0000_dq_533_MS3_4800.png

http://s27.postimg.org/o988g61zn/ddr2_io_0000_dq_533_MS3_10000.png

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Garrison, Gene | 21 Oct 01:39 2014
Picon

Intel is looking for an SI Engineer in Hillsboro, OR

Job Description: Designs, develops, evaluates, and validates high speed signaling interfaces on Intel
Architecture boards and systems for the Server market. Determines creative design approaches and
solutions. Conducts experimental tests and evaluates results. 
Responsible for the robust performance and reliability of signaling interfaces through high volume
production, cradle to grave. Duties include the design and definition of a suitable routing topology
through simulation or other means, verifying and approving the final design and routing of the interface
before board tape-out, verifying the signaling performance through testing and margining, and
supporting the debug of any subsequent issues over the life of the product.

Minimum Qualifications:
- Bachelor's degree in Electrical Engineering or equivalent with 4+ years of industry experience or a
Master's degree in Electrical Engineering or equivalent with 2+ years of industry experience.
- 2+ years with high speed PCB design. 
- 2+ years with at least one applicable simulation tool such as HSpice, Cadence Allegro SI, HFSS, etc. 
- Understanding of basic electromagnetic design concepts

Additional preferred skills:
- Knowledge of Intel Architecture system design.
- Experience with EMI layout considerations or simulation.
- Experience with a scripting language, such as Perl.
- The successful candidate must be a self-starter who can work with minimal supervision in a team
environment. 
- Good verbal and written communication and problem solving skills are required.

Please refer to Job Number 745099 at http://jobs.intel.com.

Thanks,
- GeneG
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a.ippich | 19 Oct 12:49 2014

a.ippich@...

http://hartnekkigtog.mvhartog.nl/owt/tffpvgmgkvgqcc.xzggtzcyzzqitnydnfydnfxsthworiaokm
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Douglas Smith | 19 Oct 04:32 2014

an intuitive way to look at shielded cables and pcb traces

 Hi All,
Next week, I am going to deliver a webinar, about an hour, that shows how
shielded cables work in a graphical, intuitive way that is quite different
than anything you have seen, and does not require much math (maybe a little
algebra from high school). This way of looking at shielded cables leads to a
better understanding of how to make a design using such cables work. Even
themost experienced SI or EMC people have not seen an analysis like this,
unless they have attended my courses at Oxford University or my Boulder City
Seminar.

One outcome of this analysis is that a solid rod of metal acts just like a
coaxial cable because of skin effect. How the center conductor is related to
the shield is inseparable from skin effect. Also, a shielded cable acts a
lotlike a common mode choke would that has two wires passing through it
(center conductor and shield in this case) with respect to shield current
andits effect on the center conductor(s).

Here is the scoop from my website:

Time: Thursday,  October 23rd  <at>  10:00 a.m. Pacific time: Shielded Cables
Explained (Simply!)[1]  (This is probably the best treatment of shielded
cables, in terms of being easily understood with no deep math, that is
available anywhere).

  * This Webinar presents a novel way to understand how shielded cables work
using a graphical intuitive technique, no math required. You will never
thinkof shielded cables (and unshielded cables as well as paths on PCBs) in
the same way again. This presentation is good for both beginners and
experienced engineers, and both are not likely to have seen this approach
before. 
(Continue reading)


Gmane