Ajay Dhingra | 25 Oct 20:55 2014
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Fw: AC or DC Coupling Selection


-------- Original Message --------
Subject: Re: [SI-LIST] AC or DC Coupling Selection
From: Ajay Dhingra <ajay.dhingra@...>
To: Orin Laney <olaney@...>
CC: si-list@...

The data rates are around 6Ghz and 8b/10b is also there.
I mainly want to understand how Vcm difference has impact specially in DC Coupled interface and what are
potential reasons of Vcm differences.

What kind of implementations in Rx helps mitigate the Vcm difference problem.

Ajay

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Ajay Dhingra | 25 Oct 18:54 2014
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AC or DC Coupling Selection

Hi All
Could anyone put some light on what criteria should be used to decide for a serial interface that
1. It should use AC or DC coupling
2. How to decide the common mode voltage.
3. how much should be the difference between Vcm of Tx and Rx. What criteria determines this difference in
multi GHz range.

Thanks
Ajay

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Doug Smith | 24 Oct 01:36 2014

switch mode power supply noise (class D amps as well)

Hi All,

I am going to present a one hour web session next Thursday, October 30th 
on a problem a lot of engineers have encountered.

Here are the details:

Next presentation: Thursday,  October 30th  <at>  10:00 a.m. Pacific time: 
Switching Circuits in Electronic Systems (Problems and solutions for the 
design engineer)

Switch mode power supplies (at system and board level) and other 
switching devices like class D amplifiers and pulse width modulation 
controlled devices have caused a lot of noise problems over the years 
resulting in a lot of weekends and evenings at work for engineers. This 
webinar will discuss the four modes of noise generation in switching 
circuits and how to deal with them. The fourth mode is not well known 
yet causes many of the problems due to switching circuits and is not 
covered in specifications.

Did you know that switching circuits generate noise that can cause 
intermittent operation of systems with problems occurring once per hour 
or even less frequently? How this can happen will be discussed and ways 
of debugging this type of problem will be covered. Examples will be 
discussed where switching noise generated in one part of a system caused 
problems in remote parts of the system, including one case where a hard 
drive was corrupted from a meter away and the drive was not even 
connected to the noisy supply causing the problem.

Recommendations from system level to PCB level are given, right down to 
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Chen, Sherman | 22 Oct 20:47 2014

Re: time domain simulation w/ PDN planes

Nilesh,

Thanks for the paper. My question is regarding how to model the coupling from PDN to the transmission line,
not the transmitter or the receiver chip. The coupling effect across the whole span of the tline need to be
calculated. To do that in circuit simulator what I can think of is to use a multi-port sparam which's ports
are extracted btw the locations along the tline and the VRM, at the interval of say lambda/20. At each
location the port need to be set at four points: DP+, DP-, Vcc on power plane, and GND on the ground plane. 
Any comments on this thought? 

-----Original Message-----
From: nilesh_kamdar2@...
[mailto:nilesh_kamdar2@...] 
Sent: Wednesday, October 22, 2014 11:38 PM
To: si-list@...; Chen, Sherman
Subject: RE: [SI-LIST] time domain simulation w/ PDN planes

Sherman

If I understood your question correctly, I believe that this simulation can be handled in ADS. To do this you
need to create an SI/PI model of the physical interconnects that includes all the power/ground planes and
also signal lines. Then you can apply specific time domain stimulus in a Transient simulation. 

Here is a DesignCon 2014 paper that explains how we can do this:

Paper:
http://cp.literature.agilent.com/litweb/pdf/5991-4083EN.pdf

Slides:
http://www.xilinx.com/events/designcon2014/11_WE5Slides_Touchstonev2SIPISParameterModels.pdf

(Continue reading)

Mallikarjun K | 22 Oct 16:26 2014
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Re: Point to point simulation results

The receiver IO model i selected is Without ODT.
I will try with single Pulse.....

On Wed, Oct 22, 2014 at 5:39 PM, preetesh rathod <preeteshrathod@....in
> wrote:

> Hello
>          You haven't mentioned anything about end termination (ODT) if
> you using it. In your case it seems impedance mismatch at both ends. So
> your single pulse reflections may not die out in single cycle which can
> create such type of results at different trace lengths. I suggest you to
> simulate with single edge which will help you to understand what is going
> on in more detail in terms of reflections.
>
> Regards
> Preetesh Rathod
>
>
>   On Tuesday, 21 October 2014 7:30 AM, Bert Simonovich <
> bertsimonovich@...> wrote:
>
>
> This looks like a case of driver impedance mismatch to the transmission
> line. The driver likely has a lower impedance than the transmission line.
> Try increasing the 0 ohm resistor to a value equal t-line impedance minus
> the driver impedance. Eg. if the driver impedance is 15 ohms, and the
> t-line is 50 ohms, then the resistor should be 35 ohms.
>
> Sent from my iPad
>
(Continue reading)

Loyer, Jeff | 22 Oct 14:44 2014
Picon

Ground vias and the land of ID ("It Depends")

At the risk of finding myself embroiled in a furball, I thought I'd see if I could clear up (in my own mind
anyway) some of the effects of ground vias.  I ran 3-D simulations on a pair of single-ended signal vias with
various configurations of ground vias around them and compared impedance, NEXT, and FEXT.  The results
strongly suggest that nearby ground vias are a good investment to reduce via crosstalk.  Of course, if you
can absorb the extra crosstalk, it's a moot point.  And ground vias are often hard to put where we want them,
since they impede routing on every layer, so we seldom have the luxury of all the vias we might like (the "no
xtalk" configuration in the study).
Here's a link to the study.
https://www.filesanywhere.com/fs/v.aspx?v‹6e658761616dab72a2

Note: I'm leaving the presentation a bit vague (leaving out any conclusions, many exact dimensions, and
not stipulating simulation assumptions) on purpose - this should not be regarded as any formal
"report-out".  It's only a "quick-and-dirty" peek at the issue.  Others may duplicate the simulation with
different results, though that seems improbable - I don't see anything leading me to believe they are
fundamentally flawed.  They are not overly complex topologies, so I invite others to replicate the
simulations if the results seem questionable.

And, of course, exact results will depend on design specifics (stackups, via dimensions, etc.).  Your
mileage may vary...

Cheers,
Jeff Loyer

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Bob Ross | 22 Oct 01:38 2014

Asian IBIS Summit (Yokohama) - Third Announcement

To All:

The IBIS Open Forum will hold its ninth Asian IBIS Summit Meeting

on Thursday, November 20, 2014 in Yokohama, Japan.  We have a full

program and are starting the meeting on Thursday afternoon.

JEITA (Japan Electronics and Information Technology Industries

Association) is the primary event sponsor.  An Embedded Technology

Conference and Exhibition on November 19-21, 2014 is co-located with

the IBIS Summit.

Note that we are also holding two other Asian IBIS Summits:

  Shanghai, China   Friday, November 14, 2014

  Taipei, Taiwan    Monday, November 17, 2014

Bob Ross

Teraspeed Labs

Yukio Masuko

Cadence Design Systems

(Continue reading)

VenugopalUllerahally, Venu | 21 Oct 23:07 2014

DDR3 Memory Power Measurement

Hi Experts,
I am trying to measure DDR3 total power consumption and needed some help.

The challenge is to measure only the power consumed by DDR3 excluding memory controller. We don't have FB or
other means to control power only to DDR(We have 1.5V plane).I thought of measuring the power through
decaps,but that doesn't seems to cover the total power.

Any help is really appreciated.

Thanks,

Venu

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Felton, Mickey | 21 Oct 22:14 2014

Best groups to join for IEEE

Hello, I was wondering what were the best groups to join within IEEE to get a focus on the Signal Integrity
topics being discussed. It seems they are scattered across many different groups, but if there were 3 or 4
major ones it would be great to know. Clearly if the focus was just SI on packages that would be the group to
join but would like a more broader focus if possible.
Thanks in advance..
Mick 

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Grasso, Charles | 21 Oct 22:05 2014

With Apologies - RE: [Recrafted] Serpentining of Differential Pairs

Hello and thank you to all that have responded -.
I left out an important piece of detail:

Due to space constraints the concept of the double curve approach is
not feasible and some other designs (a large bulge in one pair or  little bulges
along the length of one pair) are being proposed.

Has anyone done a study of the "non- serpentine" alternatives for skew control.?

[I don't have access to a 3M modeling tool :()

Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t) 3032042974@...
(e) charles.grasso@...
(e2) chasgrasso@...

From: Grasso, Charles
Sent: Tuesday, October 21, 2014 1:22 PM
To: si-list@...
Subject: [Recrafted] Serpentining of Differential Pairs

[Recrafted - Sorry!]
Hello all,

I have a question on how to achieve length symmetry  of differential pairs using serpentine designs.
(Continue reading)

Grasso, Charles | 21 Oct 21:22 2014

[Recrafted] Serpentining of Differential Pairs

[Recrafted - Sorry!]
Hello all,
I have a question on how to achieve length symmetry  of differential pairs using serpentine designs.
What is the "best" (or "least worst"!) serpentine design that can be used to minimize the
mode conversion that is the inevitable result of having a serpentine in the first place?

(I have a wealth of information on the effects of vias (placement/symmetry and so on)
but I seem to be coming up short on the relative merits of the different types/styles  of
serpentine design.)

Thanks!

Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications
(w) 303-706-5467
(c) 303-204-2974
(t) 3032042974@...<mailto:3032042974@...>
(e) charles.grasso@...<mailto:charles.grasso@...>
(e2) chasgrasso@...<mailto:chasgrasso@...>

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Gmane