Mirmak, Michael | 17 Apr 22:41 2014
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European IBIS Summit at SPI 2014 - Third Call for Presentations and Participation

The IBIS Open Forum is holding the 17th European IBIS Summit Meeting along with the 18th IEEE Workshop on
Signal and Power Integrity (SPI 2014), on Wednesday, May 14, 2014 in Ghent, Belgium.

These IBIS Summits are intended to promote exchanges of ideas and methods among users and developers of
IBIS models and associated tools in Europe.  Our thanks to Zuken for kindly sponsoring the Summit.

The meeting is FREE and OPEN to everyone.  You are invited to register and also to submit presentation proposals.

We look forward to seeing you there!

Michael Mirmak

Chair, IBIS Open Forum

===============================================

                 European IBIS Summit at SPI 2014

       Third Call for Presentations and Participation

===============================================

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      E U R O P E A N   I B I S   S U M M I T   M E E T I N G

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Time/Date:         13:00 - 18:00, Wednesday, May 14, 2014

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Gregory R Edlund | 17 Apr 21:24 2014
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Fw: PCIe Gen 3 Compliance Pattern


Probably not too many of you are using a sampling scope to measure RJ, but
in case you are, the magic number is . . .(drum roll please). . . 4680.

The PCIe Gen 3 compliance pattern (short version) is made of 36 blocks of
130 bits each.  This works out to 4680 bits.

Thanks to everyone who pitched in.  Less than 24 hr. turn time.  Pretty
decent.

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901

----- Forwarded by Gregory R Edlund/Rochester/IBM on 04/17/2014 02:21 PM
-----

From:	Gregory R Edlund/Rochester/IBM
To:	si-list@...,
Date:	04/16/2014 04:09 PM
Subject:	PCIe Gen 3 Compliance Pattern

How Long is the Compliance Pattern for PCIe Gen 3?

The spec lists several different types of compliance patterns.  Some of
them look rather large.  I'm not sure which one my device is using, but my
sampling scope won't sync to it.  Anybody out there seen this?
(Continue reading)

EPEPS Admin | 17 Apr 00:30 2014

2014 EPEPS Conference – Call for Papers

Dear Members,
The call for papers for the 23rd Conference on Electrical Performance of Electronic Packaging and Systems
is posted at our website epeps.org<http://epeps.org/> and can be accessed through the link Call for
Papers<http://epeps.ece.illinois.edu/2014%20call_for_papers_epeps.pdf>.  The conference is
held during Oct. 26-29, 2014, in Portland, Oregon. The deadline for submission of manuscripts is June 16,
2014. Also there are great opportunities provided for companies to showcase their products/brands
through structured sponsorships/exhibitions, details of which can be found in the link Sponsorship
Packages<http://epeps.ece.illinois.edu/2014_Sponsorship_Packages.pdf>. We look forward to your
participation in this premier conference on signal integrity, interconnects and electronic packaging.
For more information, please contact EPEPS administrator, Mandy Wisehart via email, epeps-admin@...<mailto:epeps-admin@...>.
Sincerely,
EPEPS Co-Chairs: Dale Becker, IBM, and Jose Schutt-Aine, University of Illinois

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Gregory R Edlund | 16 Apr 23:09 2014
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PCIe Gen 3 Compliance Pattern


How Long is the Compliance Pattern for PCIe Gen 3?

The spec lists several different types of compliance patterns.  Some of
them look rather large.  I'm not sure which one my device is using, but my
sampling scope won't sync to it.  Anybody out there seen this?

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-3
Rochester, MN 55901

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lei li | 16 Apr 11:17 2014
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LPDDR2 derating table problem

Hi, Experts
There are tIS/tIH derating tables in JEDEC LPDDR2 standard (JESD209-2F) for looking up. But in my project,
the slew rate is out of the table. 

For example, in Table105, the maximum CK differential slew rate is 4V/ns, and the maximum CA slew rate is
2V/ns. But my result is CK diff slew rate = 8V/ns and  CA slew rate = 4V/ns. They are out of the table list. 

My problem is how to ensure the derating value of tIS/tIH in my case.

Thanks.

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lei li | 16 Apr 11:06 2014
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LPDDR2 derating table problem

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李磊 | 16 Apr 09:40 2014

LPDDR2 derating table problem

/ÄƗ«¶Äáz·š­ëHKûH׫jا‚Ö›•ë"œ‘"Ï4v²Ö§uªÝü‘m=ÿaÿ~Šå¢‰"ž©ü­Šy²¦º#yËÿ¶¬•ì+j×¢²‹­¡ûaz֛•ïÅ¢·±jje{ø§M¦å{]9þØ^™¬bšé‚)؟}êޞؚ–É^¶­z+8Wùìý©Ý¶¦k¦º`€²W°­«^ŠÍ•þ{ÿëfÊ·¬º[b°"‰÷ì•ì+j×
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李磊 | 16 Apr 08:39 2014

LPDDR2 derating table problem

†/ÞƗ«¶Ëaz·š­ëHKûH׫jا‚Ö›•ë"œ‘"Ï4v²Ö§uªÝü‘m=ÿaÿ~Šå¢‰"ž©ý»­Šy²¦º#yËÿ¶¬•ì+j×¢²‹­¡ûaz֛•ïÞÅ©©•ïâ6›•ítçûazf±Šk¦§b}÷«z{bj[%{
Úµè¬á_ç³ö§vØ^™¬bšé‚É^¶­z+6Wùìý»­›*Þ²émŠÀŠv'ß²W°­«^
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Doug Brooks | 15 Apr 18:29 2014

Re: Date for Gauss's Law of Magnetism

Kieran

Thanks for the insight. I wonder why Wikipedia gives 1867 if Maxwell 
did it in 1865??

I guess the most precise we can be is sometime in the early to mid 1800's.

Doug

At 07:19 AM 4/13/2014, Kieran O' Leary wrote:
>Hi Doug,
>
>Not an exact answer but James Clerk Maxwell's "A Dynamical Theory of the
>Electromagnetic Field" was published in 1865.
>
>This paper contains all four of what we now know as Maxwell's Equations
>including both of Gauss' laws.
>
>http://en.wikipedia.org/wiki/A_Dynamical_Theory_of_the_Electromagnetic_Field
>
>Maxwell formulated 20 equations but these were later reduced to the 4 that
>we are familiar with nowadays by Oliver Heaviside.
>
>No later than 1865 would seem appropriate to me but of course there were
>multiple contributors to the development of these laws.
>
>Hope this helps.
>
>Best regards,
>Kieran
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Amit Agrawal (amiagra2 | 14 Apr 08:43 2014
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Signal Integrity Engineering positions at Cisco San Jose

We are anticipating few job openings for signal integrity engineers in Enterprise
Networking Group (ENG), Cisco, San Jose. The description is
given below. If you are interested, please send your resume or contact
me directly.
Best Regards,

Amit P. Agrawal, Ph.D.
Senior Manager, Hardware Engineering
Enterprise Networking Group
Cisco, San Jose, CA
amiagra2@...<mailto:amiagra2@...>
(408) 424-2732 (Office)

Senior Signal Integrity and Power Integrity Engineer:

An experienced signal integrity engineer is being sought for design and analysis of high speed interfaces
and power distribution network. The successful candidate will be part of signal integrity and power
integrity team and participate in the definition of chip, package, printed circuit board (PCB), and
system interconnects.  Within a concurrent engineering environment, the individual will be part of a
larger team with system architects, logic designers, ASIC engineers, and SI engineers in creation of
next generation networking products.

 This group works on present and next-generation cost-sensitive yet high performance and high volume products.

 Your responsibilities will include but not be limited to:

- Working experience in high speed serial I/O applications, PLLs, CDR, transceiver/SERDES operations
- Definition of signaling and package technology for high performance ASICs
- Simulating and/or analyzing and/or generating power delivery network requirements
- Understanding signal integrity and timing in order to budget and evaluate trade-offs between design
(Continue reading)

Carson Au | 14 Apr 06:42 2014
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What is the intention of this application of ferrite beads?

Hi,
My first post on the reflector! :)

I was looking through some documentation for the Xilinx FPGAs and came
across this schematic diagram (page 72 - UG480 -
http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
)

This is meant to be a circuit to filter or prevent high frequency noise
from coupling onto the inbuilt ADC of the FPGA.

I do not quite understand the intention of Xilinx to recommend the ferrite
bead on the low-side. Xilinx says it is to provide high frequency
isolation. However, as I see it, the 470nF capacitor as shown will provide
an AC path for the high frequency noise of the ground to couple into VCCADC
anyway??

Regards,
Carson Au
[image: Inline image 1]

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Gmane