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vinod ah | 24 May 2013 07:01
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AC DC SPEC FOR POWER PINS

Hi All,
Have a very basic question on AC DC spec provided to power pins of an
ASIC/IO Controller.

I am working on PLL Characterisation and i find that supply voltage for
that PLL is from an Pin which is 1.2V powered. AC spec is +-2% while DC
spec is +-4%.

I assume that AC spec means ripple while DC spec means supply voltage
tolerance (not ripple).

So was wondering how is the AC DC spec derived in the first place?

Regards
Vinod A H

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jackle zheng | 23 May 2013 05:18
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the relationship of tck(avg) and CL in DDR3 spec

hi, member,
I was testing my EP board on DDR3 compliance, my  tck(avg) was smaller than
spec. So, i checked the DDR3 spec, i found tck(avg) is correlated with CL
value. my question is what is the relationship of the two parameters???
any comment is appreciated.

-- 
ÎÒ˼¹ÊÎÒÔÚ

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Loyer, Jeff | 22 May 2013 16:44
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Presentation on bidirectional SET2DIL May 30 8:00AM and 5:00PM PDT

For those who are using SET2DIL (Single Ended TDR to Differential Insertion Loss),
I will be offering a 1 hour on-line presentation (and audio bridge) on a forthcoming improvement to the
technique Thursday, May 30 at 8:00AM and 5:00PM PDT.
In short, we have found that due to the asymmetric nature of soldermask on microstrip traces, SET2DIL
should excite the DUT from both directions and sum all terms for best results.

We haven't studied stripline traces enough to know if they are similarly affected by asymmetric factor(s).

If you would like to attend but haven't yet received an invitation to the presentation, please e-mail me and
I will send you the logistics.

Thank you,
Jeff Loyer

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Balamanikandan K | 22 May 2013 08:38
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DDR2 length matching address and clock

Dear Experts,

This is regarding the trace length matching between DDR2 address and clock
signals.

*As per my understanding, **the CLK should be centered within** **address
eye to measure and match the trace length.  i.e. signals should like as
shown in figure.*

**
*[image: Inline image 1]*
**

**

I am using Hyperlynx tool for simulation.

Address line is connected from a processor to only one DDR2 DRAM(Not DIMM).

I am using a separate PLL clock driver which drives the clock to only one
DRAM.

No transmission lines are used (direct connection between driver and
memory). Terminations are provided.

*Under direct connections and equal load ( only one DRAM) :*

*
*
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Jagadeesh Gownipalli | 21 May 2013 22:49
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Employment opportunity at Qualcomm for High-Speed Digital Hardware Characterization Engineer

We have immediate openings in our High-Speed SERDES design
validation/Characterization team. We are looking for people with 3-10 years
experience in High Speed SERDES validation/characterization, signal
integrity, PCB design
Below is the description of the Job . If you are intrested please apply at
the link High-Speed Digital Hardware Test
Engineer<http://jobs.qualcomm.com/public/jobDetails.xhtml?requisitionId=1886271>

  Posting Title

High-Speed Digital Hardware Characterization Engineer

  Job Function

As part of the HSWP (High-Speed Wired Peripheral) organization within QCT,
you will be responsible for bench characterization of Digital High-Speed
Physical Layer SERDES (USB, SATA, PCIe,SGMII/QSGMII, MIPI PHY ,
HDMI,LVDS,eDP). Our goal/mission is to ensure that our products are
manufacturable, and exceed the performance expectations of our global
customers.

  Skills/Experience

Candidate must be proficient in test/characterization of High-Speed SERDES
(USB, SATA, PCIe,SGMII/QSGMII, MIPI PHY , HDMI, LVDS,eDP) on custom bench
test platforms. Position requires a working knowledge in the areas of board
design, transmission line theory, High-Speed signal integrity,
de-embedding, and port extension. Hands on knowledge of oscilloscopes,
network / spectrum analyzers, signal generators, and logic analyzers is a
must; experience with Agilent test equipment a plus. Software programming
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Jan Vercammen | 21 May 2013 10:37

mlcc capacitors with silver-palladium termination

Hi,
can anyone point me to a vendor who can supply 0201 size capacitors with
a 6.3V rating (capacitance values 47nF, 68nF, 100nF and 1uf (or 470nf)
but with a silver-palladium termination for conductive epoxy assembly

I have checked DigiKey, Farnell and several large manufacturers of
passive components  but without success

Kind Regards,

Jan Vercammen | Agfa HealthCare
Hardware/RF/EMC/Analog Designer | HE/Architecture & Design Mortsel
T  +32 3444 6233 | F  +32 3 444 6268

Agfa HealthCare NV, Septestraat 27, 2640 Mortsel, Belgium
http://www.agfahealthcare.com
http://blog.agfahealthcare.com
R.O.: Septestraat 27, B-2640 Mortsel, Belgium | RLE Antwerp | VAT BE 
0403.003.524 | IBAN Operational Account BE81363012356224 | IBAN Customer 
Account BE20375104592856 | ING Belgium NV, B-1000 Brussels
Click on link to read important disclaimer: 
http://www.agfahealthcare.com/maildisclaimer 

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piyush bhatt | 18 May 2013 12:46
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Causality Condition -why real and imaginary part of a Frequency response of causal system need to be even and odd respectively

Hi All
An LTI system is causal if and only if h(t)=0 for t<0.

As derivation goes h(t)=h(t)sgn(t).Taking Freq transform both side and
doing some manipulations.We get to point that H(jw) = Hilbert transform of
itself.

Then they say we can divide H(jw) into real and imaginary part.And real
part will be even function and imaginary part will be odd function.

Can you tell me why real part will be even function and imaginary part will
be odd function?

regards
Piyush

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sunil bharadwaz | 18 May 2013 11:45
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POE Circuitry

Hi Friends ,
I was going through some of the POE ( Power over Ethernet ) circuits available .
Design spec is 48V to 5V or 48V to 3.3V  <at>  2.5 to 3 Amps .

I will be helpful if some one can share the info or point me to the 

right links .Are there any simulation models available ?

Thanks in Advance !!

Regards
Sunil

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Jason Miller | 17 May 2013 18:49
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Employment Opportunity with Oracle (Burlington, MA)

We have an opening within the Oracle SPARC Processor Group for a signal 
integrity engineer with 3-7 years of relevant industry experience in 
packaging and board design/analysis. The job location is Burlington, MA. 
Please find the job description and requirements below. To apply for 
this position, please use the link below.

Please email me directly at jason.miller@... with any questions.

------------------------------------------------------------------------------------------------------------------------------------
Description
Our organization is looking for a highly motivated, dedicated team 
member to perform signal integrity modeling, design and characterization 
of server hardware including packages and PCBs.

Signal Integrity engineers participate in all phases of the system 
life-cycle including:
-         Initial concept/architecture
-         Simulation/correlation of high speed passive channels
-         Creation of design rules, driving physical layout and review
-         Bring-up and validation of systems

Job Requirements
- Duties and tasks are varied and complex needing independent judgment
- May have project lead role and or supervise junior engineers
- Ideal candidate will have M.S. or Ph.D in Electrical Engineering or 
Computer Science
- 3-7 years relevant experience in signal integrity
- Experience with printed circuit board design and/or packages
- Background in high-frequency design techniques
- Experience analyzing and optimizing  passive channels in both time and
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Dmitriev-Zdorov, Vladimir | 16 May 2013 21:52
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Re: enforcing passivity on s-parameters

Amit,

> The question I have is : Can we trust the results we get after enforcing passivity on s-parameter or
enforcing passivity spoils the s-parameter?

Many responses on you original question are valuable. Still, it is difficult to give yes or no answer for all
cases. You need to consider several things:

1. Large or small passivity violations?
This can be found as having negative eigenvalues in the matrix (E-SS*), with identity 'E' and Hermitian
conjugate S*. If they are small, e.g. 1e-3 or less, non-passivity correction won't not change the data
much, but also with high probability you will not experience instability with this model.
If passivity violations are large, you have no choice as to fix that.

2. Can we us the model with large passivity violations?
Assuming we fix non-passivity, what's then? Look where exactly non-passivity is located. Is this e.g.
near to base frequency of the channel you need to simulate, or somewhere at very low or high frequency,
compared to what's important to you. If the first, you would better not use your model because you should
rely right on the data which cannot be trusted. In the second case, you may still use your model with some care.

3. Methods used to fix passivity
There are many ways of fixing non-passivity, good and bad. Scott mentioned adding absorbing models, which
at least guarantee that the corrected model does not get causality issues (if it did not before the fix).
Beware of methods making local corrections to sampled S-parameter data, like trimming out the portion
that shows violations without modifying the neighbor points. Such correction is equivalent to
multiplication of your dependence on highly non-causal function. The problem with acquired
non-causality is inability to accurately perform time domain simulation, since IFFT of non-causal
function contains portions of the impulse response at negative times, which cannot be used.
Non-causality by itself (even for passive model) may cause considerable inaccuracies in time domain
analysis, including both deficiency or excess in the response's energy (the latter may cause
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Amit Kumar | 16 May 2013 07:41
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enforcing passivity on s-parameter

Hello Experts,
Many a times I face convergence issues in simulation because of s-parameter.
I then enforce passivity on s-parameter and it does work most of the times.
The question I have is : Can we trust the results we get after enforcing passivity on s-parameter or
enforcing passivity spoils the s-parameter?

Regards
Amit

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