Wensong Wang (王文松 | 20 Aug 02:50 2014

need the mutual inductance and mutual capacitance between two microstrip

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Doug Smith | 20 Aug 01:13 2014

Audio sources, class D digital amps, radiated emissions, and philosophy

 Hi All,
Just finished and posted my August 2014 Technical Tidbit titled:

Radiated Emissions Can be Strongly Affected by Driving Signals, A Problem
forEmissions Testing
(An Example Using a Class D Stereo Audio Amplifier)

Abstract: Radiated emissions from electronic equipment can be a strong
function of how the equipment is operated. In the case of class D audio
amplifiers, the audio signal driving the amplifier can have a large effect
onemissions. Test results and implications are discussed as they relate to
the philosophy of radiated emissions testing.

The link to the article is: http://www.emcesd.com/tt2014/tt081914.htm[1]

The link to the main page: http://www.emcesd.com/[2]
(lots of new stuff there)

Check to make sure your computer does not corrupt the links above. They
should look just as above with no other symbols or numbers added as Windows
sometimes does at the end of the link of the form "[1]".

Doug
-- University of Oxford Tutor Department for Continuing Education Oxford,
Oxfordshire, United Kingdom
-------------------------------------------------------------- ___ _ Doug
Smith \ / ) P.O. Box 60941 ========= Boulder City, NV 89006-0941 _ / \ / \ _
TEL/FAX: 702-570-6108/570-6013 / /\ \ ] / /\ \ Mobile: 408-858-4528 |
q-----() | o | Email: doug@...[3] \ _ / ] \ _ / Web:
http://www.dsmith.org[4]
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Bill Martin | 19 Aug 06:12 2014
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New job opportunity.

To all:
E-System Design is hiring!   

If you or someone you know has interest, please info@...

regards,
Bill

Position specifics are:

www.e-systemdesign.com

Sr. Software Development Engineer

Job Location :
Silicon Valley 
San Jose, CA 95119
United States

Employment term : Full Time 
Travel : Moderate 0% to 25% 
Job level : Min Level: 5 yrs+ 
Work Authorization : ·  Authorized to work in USA 

JOB RESPONSIBILITIES

The Senior Software Development Engineer will work with a very knowledgeable and high profile
development team and will focus on the development of the next generation EDA tools for high performance,
2.5D and 3D systems.  The candidate will also be responsible for interaction with industry leading
semiconductor and system companies on the application of these tools for design and analysis, and be able
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Anto Davis | 17 Aug 15:10 2014
Ajay Dhingra | 16 Aug 15:32 2014
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Drive strength to Load conversion

Hi All
What's the standard way to convert drive strength in mA to a equivalent
Capacitive load. For example if i want to convert 8mA to equivalent pF
load, what's the most reasonable calculation.

Apparently considering full voltage swing in C(dv/dt) equation gives
pessimistic results.
what's the typical dt should be considered.

Thanks
-- 
AJAY DHINGRA
Bangalore, India
9741414027
It is Attitude,Not Aptitude, that determines your Altitude.

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fengling@...


Greetings SI

http://taigamewap.net/yourself.php?upbgkuxgnr2567nx

fengling@...

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Brendan Simpson | 16 Aug 02:53 2014
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Resources for understanding RF

Hello all,

I am a recent graduate with a bachelor’s in Electrical engineering. I would like to more thoroughly
understand the principles of RF communication, as right now it seems to be a bit of black magic. If anybody
can suggest some books or online resources that can provide a comprehensive explanation of RF and
associated sciences, that would be wonderful. Thanks in advance.

Brendan------------------------------------------------------------------
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Yuriy Shlepnev | 15 Aug 16:07 2014

fiber weave effect

Hello Everyone,

Some results of our on-going investigation of fiber-weave effect (FWE) were
recently presented at IEEE EMC 2014 symposium (at SIPI section) and the
paper and presentation are now available at
http://www.simberian.com/AppNotes.php - see #2014_04.
One of the interesting outcomes was practically negligible FEW impact on the
tightly coupled traces on spread fiber fabric (voltage coupling coefficient
about 0.2). We have observed it both on strip and micro-strip (one sheet of
dielectric fabric) configurations. 
We did not find any published confirmation of this result. Any comments or
thoughts?

Best regards,
Yuriy

Yuriy Shlepnev, Ph.D.
President, Simberian Inc.
3030 S Torrey Pines Dr. Las Vegas, NV 89146, USA
Office +1-702-876-2882; Fax +1-702-482-7903
Cell +1-206-409-2368; Virtual +1-408-627-7706
Skype: shlepnev

www.simberian.com 
Simbeor - Accurate, Fast, Easy and Affordable Electromagnetic Signal
Integrity Software
2010 and 2011 DesignVision Award Winner

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pietro | 13 Aug 12:12 2014
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about connector models and backplane

Hello experts.
I need to simulate some PCBs (space application) mounting high 
reliability connectors and for none of them any simulation model exist 
(I checked with the manufacturers C&K and Hypertac). I do not have any 
physical component either instruments to extract s-params by measurements.

Signal frequencies are not critical in terms of speed (whilst signal 
fronts are): any suggestion ?  Modelling each pin as a RLC matching 
signal net nominal impedance would work, at least as first approximation 
? How would you take some margin using the before mentioned approach ?

Another question on backplanes.

Suppose you have several power supply on same layer and those are of 
course connecting several connectors, how would you suggest routing them 
? With copper areas, with traces having enough width and thickness to 
carry the required current, other ?

Thanks

   Pietro

--

-- 
Pietro Vergine
President

CID/CID+ certified

Leading Edge

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Sukumar | 4 Aug 18:58 2014

Reg: Balun return loss

 Hi Experts,
I have downloaded two Balun S parameter models(.s3p) from manufacturer
website. 

Port definitions are shown below,

Balun 1
Port 1: unbalanced input(50 ohm)
Port 2 and port 3: balanced output (50 ohm)

Balun 2
Port 1: unbalanced input(50 ohm)
Port 2 and port 3: balanced output (100 ohm)

How to find insertion and return loss for these 3 port models?

Thanks,
Sukumar

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eric silist | 1 Aug 21:49 2014
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source of DDR 4 timing recommendations

Can anyone help me understand the source of the pcb routing recommendations
I see for DDR4.  For instance DQ to DQS timing for a byte lane?    I see
some papers quoting 90ps or 50mil, but I don't know where those numbers
come from.
At a basic level I understand that DQS is the clock for the data byte on
DQ,  And that the total timing budget must be spread across chip, package,
board, and dram.   If I look at say DDR4-2800 that's a clock of 1.4Ghz with
a period of 714ps.   So at double data rate I figure each byte is 357ps
wide.  Then that should mean I have +/- 178ps of total margin that the DQS
can move from it's ideal position of being in the center of the.  I think
:)   Maybe that's where the 90ps for the board and 90ps for chip come from.

Anyway I'm just having trouble finding a good explanation to help me
understand how all that timing margin is calculated for each piece in the
chain.

I did try to look up DQ-DQS timing in the JEDEC standard and it just says
TBD.   I've found several docs that give me an idea of what values to use,
but none so far that explain how they are calculated.   I feel like this is
still an SI related question since I'll use this information to setup
constraints for my simulations but sorry if it's off topic.

Thank you.

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Gmane