How to estimating signal waveforms at inaccessible points in DDR3 or 4?
Robbie Liu <luliu@...
2015-01-23 09:06:24 GMT
You may treat this question as a follow up discussion of recently hot discussion "tips of using TDR probe "
and "Pin vs. Die", so I may thanks to those experts first ,for their wonderful knowledge sharing.
The question will be met by many hardware engineers such that our DDR3/4 chip may be imaging mounted on board
, or the board use HDI so you can't have test point close enough to the end.
Take DDR write as example, If we just have a test point (TP1)10mm away from the DDR3 chip, and you want to
estimate the signal waveform at the DDR3 die (TP2 ), we need to know the S21 from TP1 to TP2, but for most of us
didn't have such capability to access the TP2, so the problem comes.
Certainly you can use 2D or 3D EM tool to get the channel S parameter, but the high accuracy need experience ,
and the package file is difficult to get.
So can we just use one port test from TP1 ,to get the S parameter of this two port network?
We notice two papers recently mentioned this topic , one is by Tomohiro Kinoshita, Shoichi Hara, Eiji
Takahashi ,Panasonic, A technique for estimating signal waveforms at inaccessible points in high speed
digital circuits, 2013 9th International Workshop on Electromagnetic Compatibility of Integrated
Circuits (EMC Compo), December 15-18, Nara. Japan, it use their own Novel Electromagnetic Tool
'MomCACE' to get the ABCD matrix from TP1 to TP2, then estimate the waveform at the channel end.
Another is by Evelyn Mintarno#1, Steven Ji*2 , A Practical Method to Characterize Interconnect in a Fully
Loaded System, and its Application to DDR3 Channel, Proceedings of the 38th European Microwave
Conference, , based on my understand (maybe wrong ), the method is use for characterize the channel
between the CPU and the SO DIMM connector, right? I was wondering if we can push it further , like the PCB
+Package, so that we can use the s parameter to estimate signal waveforms at inaccessible points in high
speed digital circuits, for example , the imaging mounted DDR3 chip on board. The condition at port 2 may
change between ODT 40, ODT 75 and ODT120, or ODT OFF, not sure if it is possible.
What is your opinions ? do you have better solutions?