bala | 22 Jul 11:08 2014
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Pad parasitics

Hi All,

Is there any tool to calculate my PAD+TRACE+Via parasitic capacitance, .I
can calculate RLC in frequency domain using Sigrity tool, however it will
take decoupling capacitor also into account .I need only parasitic
capacitance of my discrete path. I checked with many CAD tool vendor and no
tool support this feature. I can get parasitic of my trace alone from
cadence. But I need combined (trace+pad+via) parasitic capacitance. Please
help

-- 
bala

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How to evaluate ESD immunity of components when designing ESD robust product?

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Garrison, Gene | 21 Jul 23:08 2014
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Intel looking for SI Engineer in Guadalajara, MX

Intel is looking for a Signal Integrity Engineer in Guadalajara to assist in the design of Server boards and
systems.  This opening is for someone with at least two years of experience in the field.
For further details, go to jobs.intel.com and look for requisition #738116, or you can do a direct search
for 738116 at https://intel.taleo.net/careersection/10000/moresearch.ftl.

- GeneG

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edward kowal | 21 Jul 20:28 2014
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"Bit Inversion" (e.g. DDR4) Simulation in HSPICE

Due to the increasing popularity of the idea of "bit inversion" (by which I am referring to a set of schemes
that limit the number of simultaneously toggling IOs via a parity requirement or similar), I have the need
to generate these kind of input vectors in HSPICE.  Normally, for SSO I am just running PRBS's or clock
patterns, with each DQ uncorrelated to the other DQs.  Can someone who has done it get me pointed in the right
direction about how to generate and stimulate the IO banks with "bit inversion" compliant vectors?
Thanks,Ed 		 	   		  
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Eric Bogatin | 21 Jul 17:12 2014

Front Range SI Lecture series now posted for viewing

Hi folks-

Last year, we invited five world experts to present at the Front Range
Signal Integrity Lecture in Longmont, CO.

These were all recorded and are now posted for free viewing at the new Si
Academy. If you missed the live events, visit www.beTheSignal.com and check
out the fourth course we just added, Video Recordings of Presentations and
Webinars. 

You'll see the Front Range SI Lectures and a few other webinars I've done
over the years, available for free viewing. No registration required. 

Check out the review of the SI Academy Bert Simonovich wrote:
http://iconnect007.uberflip.com/i/344372/45 

--eric

*******************************************************
Dr. Eric Bogatin, Dean

 <http://www.bethesignal.com/> Teledyne LeCroy Signal Integrity Academy

 <http://www.bethesignal.com/> www.beTheSignal.com 

Adjunct Prof, ECEE Univ of Coloroado, Boulder

105 S Sunset St, Suite J

Longmont, CO 80501 USA
(Continue reading)

bala | 17 Jul 17:34 2014
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XFI compliance

Hi,
As per the below spec xfi compliance is defined at point 'D'.(refer page 41
and 47).Is it okay if we meet this spec before equalization.Is there any
xfi spec defined at die after EQ.
p://ftp.seagate.com/sff/INF-8077.PDF
Regards
bala

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Yassin, Adnan | 12 Jul 01:13 2014
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Frequency dependent in ADS

Hello,
Is it possible to model the following frequency dependent resistor in ADS (AC simulations)? How?

R = 0.03 + [freq(MHz)/10,000] + [0.15/freq(MHz)]

Thanks,
-Adnan

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EPEPS Admin | 11 Jul 23:12 2014

2014 EPEPS – Deadline extended for paper submission

Dear Members,
The call for papers for the 23rd Conference on Electrical Performance of Electronic Packaging and Systems
submission deadline has been extended to July 21, 2014.  The submission process can be found at
epeps.org<http://epeps.org/> and can also be accessed through the link Call for
Papers<http://epeps.ece.illinois.edu/2014callforpapersepeps.pdf>.  The conference is held
during Oct. 26-29, 2014, in Portland, Oregon. Also there are great opportunities provided for companies
to showcase their products/brands through structured sponsorships/exhibitions, details of which can
be found in the link Sponsorship
Packages<http://epeps.ece.illinois.edu/2014_Sponsorship_Packages.pdf>. We look forward to your
participation in this premier conference on signal integrity, interconnects and electronic packaging.
For more information, please contact EPEPS administrator, Mandy Wisehart via email, epeps-admin@...<mailto:epeps-admin@...>.
Sincerely,
EPEPS Co-Chairs: Dale Becker, IBM, and Jose Schutt-Aine, University of Illinois

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steve ham | 11 Jul 16:58 2014

A measurement question on spectrum analyzer and network analyzer

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bmRlbnQ6LTE4LjAwMDBwdDsgbWFyZ2luLWJvdHRvbToxMC4wMDAwcHQ7IG1hcmdpbi10
b3A6MHB0OyB0ZXh0LWFsaWduOmp1c3RpZnk7IGxpbmUtaGVpZ2h0OjExNCU7IG1zby1s
aXN0OmwwIGxldmVsMSBsZm8xOwoiPjxzcGFuIHN0eWxlPSJsaW5lLWhlaWdodDogMTE0
JTsgdGV4dC1pbmRlbnQ6IC0xOHB0OyBmb250LXNpemU6IDEycHQ7IGZvbnQtZmFtaWx5
OiAnVGltZXMgTmV3IFJvbWFuJzsiPltNZWFzdXJlbWVudCzCoHNwZWN0cnVtXcKgV2hh
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oGJldHdlZW7CoDwvc3Bhbj48L3A+PHAgY2xhc3M9InAxNSIgc3R5bGU9Im1hcmdpbi1s
ZWZ0OjM2LjAwMDBwdDsgdGV4dC1pbmRlbnQ6LTE4LjAwMDBwdDsgbWFyZ2luLWJvdHRv
bToxMC4wMDAwcHQ7IG1hcmdpbi10b3A6MHB0OyB0ZXh0LWFsaWduOmp1c3RpZnk7IGxp
bmUtaGVpZ2h0OjExNCU7IG1zby1saXN0OmwwIGxldmVsMSBsZm8xOwoiPjxzcGFuIHN0
eWxlPSJsaW5lLWhlaWdodDogMTE0JTsgdGV4dC1pbmRlbnQ6IC0xOHB0OyI+dGhlwqBu
ZXR3b3JrwqBhbmFseXplcsKgYW5kwqBzcGVjdHJ1bcKgYW5hbHl6ZXI/wqA8L3NwYW4+
PC9wPjxiciAvPiAqKioqKiogRnJvbSBTSVBJIEV4Y2hhbmdlICoqKioqKjxiciAvPiAo
TGluayk6aHR0cDovLzEyMi4yMjUuMTkuMTA2OjQxMjAyL1F1ZXN0aW9uL0RldGFpbHM/
aWQ9MTAyNTM8YnIgLz4gKEhvbWUgUGFnZSk6aHR0cDovLzEyMi4yMjUuMTkuMTA2OjQx
MjAyL0hvbWUvSW5kZXg= 
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steve ham | 11 Jul 05:02 2014

I am using HFSS TDR and compare with Agilent TDR in measurement of a sliced via, I found usually HFSS has 2 or 3 ohm higher than Agilent, why?

 I am using HFSS TDR and compare with Agilent TDR in measurement o= f a
sliced via, I found usually HFSS has 2 or 3 ohm higher than A= gilent, why? 
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luyi | 11 Jul 03:39 2014

Experts, who have some experience in conductor surface roughness of 3d modeling, is the huray model the only choice provided in Ansys?‏

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Gmane