Boris Bakshan | 20 Dec 19:20 2014
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DDR3 16bit interfaces

Hello all,
I would like to ask your help with the following:
With 16bit DRAM interfaces we have both UDQS and LDQS.
In a write cycle, does a DDR controller write the two 8bit sets
simultaneously?
Should there be a shift between UDQS and LDQS? What is the the timing
relationship between the two?

Many thanks,
Boris.

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Anto Davis | 20 Dec 05:52 2014
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controlled ESR capacitors or series resistors

Hi,
For optimum flat PDNs, the series resistor should be equal to  square root
(L/C).
Out of the two options (1: controlled ESR caps 2: adding series resistors
to capacitors) which is more commonly chosen?
Is there any other option available ?

Thanks,
Anto

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Doug Brooks | 19 Dec 17:34 2014

Thermal properties of old pcbs

I am reviewing an old article (1968) in which it refers to "copper 
conductors an epoxy glass" and "copper conductors on epoxy paper." 
Although I remember 1968 (that's a clue!!) I don't remember epoxy 
paper. I am particularly interested in the thermal properties 
(thermal conductivity) of these materials.
1. Am I safe in assuming "epoxy glass" is similar to todays FR4?
2. What would "epoxy paper" be like?

Thanks to all the old timers here!!

Doug

Check out our resources at  http://www.ultracad.com 

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M.2 connector signal connectivity

Hi All,

I am using M.2 connector in my design with PCI interface.
Whether the Tx to Rx has to be swapped in the connector or it is taken care in the M.2 module.

Please confirm as I am stuck with my testing, where the swapping is done at the connector in my design.

In case if the design I have is wrong is there any option to overcome this?

Thanks for your clarification.

Regards
SLN

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Boris Bakshan | 18 Dec 09:07 2014
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DDR3 - DQ lines in idle state

Hello all,
I'm now deep into study of DDR3 and more specifically covering the
terminations in READ / WRITE cycles.
I was wondering, what happens in IDLE state when no READ or WRITE operation
is activated? I see that either the controller or DRAM sets VREF voltage on
the DQ lines.
Who's driving the line to VREF? is it the ODT of the DRAM or is it the
controller?

Many thanks,
Boris.

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Doug Smith | 16 Dec 22:11 2014

emc labs and calibration labs

Hi Everyone,

I am thinking of writing next month's Technical Tidbit on equipment 
calibration. As with EMC labs, I have experienced significant errors 
from calibration labs. Things like equipment coming back non-functional 
because parts are missing/loose inside (they must not have actually 
checked anything) and other problems. Also, equipment calibration should 
not be readjusted to be centered in the range according to a study at 
Bell Labs which I will cover in that article.

But this week, at http://emcesd.com#upcoming , is a webinar that picks 
up where this month's Technical Tidbit - December 2014
"EMC and Other Test Lab Errors," leaves off ( 
http://www.emcesd.com/tt2014/tt120214.htm ). If you use test labs or 
work at one, this is critical information that does not seem to be well 
enough known.

Failing a system that really was passing is more typical and causes 
consternation on the part of designers, but the opposite, passing a 
product that should have failed, can lead to lawsuits against test labs. 
I have experienced both types of errors adding to a significant fraction 
of the tests I have been witness to.

Doug

--

-- 
University of Oxford Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
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(Continue reading)

vinod ah | 15 Dec 12:04 2014
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[SI-List]: Spread Spectrum Modulation Rate

Hi All,
This query is with respect to Spread spectrum clocking/PLL design.

We see that modulation rate for Spread spectrum clocking will usually be
30KHz-33KHz.

Is there any legacy reason or design constraint or any other reason for
keeping the modulation rate at 33KHz instead of 10KHz or 100KHz etc..

Regards
Vinod A H

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Doug Smith | 15 Dec 00:34 2014

brick power supplies and test lab errors

 Hi All,
Many of you have attended my web presentation on ESD/EFT internally
generatedin system power supplies. In addition, to the small wall plug power
supplies, I have now confirmed that "brick" type supplies used in PCs can
also exhibit these characteristics. Next to try on larger internal power
supplies, likely to see the effect here too. We will see.

When I was at Auspex Systems (1996-2001) we had 8 EMC radiated emissions
tests performed on our equipment (three 1500 lb cabinets full of disk
drives). Of these, 4 tests had significant test errors, two major and two
minor errors! The tests were done at three different labs over time, all
madeat least one error. "Trust but verify." In 2010-2011, I evaluated 8 ESD
guns, all current cal stickers. 2 of the 8 did not produce the correct
output. "Trust but verify." (Any of you know who said that quote? It is
someone from a completely different field from us.) All the bad data I have
ever seen, came from "calibrated" equipment.

So, if you missed my webinar last week titled "How to Avoid EMC Test Lab
Errors and Their Consequences," I am delivering it next Wednesday, Dec. 17th
at 10 a.m. PST. This is for both experienced engineers as well as new
engineers, especially if you are not in the EMC field. It is a "must see" if
you want to meet schedules and cost targets. Test lab error can be very
costly to your company. The webinar will show you what to look for and
checklists to protect yourself. Info at http://emcesd.com/#upcoming[1] .
Errors covered for many different types of test your equipment will be
subjected to. Suggestions for test labs are made as well.

Doug
-- University of Oxford Tutor Department for Continuing Education Oxford,
Oxfordshire, United Kingdom
(Continue reading)

Hermann Ruckerbauer | 12 Dec 17:55 2014
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Re: S-Parameter view for multiDrop bus

Hello Jay,
the solution for ADS is quite simple (but my HSPICE is a bit rusty, so
don't know how it can be implemented there...)

- Starting point is the normal S-Parameter set with 50ohm termination.
- As also Eric proposed the simulation just simulates DRAM port
independently, but do this automated and saves the result in a single
dataset (ADS container file for all simulation results).
- To do so you define a Variable "DRAM" and sweep this one from 1 to 16.
- With an ideal switch you connect only the port of the DRAM of interest
to the bus dependend on the variable "DRAM" (and maybe connect the
others to the corresponding load). ADS allows some "if then else"
constructs to implement such a matrix (I'm using this concept also for
Multi Slot Memory system simulations in order to simulate all DIMM
population possibilities)
- With a sweep simulation from 1 to 16 now  there are running 16
S-Parameter simulations.
- ADS writes all the data into one dataset, so it's easy now to display
all ports indivdually.

Its basically the same propsal as Eric made, but automated ...

The only thing that is not correct:
The 50 ohm port at the driver is OK, but there should be no termination
at the DRAM position, but the terminating port should be at the end of
the bus.
So if you introduce the real termination you get 3 ports and therefore
an attenuation that is not there in real application and you ignore the
reflections from the port that you are looking at ..
But this might be a acceptable error (at least better than looking into
(Continue reading)

Farooq Iqbal | 11 Dec 20:09 2014

EMC Test Tech in Sunnyvale, CA - Long Term!

I am looking for an EMC Test Technician that can sets up and performs EMC tests, coordinates the maintenance
and calibration of EMC test equipment, and works with clients to meet their needs. The successful
candidate will be detail-oriented, enjoys solving problems in a fast-paced environment, and working
with clients to help them solve theirs.

-Working in EMC lab and with lab equipment
-Knowledge of EMC standards such as: EN, ISO and FCC process standards
-Experience with using: Spectrum Analyzers, LISNs, Signal Generators, Amplifiers, various antennas,
current clamps, oscilloscopes / O'scopes, multimeters and other routine test equipment
-EUT - Equipment Under Testing

If you or someone you know maybe interested and qualified, please send resumes to farooq.iqbal@...

This is a Contracted - Long term, 1 yr + + , Located in Sunnyvale, CA

Also for more details on the job:
http://unitek.theresumator.com/apply/cQi1nT/Emc-Test-Technician.html or navigate to the open
positions through our site: www.nts-unitek.com<http://www.nts-unitek.com/>

Thank you in advance,

Farooq Iqbal
Corporate Recruiter
NTS Unitek
5900 Fort Drive, Suite 100
Centreville, VA  20121
farooq.iqbal@...<mailto:farooq.iqbal@...>
www.nts-unitek.com<http://www.nts-unitek.com/>
Office: 703-961-9901 x 130
Fax: 703-961-9936
(Continue reading)

Julian Ferry | 11 Dec 21:04 2014

FW: test

This is a retransmit of my earlier message.  The first one had a bad email address.  Hopefully, this one will
work better.  If it's not clear, the RSVP email address is: meetandgeek (AT) samtec.com
Sorry for any inconvenience!

Greetings SI Listers!

Samtec will host our ninth annual get-together for SI-List readers at the DesignCon 2015 trade show.

When: Wednesday, Jan 28, 2015 from 6:30-8:30 PM

Where: Hyatt Regency Hotel, Santa Clara, CA - (this is the DesignCon 2015 trade show host hotel)

We will provide the meeting room and complementary beer, wine, non-alcoholic beverages, appetizers and
giveaways all at no cost to you.

As always, there's no sales pitch involved, just friendly socializing and networking.  Who knows ... we may
even try some more trivia questions!! :)

We need an accurate head count to control admission a bit due to pesky party crashers, so we really do need to
know in advance if you plan to stop by ... even if only for a few minutes.

If you would like to attend, just do the following:

  * RSVP by sending an email to
meetandgeek@...<mailto:meetandgeek <at> samtec.com>  by
January 16, 2015.

  * Stop by our booth 943 on the exhibit floor to pick up your admission ticket (note that we're in a new location
this year).

(Continue reading)


Gmane