Doug Brooks | 24 Jan 19:19 2015

Heat exchange coefficient

When I went through school (as a EE) I apparently slept through most 
of my thermodynamics class! Finally, after 50 years, I need to know something.

Can someone estimate the thermal exchange coefficient (thermal 
transfer coefficient) for the following structure for me?

FR4 substrate
3 Oz, 6 inch long trace
delta T of 100 degree C
Horizontal in still air.

Even better, can someone estimate the curve for me (i.e., at delta T 
= 20, 40, 60, 80, 100?)

Thanks for any help

Doug Brooks

Check out our resources at  http://www.ultracad.com 

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@... with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@... with 'help' in the Subject field

(Continue reading)

Mirmak, Michael | 24 Jan 02:47 2015
Picon

Agenda, IBIS Summit at DesignCon, Jan. 30, 2015

Please join us for the free IBIS Summit at DesignCon in Santa Clara next week!

Presentation materials will be available on-line after the event.

Many thanks to our co-sponsors, Keysight Technologies and UBM!

-----------------------------------------------------------------------

                     AGENDA - IBIS SUMMIT MEETING

                       Friday, January 30, 2015

                     Santa Clara Convention Center

                        Santa Clara, California

                   Room: Great America Meeting Room 2

                      Second Floor (look for signs)

           Sponsored by Keysight Technologies, UBM (DesignCon)

-----------------------------------------------------------------------

                  (order and times subject to change)

8:00 AM     Refreshments & Sign In

8:30 AM     Official Opening

(Continue reading)

Lee | 23 Jan 19:04 2015
Picon
Picon

Special Book Offer- Volume 1 and Volume 2, both available in print now for a limited time

Content-Type: text/plain;
	charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Subject: Special Book Offer- Volume 1 and Volume 2, both available in =
print now for a limited time.

For a limited time we are offering both Volumes 1 and 2 of =
=E2=80=9CRight the First Time, A Practical Handbook on High Speed PCB =
and System Design=E2=80=9D for $170 plus shipping.

This is special because Volume 1 is no longer available in print, except =
for this one time.  Volume 1 is normally only available on CD.

Perhaps you have fellow workers who would like the print versions of =
these two very popular books or, like me, prefer your technical =
resources in print form.

This special offer represents a savings of more than $30 over purchasing =
these books one at a time.

You can order these books on our web site www.speedingedge.com

Lee Ritchey
Speeding Edge
P.O. Box 2194
Glen Ellen, CA
95442

707-568-3983
(Continue reading)

Aramareddy Sreekanth reddy | 23 Jan 15:07 2015

NTSC/PAL interface issue

Hi,
NTSC/PAL standard recommends 75ohm transmission line.
But i have used 50ohms trace on my board and designed the board.

Topology is shown below:

NTSC/PAL encoder--->20inch cable(50ohm cable)---->onboard 5inches----> NTSC/PAL decoder.

What could be the impact?
Have anybody faced this problem?
Its very urgent for me, could you please reply.

thanks

::DISCLAIMER::
----------------------------------------------------------------------------------------------------------------------------------------------------

The contents of this e-mail and any attachment(s) are confidential and intended for the named
recipient(s) only.
E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted,
lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents
(with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates.
Views or opinions, if any, presented in this email are solely those of the author and may not necessarily
reflect the
views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying,
disclosure, modification,
distribution and / or publication of this message without the prior written consent of authorized
representative of
HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately.
Before opening any email and/or attachments, please check them for viruses and other defects.
(Continue reading)

Aramareddy Sreekanth reddy | 23 Jan 14:57 2015

NTSC/PAL interface

Hi,
NTSC/PAL standard recommends 75ohm transmission line.
But i have used 50ohms trace on my board and designed the board.

Topology is shown below:

NTSC/PAL encoder--->20inch cable(50ohm cable)---->onboard 5inches----> NTSC/PAL decoder.

What could be the impact?
Have anybody faced this problem?
Its very urgent for me, could you please reply.

Thanks & Regards
Sreekanth

::DISCLAIMER::
----------------------------------------------------------------------------------------------------------------------------------------------------

The contents of this e-mail and any attachment(s) are confidential and intended for the named
recipient(s) only.
E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted,
lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents
(with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates.
Views or opinions, if any, presented in this email are solely those of the author and may not necessarily
reflect the
views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying,
disclosure, modification,
distribution and / or publication of this message without the prior written consent of authorized
representative of
HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately.
(Continue reading)

Robbie Liu | 23 Jan 10:06 2015

How to estimating signal waveforms at inaccessible points in DDR3 or 4?

Dear All:

        You may treat this question as a follow up discussion of recently hot discussion "tips of using TDR probe "
and "Pin vs. Die", so I may  thanks to those experts first ,for their wonderful knowledge sharing.

        The question will be met by many hardware engineers such that our DDR3/4 chip may be imaging mounted on board
, or the board use HDI so you can't have test point close enough to the end.

        Take DDR  write as example, If we just have a  test point (TP1)10mm away from the DDR3 chip,  and you want to
estimate the signal waveform at the DDR3 die  (TP2 ), we need to know the S21 from TP1  to TP2, but for most of us 
didn't have such capability to access the TP2, so the problem comes.

        Certainly  you can use 2D or 3D EM tool to get the channel S parameter, but the high accuracy need experience ,
and the package file is difficult to get.

        So can we just use one port test from TP1 ,to get the S parameter of this two port network?

        We notice two papers recently mentioned this topic , one is by  Tomohiro Kinoshita, Shoichi Hara, Eiji
Takahashi ,Panasonic, A technique for estimating signal waveforms at inaccessible points in high speed
digital circuits, 2013 9th International Workshop on Electromagnetic Compatibility of Integrated
Circuits (EMC Compo), December 15-18, Nara. Japan, it use their own Novel Electromagnetic Tool
'MomCACE'  to get the ABCD matrix from TP1 to TP2, then estimate the waveform at the channel end.
       Another is by  Evelyn Mintarno#1, Steven Ji*2 , A Practical Method to Characterize Interconnect in a Fully
Loaded System, and its Application to DDR3 Channel, Proceedings of the 38th European Microwave
Conference, , based on my understand (maybe wrong ), the method is use for characterize the channel
between the CPU and the SO DIMM connector, right?  I was wondering if we can push it further , like the PCB
+Package, so that we can use the s parameter to   estimate signal waveforms at inaccessible points in high
speed digital circuits, for example , the imaging mounted DDR3 chip on board. The condition at port 2 may
change between ODT 40, ODT 75  and ODT120, or ODT OFF, not sure if it is possible.
       What is your opinions ? do you have better solutions?
(Continue reading)

shankar san | 21 Jan 05:56 2015
Picon

IBIS Speed Support - DDR3

Hi Experts,
In DDR3 IBIS File, few vendors provide the supported speed with voltage.

For Example: 1066/1333/1600/1866  <at>  1.5V and 1066/1333/1600  <at>  1.35V

I have an IBIS file from an vendor in which datasheet says it supports 1866
 <at>  1.35V, but IBIS doesn't support 1866  <at>  1.35, it supports only 1866  <at>  1.5V
(These info's are commented in the IBIS file).

Could some one clarify me how can we find the speed and voltage
supportability of an IBIS file (If commented sections are not available).

I am also following up with vendor for this, meanwhile any
thought/suggestions would be of great help.

Thanks in advance.

Regards,
S Sankar

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@... with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@... with 'help' in the Subject field

(Continue reading)

heidi_barnes | 21 Jan 02:49 2015

Free Webcast Jan. 22 - PCB Materials, Simulations, and Measurements for 32 Gb/s

Hello All,

Join veteran signal integrity experts Lee Ritchey of Speeding Edge, Al Neves of Wild River Technologies,
and Heidi Barnes of Keysight Technology this Thursday at 10am Pacific  for a short webcast entitled "PCB
Materials, Simulations, and Measurements for 32 Gb/s".  

Learn how to specify a PCB stack-up and how to call out the materials so that the PCBs are manufactured in such
a manner that they meet the requirements of high speed designs. Then see how to match measurements with
simulations by using as-fabricated material properties and fixture de-embedding/embedding. Next
learn how to design PCB test structures that validate measurement and simulation for a robust design
flow. 

Registration is free at this long link:
http://www.keysight.com/main/eventDetail.jspx?cc=US&lc=eng&ckey=2494563&nid=-11143.0.00&id=2494563

...or use this shortened link in case the long link gets mangled:
http://bit.ly/SItutorials

Date & time: Thursday, January 22  at 10am US Pacific Time / 1pm US Eastern Time

.... and if you are at DesignCon 2015, you can see us live and in-person on Tuesday afternoon in Ballroom A/B
for a deep dive on the same topic:
DesignCon 2015 Tutorial 13-TU2: BREAKING THE 32 GB/S BARRIER: PCB MATERIALS, SIMULATIONS, MEASUREMENTS
http://www.designcon.com/santaclara/scheduler/session/breaking-the-32-gbs-barrier-pcb-materials-simulations-measurements

--Heidi

Heidi Barnes
Applications Engineer for Signal Integrity, Power Integrity, and EMI/EMC tools for High-Speed Digital Design
Keysight EEsof EDA
(Continue reading)

Garrison, Gene | 20 Jan 23:51 2015
Picon

Intel looking for Sr. SI Engineer

My team in Hillsboro, OR, has an opening for a Sr. Engineer to be responsible for electrical interfaces on
Server board and system designs.
For details, go to https://intel.taleo.net/careersection/10000/moresearch.ftl and put in Job Number 751292.

- GeneG

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@... with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@... with 'help' in the Subject field

List forum  is accessible at:
               http://tech.groups.yahoo.com/group/si-list

List archives are viewable at:     
		http://www.freelists.org/archives/si-list

Old (prior to June 6, 2001) list archives are viewable at:
 		http://www.qsl.net/wb6tpu

Doug Smith | 20 Jan 23:35 2015

Design by committee disasters!

 Hi All,
Here are some thoughts of mine on two examples of design-by-committee in the
EMC field which ended, in my opinion, a poor outcome:

First, is the LISN (line impedance stabilization network), used in conducted
emissions testing. I can&#8217;t believe that a design would be included in
standards that can easily source a 1000 Volt transient out of an innocent
looking BNC connector intended for connecting to a spectrum analyzer. But
that is what happens and many people have burnt out the input of their
spectrum analyzer by connecting it to a LISN.

The LISN design should not rely on people realizing the BNC output cannot be
connected to a spectrum analyzer and putting in various protecting circuits
between the spectrum analyzer and LISN.

Just on the surface, it seems the original LISN circuit was a concept
proposal not a real design, or the designer was completely unfamiliar with
the nature of the AC mains the LISN is used with, or both.

Second, is the capacitive clamp used with IEC 61000-4-4, Electrical Fast
Transients. By the way, EFT bursts as well as inductive kick are what causes
the problems above with the LISN.

The problem arises in that the capacitive clamp was poorly understood at the
time it was included in the standard. It is quite directional and sends much
more energy towards the auxiliary equipment than the equipment under test!
Inturns of peak current, the auxiliary equipment gets 30% to 100% more than
the EUT, depending on the nature of how the common mode impedance of the
auxiliary equipment interacts with the capacitive clamp.

(Continue reading)

Doug Smith | 20 Jan 22:46 2015

Feb. 16-18 seminar on design troubleshooting

 Hi All,
Just a reminder about my Boulder City Seminar on February 16-18th. Info at
http://emcesd.com#BoulderCity[1] . This is unique and unlike any technical
course in the field with lots of demonstrations and a unique "MacGyver" 
likeapproach to problem solving in circuits and systems. Topics covered
include:

  * Good lab troubleshooting and data taking technique 
  * Design troubleshooting techniques (analog and digital) 
  * EMC troubleshooting techniques 
  * ESD troubleshooting techniques 
  * Advanced troubleshooting techniques to find future field problems before
they become field problems 
  * Design techniques to avoid above problems in the first place

Good value too as the fee includes travel and living expenses in Nevada
(hotel, food, transportation to/from airport) for an industry typical fee
that does not usually include these expenses.

Feedback from prior people attending has been extremely positive. I design
the complete experience (seminar and environment) to give the best possible
experience (apple pie a-la-mode afternoon refreshment, for example).

Doug
-- University of Oxford Tutor Department for Continuing Education Oxford,
Oxfordshire, United Kingdom
-------------------------------------------------------------- ___ _ Doug
Smith \ / ) P.O. Box 60941 ========= Boulder City, NV 89006-0941 _ / \ / \ _
TEL/FAX: 702-570-6108/570-6013 / /\ \ ] / /\ \ Mobile: 408-858-4528 |
q-----() | o | Email: doug@...[2] \ _ / ] \ _ / Web:
(Continue reading)


Gmane