Longjun Zhou(LUXSHARE-ICT | 26 Nov 14:59 2014

Shielding vias around microstrip

Hi all,
         I’m confused why some microstrip has shielding vias around them and some without
them. It’s well known that adding vias will add cost of the PCB. In the light of the statement that you get
what you pay for. the microstrip with vias must be better than those without vias. Is it right? In addition,
which rules we should follow when we design the microstrip with vias? How to determine the space between
two vias in line, the gap between the vias and signal trace and the appropriate via number?
        
Best regards
Zhou Longjun
Zhou Longjun 周龙军
EE Team / Enterprise Business Group
LUXSHARE-ICT Precision Industry Co., Ltd.
T:+86 769 89089000  Ext 86024  M:+86 13620065253
E:Longjun.zhou@...
A:No. 17 KuiQing Road, QingHuang Industrial Zone, QingXi Town, DongGuan City, GuangDong, China
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Longjun Zhou(LUXSHARE-ICT | 26 Nov 13:37 2014

Shielding vias around microstrip

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Longjun Zhou(LUXSHARE-ICT | 26 Nov 13:11 2014

Shielding vias around microstrip

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vinod ah | 26 Nov 10:48 2014
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[SI-List]: Energy at the quarter-wave stub resonant frequency

Hi All,
I have a very basic query on quarter wave stubs.

In a FR4 board, with typical Tx to Rx connection using PCB trace with stub,
signal left the Tx but did not make it to the Rx due to quarter-wave stub
resonant frequency matching the signal frequency. This is expected.

But i am unable to understand where did the signal energy go?

I understand that there is cancellation due to quarter wave, but i unable
to understand from energy cancellation point of view because Tx has
launched the energy, but Rx is not seeing it.

Regards
Vinod A H

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Hithesh | 26 Nov 06:55 2014
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Calculating rise time from IBIS

Hi Experts,
A basic question on calculating rise time from ISI -

In the IBIS file, the ramp data for a 3.3V buffer  dV/dt_r is 700.2m/190.9p

This is not 10-90% or 20-80% of 3.3V
Do I take it as 700mV rise per 190psec and scale it to either 10-90% or
20-80%?

In that case why not give the values directly.

Regards
-Hthesh

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Doug Smith | 25 Nov 22:52 2014

engineering break before the holidays

 Hi All,
At work this week or bored at home? Need an interesting engineering break?
Try my short web presentation on Wednesday, tomorrow, on a new way nasty ESD
can be generated within a system power supply by low level EFT or ESD
appliedto the system. See http://emcesd.com/#NextWebinar[1] for details.
Thatlow lever electrical fast transients can do this is new, unexpected, and
bad for electronic systems.

Doug
-- 
[IMG]

--- Links ---
   1 http://emcesd.com/#NextWebinar

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Aaditya K | 25 Nov 22:38 2014
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[SI-LIST]Loosely Coupled vs Tightly Coupled

Hello Experts,

I need opinions on instances where Loosely Coupled differential traces are
better than Tightly coupled ones?

Thanks
Aaditya

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eric silist | 25 Nov 17:14 2014
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Group delay in coax

I'm having a discussion with a colleague and I'm trying to understand group
delay in coax.   Is it affected by cable length or is it constant for a
given cable?
Also I think I understand that group delay decreases with increasing
frequency meaning that the higher frequency components of say a step signal
would arrive before the lower ones?   The bandwidth for my application is
pretty low < 100Mhz, but cable lengths will be very long 100s of meters.
As always thanks for the help.

Best Regards,
-Eric

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Bryan Ackerly | 24 Nov 01:08 2014
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Trace simulation

I have a fairly basic question about trace simulation. 
How do you model a trace that is sandwiched between two 3V3 planes but is driven from logic supplied by
another plane (1V8 for example)? 

For simulation is it realistic to treat the 3V3 plane as Ground? Especially if the 3V3 plane is fairly close
to an adjacent ground plane? 

Regards,
Bryan Ackerly.

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Ajay Dhingra | 21 Nov 18:08 2014
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MLCC Derating

Hi All
Regarding MLCC viz X5R/X7R/Y5V
Is there any standard way of calculating ultimate degraded(de-rated) value
of the capacitor. Datasheets define various kind of de-ratings viz, DC
bias, AC Bias, Temperature, Aging, DC Bias aging etc. But it's not
specified if we need to account for all of them to come at final de rated
values. I have observed all the de-ratings are not independent and varies
with others.

Does a capacitor has a saturated value? and some test to find that.

Thanks
--

-- 
AJAY DHINGRA
Bangalore, India
9741414027
It is Attitude,Not Aptitude, that determines your Altitude.

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Jesús Castañé | 21 Nov 11:49 2014
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Calculating Zin for a DSP Clock

Hi Experts,
I'm trying to calculate the Zin for the CLK in the ADSP21469.

As far as I know I can use the next equation (Sorry for the plain text
format)

Zin= srqt [L_pin / (C_pin + C_comp ) ]

I have tried to find this parameters in the IBIS model but  L_pin and C_pin
are defined as N/A

 L1 CLKIN PDXO01DG NA NA NA

You can find the IBIS model in this link.
http://www.analog.com/static/imported-files/ibis_models/ad2146x_cspBGA_ibs_ver.1.3.txt

Why are these parameters defined as N/A? What am I missing?

Thank you so much for your help. I find this list really interesting.

Regards,

Jesús Castañé
uk.linkedin.com/in/jesusalbertocastanemartinez/


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