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杜 彦召 | 2 Sep 2010 03:30
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etch depth control having no etch stop layer

Hi all:

Does anyone know how to control the RIE etch depth given no etch stop layer?

Andrew

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Albert Henning | 2 Sep 2010 18:22
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Re: etch depth control having no etch stop layer

Timed etch:  Process a test wafer; measure the depth; re-adjust the time
for your 'real' wafer.

Al Henning
NanoInk
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Robert MacDonald | 2 Sep 2010 22:26

Wafer bond alignment tolerance

This is regarding bond alignment. I am basically interested in taking 
a poll regarding what people think reasonable bond alignment tolerance 
is. I know my own experience, and have spoken with a few engineers who 
have done bond process development. For myself, I found that I had to 
design my process to tolerate up to 20um of misalignment, and even so, I 
have about 1 out of 10 wafers falling out of spec. I'm wondering what 
others have encountered. One engineer I spoke with told me that they 
specified 25um, but they also had poor quality. I run a bond process on 
a standard commercially available bonder. The process is an anodic bond 
between Si and borofloat wafers both of which are patterned. I use flags 
(shims) to separate the wafers during ramp, and pull them out prior to 
bonding. The wafers are 100mm. I measure the misalignment using a 
shear-image tool, accurate to within .25um. My process can tolerate up 
to 20um of absolute misalignment at either of the alignment marks 
located on a diameter of 90mm. I am looking for others who have done 
serious process development in wafer bonding with alignment who would be 
willing to share what tolerance they were able to hold the process to. 
The reason I ask, and applications engineer has told me that 1um 
misalignment was possible.

Rob MacDonald
Shearwater Scientific

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Brad Cantos | 3 Sep 2010 00:39

Re: etch depth control having no etch stop layer

Just to add to Al's remarks, to make sure this works repeatably you will want to use the same size wafer with
the same etch pattern on the test wafer and the "real" wafer to avoid being thrown off by any loading or other effects.

Brad Cantos
brad.cantos <at> holage.com
http://holage.com

On 2 Sep 2010, at 9:22 AM, Albert Henning wrote:

> Timed etch:  Process a test wafer; measure the depth; re-adjust the time
> for your 'real' wafer.
> 
> Al Henning
> NanoInk
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Edouard Duriau | 3 Sep 2010 12:15
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Re: etch depth control having no etch stop layer

Dear Andrew,

1. Process a full batch of several wafers. Some will be used for development
of your RIE step.

2. RIE step: adjust your process conditions with some of the wafers from
your batch. Keep in mind that you need the depth tolerance since, due to
chamber and plasma geometry, acceleretaing plates geometry... the depth will
be different at the centerand at the edges of your wafers.

3. Proceed with the rest of your process

Keep in mind that if you want your process to be reproducible, all of your
conditions must remain the same. In other words, if you are etching silicon,
don't forget that Si oxidation is time dependant, beware of the
contamination of your tools, etc.

Ed


On Thu, Sep 2, 2010 at 3:30 AM, 杜 彦召 <xshdyzh <at> yahoo.com.cn> wrote:

> Hi all:
>
> Does anyone know how to control the RIE etch depth given no etch stop
> layer?
>
>
> Andrew
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Grimm, Dr. Daniel | 3 Sep 2010 15:28
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Safe RIE substrate holder + Al2O3 by ALD etching

Dear guys,

For my RIE processes, I need new substrate holders (6'' inch wafers)
which are quite safe in the chemical attacking environment. I have two
chambers:

1. Mainly Si etching with fluorine gases
2. Mainly III-V etching with chlorine gases

I was thinking of different possibilities:

A. Silicon wafer
B. Aluminium plate galvanically coated with some safe metal (e.g. gold?)

What and which material do you think is best for the two etch processes?
Any help will be highly appreciated.

Furthermore do you have any recipes to etch 20nm of Al2O3 deposited by
ALD? I have a typical parallel plate reactor.

Thanks in advance
Daniel

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Gareth Jenkins | 3 Sep 2010 16:37
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Re: Temporary adhesive for spin coating

Thanks. It worked well with AZ 5214 (spun at 750rpm - probably around 3um).
I may still try some CrystalBond just to make positioning in the centre
easier but it seems to be good enough for now.

Best regards

Gareth

On 31 August 2010 14:23, James Paul Grant <j.grant <at> elec.gla.ac.uk> wrote:

> Hi Gareth,
>
> Here is a sample process:
>
> 1. Spin your choice of resist onto your carrier substrate. I normally use
> S1828 spun at 3000 rpm for 30 s which gives a thickness of around 3.2
> microns onto a 15 mm by 15 mm substrate. I have found through experience
> that the resist thickness must be greater than 3 microns for the chip to
> stick to the substrate. I have no scienific explanation for this.
>
> 2. Attach chip to substrate
>
> 3. Bake in convection oven at 90oC for 30 mins or on hotplate at 90oC for 5
> mins. To be frank, the bake times and temperatures are not critical.
>
> 4. Proceed with litho of your chip
>
> 5. To remove chip from carrier immerse in hot acetone or photoresist
> stripper and use ultrasonic.
>
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lamine nait | 5 Sep 2010 03:22
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Safe RIE substrate holder + Al2O3 etching

Dear Daniel;

For the safe material I think it is best for your substrate holder and for the silicon etch process to use
ceramic materials like alcatel deep silicon etcher. 

For the best recipe of aluminum Al2o3 etching is to use chlorine gaze specially :  BCl3 with high power.

regards 

naitbouda abdelyaminea
naitbouda <at> cdta,dz
Process Engineer in the Dry etch area
of the Clean Room of the CDTA 
Centre de Developpement des Technologies Avancées
Cite du 20 Aout 1956 Baba Hassen,Alger,Algerie

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Tony Rogers | 7 Sep 2010 13:52
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Re: Wafer bond alignment tolerance

Hello Rob,

In response to your question regarding acceptable alignment tolerance
for wafer bonding. This depends on the tooling that you are using and
the type of bond that you are performing. The type of tooling that you
describe, requiring the withdrawal of flags after alignment, can be
problematic for many types of bond, especially those in which there is a
softening of the interface bond layer (ie adhesive bonding, glass frit
bonding and some eutectic bonding). For these bonds and flag-based
tooling then 20um alignment is a reasonable target. However for the case
of in-situ aligner bonders, there are no flags to remove and better
alignment tolerances can be achieved. Provided that the wafer bow is
within SEMI specifications, the alignment accuracy for the above bond
types using in-situ alignment can be <3um. For direct bonding and
thermocompression bonding then in-situ alignment can produce reliable,
post-bond 1um alignment accuracy. 

Anodic bonding is a different case given that there is a fundamental and
finite TCE difference between the borofloat glass and the silicon which
can result in a run-out of ~80ppm per degree. This can cause a
mis-alignment of ~5um.

Regards

Tony Rogers
AML

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From: mems-talk-bounces+tony=aml.co.uk <at> memsnet.org
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DEBASHIS MAJI | 7 Sep 2010 14:29
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Argon plasma color

Dear All,

I would like to ask why does the color of the argon plasma during sputtering
changes form light purple to bright blue as the deposition power is
increased or the working pressure is increased to about 0.1 m bar? Is the
shift in color towards deep blue, due to formation of increased number of
energy states...? if so  how is it happening with increased power and/or
with increased working pressure..?

Thanks in advance....

Debashis Maji,
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Gmane