Hi,

please post here more details about the problem and your patch.

Vlado

I have installed tinyos-1.x and trying to build a simulation for an example using make micaz sim.
 But nothing seems to work. The following error occurs:

Blink.nc:42: component Main not found
In file included from Blink.nc:42:
In component `BlinkM':
BlinkM.nc:41: too few arguments to interface `Timer'
In file included from Blink.nc:42:
BlinkM.nc:52: syntax error before `StdControl'
In file included from Blink.nc:42:
In component `SingleTimer':
SingleTimer.nc:47: too few arguments to interface `Timer'
SingleTimer.nc:52: component TimerC not found
SingleTimer.nc:54: cannot find `Timer'
SingleTimer.nc:55: no match
In component `Blink':
Blink.nc:43: cannot find `StdControl'
Blink.nc:44: cannot find `StdControl'
Blink.nc:45: cannot find `Timer'
Blink.nc:46: cannot find `Leds'
make: *** [sim-exe] Error 1

Please help me with this. Thanks in advance.

N.Mahendra.

Hi,
In the last of this mail , temporary fixed code exist. It should be located 
in c:\cygwin\opt\tinyos-2.x\tos\chips\msp430\timer\Msp430ClockP.nc
But if you understand problem exactly , you can apply it to any file which is proper location.

If you want to reproduce it, 
1. provide a BaseStation mote and Laboratary Power supply.
   connect power supply and the basestation. increase voltage level from zero to 3.3V very slowly.
2. Then , probe RS-232 bit rate of the Basestation by Oscillosope. you can see the bit rate is 
   incorrect. thus gateway can not read these datas. 

 in the msp430 user guide(SLAU049xxx.pdf), the ch4 Basic clock module has 
fault oscillator problem. but I think oscillator fault problem is different with this.
this is wrong oscillation of PLL which has problem in slow transition power supply.

if there is reset-IC, it can help this problem. But in the telosb clone board does not have
reset-IC. thus I use internal voltage detector function of msp430.

//tinyos latest version. FEB 2, 2009.
//======c:\cygwin\opt\tinyos-2.x\tos\chips\msp430\timer\Msp430ClockP.nc====

module Msp430ClockP <at> safe()
{
  provides interface Init;
  provides interface Msp430ClockInit;
}
implementation
{
 uint8_t gSVSvalue;
 
 
  MSP430REG_NORACE(IE1);
  MSP430REG_NORACE(TACTL);
  MSP430REG_NORACE(TAIV);
  MSP430REG_NORACE(TBCTL);
  MSP430REG_NORACE(TBIV);

  enum
  {
    ACLK_CALIB_PERIOD = 8,
    TARGET_DCO_DELTA = (TARGET_DCO_KHZ / ACLK_KHZ) * ACLK_CALIB_PERIOD,
  };

void MeasureAVCC();
 void MyWait(uint16_t arg1);
 

  command void Msp430ClockInit.defaultSetupDcoCalibrate()
  {
 
    // --- setup ---

    TACTL = TASSEL1 | MC1; // source SMCLK, continuous mode, everything else 0
    TBCTL = TBSSEL0 | MC1;
    BCSCTL1 = XT2OFF | RSEL2;
    BCSCTL2 = 0;
    TBCCTL0 = CM0;
   }
   
  command void Msp430ClockInit.defaultInitClocks()
  {
    // BCSCTL1
    // .XT2OFF = 1; disable the external oscillator for SCLK and MCLK
    // .XTS = 0; set low frequency mode for LXFT1
    // .DIVA = 0; set the divisor on ACLK to 1
    // .RSEL, do not modify
    BCSCTL1 = XT2OFF | (BCSCTL1 & (RSEL2|RSEL1|RSEL0));

    // BCSCTL2
    // .SELM = 0; select DCOCLK as source for MCLK
    // .DIVM = 0; set the divisor of MCLK to 1
    // .SELS = 0; select DCOCLK as source for SCLK
    // .DIVS = 2; set the divisor of SCLK to 4
    // .DCOR = 0; select internal resistor for DCO
    BCSCTL2 = DIVS1;

    // IE1.OFIE = 0; no interrupt for oscillator fault
    CLR_FLAG( IE1, OFIE );
  }

  command void Msp430ClockInit.defaultInitTimerA()
  {
    TAR = 0;

    // TACTL
    // .TACLGRP = 0; each TACL group latched independently
    // .CNTL = 0; 16-bit counter
    // .TASSEL = 2; source SMCLK = DCO/4
    // .ID = 0; input divisor of 1
    // .MC = 0; initially disabled
    // .TACLR = 0; reset timer A
    // .TAIE = 1; enable timer A interrupts
    TACTL = TASSEL1 | TAIE;
  }

  command void Msp430ClockInit.defaultInitTimerB()
  {
    TBR = 0;

    // TBCTL
    // .TBCLGRP = 0; each TBCL group latched independently
    // .CNTL = 0; 16-bit counter
    // .TBSSEL = 1; source ACLK
    // .ID = 0; input divisor of 1
    // .MC = 0; initially disabled
    // .TBCLR = 0; reset timer B
    // .TBIE = 1; enable timer B interrupts
    TBCTL = TBSSEL0 | TBIE;
  }

  default event void Msp430ClockInit.setupDcoCalibrate()
  {
    call Msp430ClockInit.defaultSetupDcoCalibrate();
  }
 
  default event void Msp430ClockInit.initClocks()
  {
    call Msp430ClockInit.defaultInitClocks();
  }

  default event void Msp430ClockInit.initTimerA()
  {
    call Msp430ClockInit.defaultInitTimerA();
  }

  default event void Msp430ClockInit.initTimerB()
  {
    call Msp430ClockInit.defaultInitTimerB();
  }

  void startTimerA()
  {
    // TACTL.MC = 2; continuous mode
    TACTL = MC1 | (TACTL & ~(MC1|MC0));
  }

  void stopTimerA()
  {
    //TACTL.MC = 0; stop timer B
    TACTL = TACTL & ~(MC1|MC0);
  }

  void startTimerB()
  {
    // TBCTL.MC = 2; continuous mode
    TBCTL = MC1 | (TBCTL & ~(MC1|MC0));
  }

  void stopTimerB()
  {
    //TBCTL.MC = 0; stop timer B
    TBCTL = TBCTL & ~(MC1|MC0);
  }

  void set_dco_calib( int calib )
  {
    BCSCTL1 = (BCSCTL1 & ~0x07) | ((calib >> 8) & 0x07);
    DCOCTL = calib & 0xff;
  }

  uint16_t test_calib_busywait_delta( int calib )
  {
    int8_t aclk_count = 2;
    uint16_t dco_prev = 0;
    uint16_t dco_curr = 0;

    set_dco_calib( calib );

    while( aclk_count-- > 0 )
    {
      TBCCR0 = TBR + ACLK_CALIB_PERIOD; // set next interrupt
      TBCCTL0 &= ~CCIFG; // clear pending interrupt
      while( (TBCCTL0 & CCIFG) == 0 ); // busy wait
      dco_prev = dco_curr;
      dco_curr = TAR;
    }

    return dco_curr - dco_prev;
  }

  // busyCalibrateDCO
  // Should take about 9ms if ACLK_CALIB_PERIOD=8.
  // DCOCTL and BCSCTL1 are calibrated when done.
  void busyCalibrateDco()
  {
    // --- variables ---
    int calib;
    int step;

    // --- calibrate ---

    // Binary search for RSEL,DCO,DCOMOD.
    // It's okay that RSEL isn't monotonic.

    for( calib=0,step=0x800; step!=0; step>>=1 )
    {
      // if the step is not past the target, commit it
      if( test_calib_busywait_delta(calib|step) <= TARGET_DCO_DELTA )
        calib |= step;
    }

    // if DCOx is 7 (0x0e0 in calib), then the 5-bit MODx is not useable, set it to 0
    if( (calib & 0x0e0) == 0x0e0 )
      calib &= ~0x01f;

    set_dco_calib( calib );
  }

  command error_t Init.init()
  {
    // Reset timers and clear interrupt vectors
    TACTL = TACLR;
    TAIV = 0;
    TBCTL = TBCLR;
    TBIV = 0;

    
    //Wait until which the VACC will 3.0V and then DCO should oscillation correctly.
    //If the power supply for the sink mote is unstable,
    //the DCO will be setted wrong and UART asynchronous data timing will be corrupted.
    //from MSP430 datasheet.
 #if 1  
    do{
     MeasureAVCC();
     if((gSVSvalue >= 0xB)&&(gSVSvalue <0xF)){//if it larger then 3.05V and smaller then 3.7V
      break;//OK....
     }
    
     if(gSVSvalue==0xF)break;  //it has error , but it must run the others job....!!!!
    
 }while(1);
#endif
 
    atomic
    {
      signal Msp430ClockInit.setupDcoCalibrate();
      busyCalibrateDco();
      signal Msp430ClockInit.initClocks();
      signal Msp430ClockInit.initTimerA();
      signal Msp430ClockInit.initTimerB();
      startTimerA();
      startTimerB();
    }

    return SUCCESS;
  }
 
//=========================
//These are temporary functions.
#define SVSCTL_REG ((unsigned char *)(0x55))
#define SVSOP               0x02
void MyWait(uint16_t arg1)
{
 uint16_t i,k;
 
 for(i=0; i<arg1; i++){

  nop(); //nop in telosb.
 
 }
 
}

void MeasureAVCC(){
 uint8_t i;
 
 *SVSCTL_REG =( 1<<4); //init with 1.9V comparation.
 MyWait(1200);   //off to on delay is 150 us.
 
 for(i=1;i<14;i++){
  *SVSCTL_REG=(i<<4);
  MyWait(96);  //each steps delay is 12us.
  
  if((*SVSCTL_REG) & SVSOP){
   gSVSvalue=i;
   *SVSCTL_REG =0; //off SVS to conserve power
   return;
  }
  
  
 }
 
 *SVSCTL_REG =0; //off SVS to conserve power

 gSVSvalue=15;  //indicate error.
 
}
 
}
 

----- Original Message -----
From: Vlado Handziski <handzisk <at> tkn.tu-berlin.de>
To: 이기섭 <gslee <at> hallym.ac.kr>
Cc: tinyos-help <at> millennium.berkeley.edu
Sent: 2009/02/02 13:15
Subject: Re: [Tinyos-help] Fw: Re: for Tinyos 2.x bugs...

Hi,

please post here more details about the problem and your patch.

Vlado

2009/1/31 이기섭 <gslee <at> hallym.ac.kr>

Dear tinyos-help

Could you receive the fixed file for the problem which is described below 
and update it into the tinyos project?

K.S.Lee

----- Original Message -----
From: Philip Levis <pal <at> cs.stanford.edu>
To: 이기섭 <gslee <at> hallym.ac.kr>
Cc: cssharp <at> eecs.berkeley.edu, Vlado Handziski <handzisk <at> tkn.tu-berlin.de>, Joe Polastre <polastre <at> cs.berkeley.edu>
Sent: 2009/01/31 13:49
Subject: Re: for Tinyos 2.x bugs...


On Jan 30, 2009, at 8:05 PM, Joe Polastre wrote:

> please contact Phil Levis, pal <at> cs.stanford.edu
>
> Best,
> -Joe
>
> On Fri, Jan 30, 2009 at 7:39 PM, 이기섭 <gslee <at> hallym.ac.kr> wrote:
>>
>> Dear Joe Polastre , Cory Sharp and Vlado Handziski,
>>
>> I had developed our system with tinyos-2.x on last year.
>> I found the bug in tinyos-2.0 source code for MSP430 PLL problem
>> at power
>> up.
>>
>> I think the recent version does not fix this problem. If sink mote
>> will be
>> used
>> with unstable DC power supply, it can be operated incorrectly on
>> RS232 bit
>> rate...
>> Thus the gateway which is located upper layer of sink mote can not
>> receive
>> uploading packet.
>> Now, "the unstable DC power supply" is only meaning which rising
>> slop on
>> power-on
>> is low.
>>
>> Could I send a file which was fixed for this problem?
>> in the Tinyos.net site, the bug report menu is not operating now.
>> And the e-mail accounts which is cssharp and handzisk are not
>> response .
>>
>> Yours sincerely,
>> K.S.Lee


K.S.,

Better yet, please email tinyos-help!

Phil

_______________________________________________
Tinyos-help mailing list
Tinyos-help <at> millennium.berkeley.edu
https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help

I'm sorry, our school email server has some problem. this is using gmail.....

Hi,
In the last of this mail , temporary fixed code exist. It should be located 
in c:\cygwin\opt\tinyos-2.x\tos\chips\msp430\timer\Msp430ClockP.nc
But if you understand problem exactly , you can apply it to any file which is proper location.

If you want to reproduce it, 
1. provide a BaseStation mote and Laboratary Power supply.
   connect power supply and the basestation. increase voltage level from zero to 3.3V very slowly.
2. Then , probe RS-232 bit rate of the Basestation by Oscillosope. you can see the bit rate is 
   incorrect. thus gateway can not read these datas. 

 in the msp430 user guide(SLAU049xxx.pdf), the ch4 Basic clock module has 
fault oscillator problem. but I think oscillator fault problem is different with this.
this is wrong oscillation of PLL which has problem in slow transition power supply.

if there is reset-IC, it can help this problem. But in the telosb clone board does not have
reset-IC. thus I use internal voltage detector function of msp430.

//tinyos latest version. FEB 2, 2009.
//======c:\cygwin\opt\tinyos-2.x\tos\chips\msp430\timer\Msp430ClockP.nc====

module Msp430ClockP <at> safe()
{
  provides interface Init;
  provides interface Msp430ClockInit;
}
implementation
{
 uint8_t gSVSvalue;
 
 
  MSP430REG_NORACE(IE1);
  MSP430REG_NORACE(TACTL);
  MSP430REG_NORACE(TAIV);
  MSP430REG_NORACE(TBCTL);
  MSP430REG_NORACE(TBIV);

  enum
  {
    ACLK_CALIB_PERIOD = 8,
    TARGET_DCO_DELTA = (TARGET_DCO_KHZ / ACLK_KHZ) * ACLK_CALIB_PERIOD,
  };

void MeasureAVCC();
 void MyWait(uint16_t arg1);
 

  command void Msp430ClockInit.defaultSetupDcoCalibrate()
  {
 
    // --- setup ---

    TACTL = TASSEL1 | MC1; // source SMCLK, continuous mode, everything else 0
    TBCTL = TBSSEL0 | MC1;
    BCSCTL1 = XT2OFF | RSEL2;
    BCSCTL2 = 0;
    TBCCTL0 = CM0;
   }
   
  command void Msp430ClockInit.defaultInitClocks()
  {
    // BCSCTL1
    // .XT2OFF = 1; disable the external oscillator for SCLK and MCLK
    // .XTS = 0; set low frequency mode for LXFT1
    // .DIVA = 0; set the divisor on ACLK to 1
    // .RSEL, do not modify
    BCSCTL1 = XT2OFF | (BCSCTL1 & (RSEL2|RSEL1|RSEL0));

    // BCSCTL2
    // .SELM = 0; select DCOCLK as source for MCLK
    // .DIVM = 0; set the divisor of MCLK to 1
    // .SELS = 0; select DCOCLK as source for SCLK
    // .DIVS = 2; set the divisor of SCLK to 4
    // .DCOR = 0; select internal resistor for DCO
    BCSCTL2 = DIVS1;

    // IE1.OFIE = 0; no interrupt for oscillator fault
    CLR_FLAG( IE1, OFIE );
  }

  command void Msp430ClockInit.defaultInitTimerA()
  {
    TAR = 0;

    // TACTL
    // .TACLGRP = 0; each TACL group latched independently
    // .CNTL = 0; 16-bit counter
    // .TASSEL = 2; source SMCLK = DCO/4
    // .ID = 0; input divisor of 1
    // .MC = 0; initially disabled
    // .TACLR = 0; reset timer A
    // .TAIE = 1; enable timer A interrupts
    TACTL = TASSEL1 | TAIE;
  }

  command void Msp430ClockInit.defaultInitTimerB()
  {
    TBR = 0;

    // TBCTL
    // .TBCLGRP = 0; each TBCL group latched independently
    // .CNTL = 0; 16-bit counter
    // .TBSSEL = 1; source ACLK
    // .ID = 0; input divisor of 1
    // .MC = 0; initially disabled
    // .TBCLR = 0; reset timer B
    // .TBIE = 1; enable timer B interrupts
    TBCTL = TBSSEL0 | TBIE;
  }

  default event void Msp430ClockInit.setupDcoCalibrate()
  {
    call Msp430ClockInit.defaultSetupDcoCalibrate();
  }
 
  default event void Msp430ClockInit.initClocks()
  {
    call Msp430ClockInit.defaultInitClocks();
  }

  default event void Msp430ClockInit.initTimerA()
  {
    call Msp430ClockInit.defaultInitTimerA();
  }

  default event void Msp430ClockInit.initTimerB()
  {
    call Msp430ClockInit.defaultInitTimerB();
  }

  void startTimerA()
  {
    // TACTL.MC = 2; continuous mode
    TACTL = MC1 | (TACTL & ~(MC1|MC0));
  }

  void stopTimerA()
  {
    //TACTL.MC = 0; stop timer B
    TACTL = TACTL & ~(MC1|MC0);
  }

  void startTimerB()
  {
    // TBCTL.MC = 2; continuous mode
    TBCTL = MC1 | (TBCTL & ~(MC1|MC0));
  }

  void stopTimerB()
  {
    //TBCTL.MC = 0; stop timer B
    TBCTL = TBCTL & ~(MC1|MC0);
  }

  void set_dco_calib( int calib )
  {
    BCSCTL1 = (BCSCTL1 & ~0x07) | ((calib >> 8) & 0x07);
    DCOCTL = calib & 0xff;
  }

  uint16_t test_calib_busywait_delta( int calib )
  {
    int8_t aclk_count = 2;
    uint16_t dco_prev = 0;
    uint16_t dco_curr = 0;

    set_dco_calib( calib );

    while( aclk_count-- > 0 )
    {
      TBCCR0 = TBR + ACLK_CALIB_PERIOD; // set next interrupt
      TBCCTL0 &= ~CCIFG; // clear pending interrupt
      while( (TBCCTL0 & CCIFG) == 0 ); // busy wait
      dco_prev = dco_curr;
      dco_curr = TAR;
    }

    return dco_curr - dco_prev;
  }

  // busyCalibrateDCO
  // Should take about 9ms if ACLK_CALIB_PERIOD=8.
  // DCOCTL and BCSCTL1 are calibrated when done.
  void busyCalibrateDco()
  {
    // --- variables ---
    int calib;
    int step;

    // --- calibrate ---

    // Binary search for RSEL,DCO,DCOMOD.
    // It's okay that RSEL isn't monotonic.

    for( calib=0,step=0x800; step!=0; step>>=1 )
    {
      // if the step is not past the target, commit it
      if( test_calib_busywait_delta(calib|step) <= TARGET_DCO_DELTA )
        calib |= step;
    }

    // if DCOx is 7 (0x0e0 in calib), then the 5-bit MODx is not useable, set it to 0
    if( (calib & 0x0e0) == 0x0e0 )
      calib &= ~0x01f;

    set_dco_calib( calib );
  }

  command error_t Init.init()
  {
    // Reset timers and clear interrupt vectors
    TACTL = TACLR;
    TAIV = 0;
    TBCTL = TBCLR;
    TBIV = 0;

    
    //Wait until which the VACC will 3.0V and then DCO should oscillation correctly.
    //If the power supply for the sink mote is unstable,
    //the DCO will be setted wrong and UART asynchronous data timing will be corrupted.
    //from MSP430 datasheet.
 #if 1  
    do{
     MeasureAVCC();
     if((gSVSvalue >= 0xB)&&(gSVSvalue <0xF)){//if it larger then 3.05V and smaller then 3.7V
      break;//OK....
     }
    
     if(gSVSvalue==0xF)break;  //it has error , but it must run the others job....!!!!
    
 }while(1);
#endif
 
    atomic
    {
      signal Msp430ClockInit.setupDcoCalibrate();
      busyCalibrateDco();
      signal Msp430ClockInit.initClocks();
      signal Msp430ClockInit.initTimerA();
      signal Msp430ClockInit.initTimerB();
      startTimerA();
      startTimerB();
    }

    return SUCCESS;
  }
 
//=========================
//These are temporary functions.
#define SVSCTL_REG ((unsigned char *)(0x55))
#define SVSOP               0x02
void MyWait(uint16_t arg1)
{
 uint16_t i,k;
 
 for(i=0; i<arg1; i++){

  nop(); //nop in telosb.
 
 }
 
}

void MeasureAVCC(){
 uint8_t i;
 
 *SVSCTL_REG =( 1<<4); //init with 1.9V comparation.
 MyWait(1200);   //off to on delay is 150 us.
 
 for(i=1;i<14;i++){
  *SVSCTL_REG=(i<<4);
  MyWait(96);  //each steps delay is 12us.
  
  if((*SVSCTL_REG) & SVSOP){
   gSVSvalue=i;
   *SVSCTL_REG =0; //off SVS to conserve power
   return;
  }
  
  
 }
 
 *SVSCTL_REG =0; //off SVS to conserve power

 gSVSvalue=15;  //indicate error.
 
}
 
}
 

----- Original Message -----
From: Vlado Handziski <handzisk <at> tkn.tu-berlin.de>
To: 이기섭 <gslee <at> hallym.ac.kr>
Cc: tinyos-help <at> millennium.berkeley.edu
Sent: 2009/02/02 13:15
Subject: Re: [Tinyos-help] Fw: Re: for Tinyos 2.x bugs...

Hi,

please post here more details about the problem and your patch.

Vlado

2009/1/31 이기섭 <gslee <at> hallym.ac.kr>

Dear tinyos-help

Could you receive the fixed file for the problem which is described below 
and update it into the tinyos project?

K.S.Lee

----- Original Message -----
From: Philip Levis <pal <at> cs.stanford.edu>
To: 이기섭 <gslee <at> hallym.ac.kr>
Cc: cssharp <at> eecs.berkeley.edu, Vlado Handziski <handzisk <at> tkn.tu-berlin.de>, Joe Polastre <polastre <at> cs.berkeley.edu>
Sent: 2009/01/31 13:49
Subject: Re: for Tinyos 2.x bugs...


On Jan 30, 2009, at 8:05 PM, Joe Polastre wrote:

> please contact Phil Levis, pal <at> cs.stanford.edu
>
> Best,
> -Joe
>
> On Fri, Jan 30, 2009 at 7:39 PM, 이기섭 <gslee <at> hallym.ac.kr> wrote:
>>
>> Dear Joe Polastre , Cory Sharp and Vlado Handziski,
>>
>> I had developed our system with tinyos-2.x on last year.
>> I found the bug in tinyos-2.0 source code for MSP430 PLL problem
>> at power
>> up.
>>
>> I think the recent version does not fix this problem. If sink mote
>> will be
>> used
>> with unstable DC power supply, it can be operated incorrectly on
>> RS232 bit
>> rate...
>> Thus the gateway which is located upper layer of sink mote can not
>> receive
>> uploading packet.
>> Now, "the unstable DC power supply" is only meaning which rising
>> slop on
>> power-on
>> is low.
>>
>> Could I send a file which was fixed for this problem?
>> in the Tinyos.net site, the bug report menu is not operating now.
>> And the e-mail accounts which is cssharp and handzisk are not
>> response .
>>
>> Yours sincerely,
>> K.S.Lee


K.S.,

Better yet, please email tinyos-help!

Phil

_______________________________________________
Tinyos-help mailing list
Tinyos-help <at> millennium.berkeley.edu
https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help