Lynda Algerienne | 24 Oct 14:39 2014
Picon

Saving in the temperature in a file

Hello,

I am using XM1000 sensors and I would like to save the obtained values of the temperature in a file.

I read that I can redirect the values to a file using   >  notation.


I tried several times but I did not succeed.

I will be very grateful if someone can help me.


Best regards,

Lynda
<div><div dir="ltr">Hello,<div><br></div>
<div>I am using XM1000 sensors and I would like to save the obtained values of the temperature in a file.</div>
<div><br></div>
<div>I read that I can redirect the values to a file using &nbsp; &gt; &nbsp;notation.</div>
<div><br></div>
<div><br></div>
<div>I tried several times but I did not succeed.</div>
<div><br></div>
<div>I will be very grateful if someone can help me.</div>
<div><br></div>
<div><br></div>
<div>Best regards,</div>
<div><br></div>
<div>Lynda</div>
</div></div>
Prashan | 24 Oct 05:48 2014
Picon

Re: tinyos help 8

http://lojawebsite.com/jahscn/fqfbonpssfwdn.ijmgcztentthjctu

































Prashan
<div>
<a href="http://lojawebsite.com/jahscn/fqfbonpssfwdn.ijmgcztentthjctu">http://lojawebsite.com/jahscn/fqfbonpssfwdn.ijmgcztentthjctu</a> <br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br> Prashan <br>
</div>
Ugo Maria Colesanti | 22 Oct 18:47 2014
Picon

Re: Change-suggestion for atm128rfa1 RadioDriverLayer to make it safe to use for atmega64/128/256rfr2

I resend the email since replied to the author only the first time.

Ugo

2014-10-19 11:31 GMT+02:00 Ugo Maria Colesanti <colesanti <at> dis.uniroma1.it>:
Hi Andreas,
please find attached the diff file of the rfa1/rfr2 datasheets that I made some months ago, I think that it might be useful. We have developed a platform based on the RFA1 and are planning to upgrade it with the RFR2 by the end of the year more or less. From my analysis, the rfa1 tinyos code, except for the ADC part, is fine for the rfr2 too  if you don't use any additional functionality that the rfr2 provides. I just added two commands to enable the low power features of the radio in rx and that's it. I did not noticed that the RX_OVERRIDE feature was enabled by default.
Hope it helps,

Ugo Colesanti


>>>>>>>>>>>>> ATTACHED FILE

Chapter 1-6: No changes except obvious ones.

Chapter 7: AVR CPU Core
-----------------------
-> [RFR2 - 7.6.4] EIND – Extended Indirect Register - is mentioned in RFR2 (in register summary too) but not in RFA1. However in the branch instructions [RFR2 - 34.2 and RFA1 - 34.2]it is present in both datasheets. Jump over 128kb? it is not mentioned in the remainder of the datasheet.

Chapter 8: AVR Memories
------------------------
-> [RFR2 - 8.1] In-System Reprogrammable Flash Program Memory - "The application section of the Flash memory contains 3 user signature pages. These pages can be used to store data that should never be modified by an application program e.g. ID numbers, calibration data etc. For details see section "User Signature Data" on page 507."

-> [RFR2 - 8.3.1] EEPROM Read Write Access - "The programming time can be reduced if an entire 8 byte EEPROM page is programmed instead of single bytes."

-> [RFR2 - 8.4.4 EECR] – EEPROM Control Register - Bit 5:4 – EEPM1:0 - EEPROM Programming Mode - there is the page buffer load (See previous note)

Chatper 9: Low-Power 2.4 GHz Transceiver
----------------------------------------
-> [RFR2 - 9.3.1.1] Register Access - The note related to register updates when the radio is not in TRX_OFF has disappeared in RFR2 -> problem solved?
The note in RFA1 was: "It is recommended to modify the transceiver registers in the address range 0x141 - 0x14D and 0x155 - 0x17F only, while in TRX_OFF state. In this case, no special procedures are required.
If registers are written while the transceiver is not in TRX_OFF state (e.g. PLL_ON,RX_LISTEN, TX_ACTIVE, ...) a separate update request for the internal temporary registers is needed. Read back of the registers does not necessarily reflect the state of the internal temporary registers. The values returned show merely the previously written content.
The update request can be forced by either these two:
1. Repeat the write to the last written register
or
2. Read and write back register PART_NUM."

-> [RFR2 - 9.3.4] TX Start Interrupt - The txstart is present in RFR2 but not in RFA1. WARNING: this interrupt signal the start of the preamble, not SFD!!!

-> [RFR2 - 9.4.2.5] MAF – Multiple Address Filter is present in RFR2 but not in RFA1. "The address filter was extended to support four PANs." There are Additional register set for Multiple Address Filter. It might be used in extended operating mode. Not in the current driver that only uses basic operating mode.

-> [RFR2 - 9.6.2.4] TX Power Ramping - WARNING: external front end management has changed, there is the PARCR register instead of PHY_TX_PWR register. Additional options to control external PA: "When using en external RF front-end (refer to "RX/TX Indicator" on page 97) it may be required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved by PARCR register in the bits PALTU/PALTD."

-> [RFR2 - 9.6.2.5] TX Spectrum side lobe suppression - Lobe suppression is present in RFR2 but not in RFA1, it's an interesting feature when using a front end.

-> [RFR2 - 9.6.6.5] RF Channel Selection - "Additionally, the PLL supports all frequencies from 2322 MHz to 2527 MHz with 500 kHz frequency spacing. The frequency is selected by CC_BAND (see "CC_CTRL_1 – Channel Control Register 1" on page 135) and CC_NUMBER"

-> [RFR2 - 9.8.9] Receiver Override - "When an incoming received frame is overlayed by a later starting stronger signal, the overlayed signal would surely destroy the received frame. With an enabled RX Override
feature, the receiver breakes the reception and restarts synchronisation to the stronger signal. The IRQs are set like after reception of a wrong FCS.The feature RX Override is enabled if the bit RX_OVERRIDE in register RX_SYN is set.". It's a very interesting feature, however there are some control registers not well documented (see later)

-> [RFR2 - 9.8.10] Reduced Power Consumption Mode (RPC) - "The RPC mode of the ATmega256/128/64RFR2 offers a variety of independent techniques and methods to significantly reduce the power consumption of the radio transceiver. RPC is applicable to selected operating modes and is transparent to other extended features.". This is the main difference w.r.t. RFA1.

-> [RFR2 - 9.8.11] Phase Difference Measurement - is present in RFR2 but not in RFA1 (don't know what is useful for...)

-> [RFR2 - 9.12.7] TRX_CTRL_0 - phase measurements register present in RFR2 but not in RFA1

-> [RFR2 - 9.12.8] TRX_CTRL_1 – Transceiver Control Register 1 - Bit 4 – PLL_TX_FLT - Enable PLL TX Filter is present in RFR2 but not in RFA1 (see lobe suppression)

-> [RFR2 - 9.12.9] PHY_TX_PWR – Transceiver Transmit Power Control Register - Bit 7:6 – PA_BUF_LT1:0 - Power Amplifier Buffer Lead Time (lead time internal PA buffer to control external front-end, relative to internal PA), Bit 5:4 – PA_LT1:0 - Power Amplifier Lead Time (lead time of the internal PA rlative to transmitted frame SHR) are present in RFA1 but not longer in RFR2

-> [RFR2 - 9.12.10] PARCR – Power Amplifier Ramp up/down Control Register - lead time of external PA and frequency inversion. It has replaced the 4 MSB in PHY_TX_PWR used in RFA1.

-> [RFR2 -9.12.15] RX_CTRL – Transceiver Receive Control Register - settings reserved for internal use

-> [RFR2 - 9.12.20] IRQ_MASK1 – Transceiver Interrupt Enable Register 1 - interrupts related to TX_START and additional address filters (0..3)

-> [RFR2 - 9.12.22] IRQ_STATUS1 – Transceiver Interrupt Status Register 1 - see previous comment

-> [RFR2 - 9.12.26] RX_SYN – Transceiver Receiver Sensitivity Control Register - Bit 6 – RX_OVERRIDE - Receiver Override Function - Bit 5 – RXO_CFG1 - RX_OVERRIDE - Bit 4 – RXO_CFG0 - RX_OVERRIDE (not documented)

-> [RFR2 - 9.12.25] FTN_CTRL – Transceiver Filter Tuning Control Register - additional fields but reserved for internal use

-> [RFR2 - 9.12.26] PLL_CF – Transceiver Center Frequency Calibration Control Register - additional fields but reserved for internal use

-> [RFR2 -9.12.30] PLL_DCU – Transceiver Delay Cell Calibration Control Register - additional bits reserved for internal use

-> [RFR2 - 9.12.31] CC_CTRL_0 – Channel Control Register 0 - sets the channel number - see 9.6.6.5 RF channel selection

-> [RFR2 -9.12.32] CC_CTRL_1 – Channel Control Register 1 - sets the band (only updated if CC_CTRL0 is written)  - see 9.6.6.5 RF channel selection

-> [RFR2 - 9.12.33] TRX_RPC – Transceiver Reduced Power Consumption Control - see 9.8.10 Reduced Power Consumption Mode (RPC)

-> [RFR2 - from 9.12.54 MAFCR0 – Multiple Address Filter Configuration Register 0 to 9.12.71 MAFSA3L] – Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) - additional register for address filtering (0..3)

-> [RFR2 - 9.12.72 TST_CTRL_DIGI] – Transceiver Digital Test Control Register - additional bits but for internal use only

-> [RFR2 - 9.12.74 TST_AGC] – Transceiver Automatic Gain Control and Test Register - automatic gain control settings (don't know the effects of these settings...)

-> [RFR2 - 9.12.75 TST_SDM] – Transceiver Sigma-Delta Modulator Control and Test Register - sigma delta modulator settings (don't know the effects of these settings...)

Chapter 10: MAC Symbol Counter
------------------------------
-> [RFR2 - 10.11.1] Symbol Counter Compare Source Register (SCCSR) exists in rfr2 but not in RFA1: "The Register describes the source timestamp register used for the relative compare
mode. The time stamp source can be selected separately for each compare unit. Possible sources for the relative compare are the Transmit Timestamp, the Receive Timestamp or the Beacon Timestamp (default)"
-> [RFR2 - 10.11.10-13] Symbol Counter Transmit Frame Timestamp Register (SCTSTRxx) exists in rfr2 but not in rfa1: "The Transmit Frame Timestamp Register is updated one symbol before the beginning of the frame transmission (preamble transmission). To allign the Transmit Frame Timestamp with a Received Frame Timestamp (SFD Timestamp),a fixed offset of 11 symbols (1 Symbol Startup + 8 Symbols Preamble + 2 Symbols SFD) need to be added to the Transmit Timestamp."

-> [RFR2 - 10.11.14-17] Symbol Counter Received Frame Timestamp Register (SCRSTRxx) exists in rfr2 but not in rfa1: "The Received Frame Timestamp Register is updated at the end of the frame reception with the contents of the Frame Timestamp Register (SFD timestamp) if the received frame was valid (FCS ok). If the transceiver auto modes are enabled and address filtering is active, the Received Frame Timestamp is only updated, if there was an address match also."

-> [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 5 – SCBTSM - Symbol Counter Beacon Timestamp Mask Register exists in rfr2 but not in rfa1: "This bit must be set to disable automatic beacon timestamping. All other timestamps as well as manual beacon timestamping is not effected by this setting."

-> [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 4:2 – SCCKDIV2:0 - Clock divider for synchronous clock source (16MHz Transceiver Clock) exists in rfr2 but not in rfa1: "The 3 Bit value controls the symbol counter clock prescaler. The input clock to the prescaler is the 16MHz transceiver clock. The different prescaler values are defined in the table below. The default prescaler setting is 62.5kHz. If the transceiver clock is selected, the counter continues on the RTC time base during sleep mode, regardless of the SCCKDIV setting."

-> [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 1 – SCEECLK - Enable External Clock Source on PG2 exists on rfr2 but not on rfa1: "If this bit is set, a asynchronous clock provided on PG2 can be used to run the symbol counter. SCEECLK overrieds SCCKSEL and forces the selection of the external clock source. The clock source on PG2 can have a maximum frequency of 1/4 of the controller clock speed. If selected, the clock on PG2 is used during sleep mode also."


Chapter 11: System Clock and Clock Options
------------------------------------------
no changes

Chapter 12: Power Management and Sleep Modes
---------------------------------------------
-> [RFR2 - 12.6.5] Transceiver Pin Register (TRXPR): Bit 3 – ATBE - Analog Test-bus Enable is present in rfr2 but not in rfa1: "The analog test-bus can be enabled by setting this bit to one. The test-bus can only be activated in the test-mode. Internal analog signals are then available at the TSTOP,TSTON, TSIP and TSTIN pins"

-> [RFR2 - 12.6.5] Transceiver Pin Register (TRXPR): Bit 2 – TRXTST - Transceiver Test-mode Enable is present in rfr2 but not in rfa1: "The TRXTST bit enables the test-functionality of the transceiver. In addition the general device test-mode must be enabled by applying the appropriate test-signature."

-> [RFR2 - 12.6.6] Data Retention Configuration Register #0 (DRTRAM0) – Bit 3:2 – DRTMP1:0 - Positive Data Retention Voltage Setting // Bit 1:0 – DRTMN1:0 - Negative Data Retention Voltage Setting
-> [RFR2 - 12.6.7] Data Retention Configuration Register #1 (DRTRAM1) - idem
-> [RFR2 - 12.6.8] Data Retention Configuration Register #2 (DRTRAM2) - idem + Bit 7 – DISPC - Disable Power-chain of SRAM 2
-> [RFR2 - 12.6.9] Data Retention Configuration Register #3 (DRTRAM3) - idem 

Chapter 13: System Control and Reset
------------------------------------
no changes


Chapter 14: I/O-Ports
---------------------
no changes

Chapter 15: Interrupts
----------------------
Interrupt vector table -> there are TX_START and ADDRESS matching interrupts at the end of the table on the rfr2 that are missing from rfa1.
Interrupt addresses changes accordingly based on the presence of boot section. The new interrupts are at the end.

Chapter 16: External Interrupts
-----------
no changes

Chapter 17: 8-bit Timer/Counter0 with PWM
-----------------------------------------
no changes

Chapter 18: 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)
----------------------------------------------------------------
no changes

Chapter 19: Timer/Counter 0, 1, 3, 4, and 5 Prescaler
-----------------------------------------------------
no changes

Chapter 20: Output Compare Modulator (OCM1C0A)
----------------------------------------------
no changes

Chapter 21: 8-bit Timer/Counter2 with PWM and Asynchronous Operation
--------------------------------------------------------------------
no changes

Chapter 22: SPI- Serial Peripheral Interface
--------------------------------------------
no changes

Chapter 23: USART
-----------------
no changes

Chapter 24: USART in SPI Mode
-----------------------------
no changes

Chapter 25: 2-wire Serial Interface
-----------------------------------
no changes

Chapter 26: AC – Analog Comparator
----------------------------------
no changes

Chapter 27: ADC – Analog to Digital Converter
---------------------------------------------
Too many changes in this chapter, analyze it later.

Chapter 28: JTAG Interface and On-chip Debug System
---------------------------------------------------
no changes

Chapter 29: IEEE 1149.1 (JTAG) Boundary-scan
--------------------------------------------
no changes

Chapter 30: Boot Loader Support – Read-While-Write Self-Programming
--------------------------------------------------------------------
[RFR2 - 30.6.14] Boot Loader Parameters for 64 kByte of Flash Memory -> is present in rfr2 but not in rfa1
[RFR2 - 30.6.16] Boot Loader Parameters for 256 kByte of Flash Memory -> is present in rfr2 but not in rfa1

Chapter 31: Memory Programming
-------------------------------
[RFR2 - 31.4] User Signature Data -> present in rfr2 but not in rfa1
[RFR2 - 31.6] Page Size -> different values for different sizes in rfr2
[RFR2 - 31.8.15] Chip Erase of EEPROM only -> is present in rfr2 but not in rfa1
[RFR2 - 31.8.16] Erase EEPROM Page -> is present in rfr2 but not in rfa1
[RFR2 - 31.8.17] Writing User Signature Data -> is present in rfr2 but not in rfa1
[RFR2 - 31.8.18] Erasing User Signature Data -> is present in rfr2 but not in rfa1
[RFR2 - 31.8.19] Reading User Signature Data -> is present in rfr2 but not in rfa1
[RFR2 - Table 31-19] Chip Erase EEPROM only/Enter EEPROM Erase/Enter User Signature Page Write/Enter User Signature Page Erase/ instruction present in rfr2 but not in rfa1
[RFR2 - 31.10.25] Performing Chip Erase of only the EEPROM -> is present in rfr2 but not in rfa1
[RFR2 - 31.10.26] Erasing an EEPROM Page -> is present in rfr2 but not in rfa1
[RFR2 - 31.10.27] Programming User Signature Data -> is present in rfr2 but not in rfa1
[RFR2 - 31.10.28] Erasing User Signature Data -> is present in rfr2 but not in rfa1
[RFR2 - 31.10.29] Reading User Signature Data -> is present in rfr2 but not in rfa1

Chapter 32: Application Circuits
--------------------------------
ignored

Chapter 33: Register Summary
----------------------------
need to have a look to the register summary

Chapter 34: Instruction Set Summary
-----------------------------------
no changes (instruction set is identical)

>>>>>>>>>>>>>>>>>> END ATTACHED FILE

 
2014-10-17 16:39 GMT+02:00 Andreas Weigel <andreas.weigel <at> tuhh.de>:
Hi everyone,

Suggestion: Add the following line somewhere to the init code:
RX_SYN &= ~(1 << 6);

Rationale:
I just had some "fun time" with a self-made C-port (not very beautiful,
but it does its job) of the atm128rfa1 RFA1DriverLayerP (and the
corresponding rfxlink layers).

Letting four ATmega256rfr2-based nodes send out broadcast packets as
fast as possible (having the whole stack in place, including backoffs
etc.), lead to RADIO_ASSERT(!radioIrq) being triggered in the RX_END
ISR. After some happy debugging and thinking (is my protocolstack
actually to slow in processing the tasklet code stuff?) I was sure that
this should not be possible.

I then stumbled across a new and greatly-documented feature of the rfr2
named RX_OVERRIDE, which is enabled on this chip by default (who does
such things?). This seems to lead to RX_END interrupts which are
triggered very soon (< 20 us) after the corresponding RX_START. In rare
circumstances when RX_START was interrupted again by the RadioAlarm
interrupt (and correspondingly, the TosRandomCollisionLayer
RadioAlarm.fired() code was executed), service_radio got deferred long
enough to allow for the RX_END to occur and the RADIO_ASSERT to happen.
Deactivating RX_OVERRIDE solved the problem.

I do not know (as I could not try out or know how fast the actual TinyOS
stack handles the code), if this problem would really affect an
ATmega256rfr2 running TinyOS (which I did not), but I think it at least
very possible. Considering this, I suggest to add the code shown above
to the init function of the driver to make the current radio driver safe
for all rfr2-type chips (also in case someone "ports" the code to rfr2
and is -- like me -- unaware of this new feature), so that other people
are spared the pain I just lived through during the last few days

Regards,
Andreas
_______________________________________________
Tinyos-help mailing list
Tinyos-help <at> millennium.berkeley.edu
https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help


<div><div dir="ltr">I resend the email since replied to the author only the first time.<div><br></div>
<div>Ugo<br><div class="gmail_extra">
<br><div class="gmail_quote">2014-10-19 11:31 GMT+02:00 Ugo Maria Colesanti <span dir="ltr">&lt;<a href="mailto:colesanti <at> dis.uniroma1.it" target="_blank">colesanti <at> dis.uniroma1.it</a>&gt;</span>:<br><blockquote class="gmail_quote">
<div dir="ltr">Hi Andreas,<div>please find attached the diff file of the rfa1/rfr2 datasheets that I made some months ago, I think that it might be useful. We have developed a platform based on the RFA1 and are planning to upgrade it with the RFR2 by the end of the year more or less. From my analysis, the rfa1 tinyos code, except for the ADC part, is fine for the rfr2 too &nbsp;if you don't use any additional functionality that the rfr2 provides. I just added two commands to enable the low power features of the radio in rx and that's it. I did not noticed that the RX_OVERRIDE feature was enabled by default.</div>
<div>Hope it helps,</div>
<div><br></div>
<div>Ugo Colesanti</div>
</div>
<div class=""><div class="h5"><div class="gmail_extra"><br></div></div></div>
</blockquote>
<div>
<div><br></div>
<div>&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt; ATTACHED FILE</div>
<div><br></div>
<div>Chapter 1-6: No changes except obvious ones.</div>
<div><br></div>
<div>Chapter 7: AVR CPU Core</div>
<div>-----------------------</div>
<div>-&gt; [RFR2 - 7.6.4] EIND &ndash; Extended Indirect Register - is mentioned in RFR2 (in register summary too) but not in RFA1. However in the branch instructions [RFR2 - 34.2 and RFA1 - 34.2]it is present in both datasheets. Jump over 128kb? it is not mentioned in the remainder of the datasheet.</div>
<div><br></div>
<div>Chapter 8: AVR Memories</div>
<div>------------------------</div>
<div>-&gt; [RFR2 - 8.1] In-System Reprogrammable Flash Program Memory - "The application section of the Flash memory contains 3 user signature pages. These pages can be used to store data that should never be modified by an application program e.g. ID numbers, calibration data etc. For details see section "User Signature Data" on page 507."</div>
<div><br></div>
<div>-&gt; [RFR2 - 8.3.1] EEPROM Read Write Access - "The programming time can be reduced if an entire 8 byte EEPROM page is programmed instead of single bytes."</div>
<div><br></div>
<div>-&gt; [RFR2 - 8.4.4 EECR] &ndash; EEPROM Control Register - Bit 5:4 &ndash; EEPM1:0 - EEPROM Programming Mode - there is the page buffer load (See previous note)</div>
<div><br></div>
<div>Chatper 9: Low-Power 2.4 GHz Transceiver</div>
<div>----------------------------------------</div>
<div>-&gt; [RFR2 - 9.3.1.1] Register Access - The note related to register updates when the radio is not in TRX_OFF has disappeared in RFR2 -&gt; problem solved?</div>
<div>The note in RFA1 was: "It is recommended to modify the transceiver registers in the address range 0x141 - 0x14D and 0x155 - 0x17F only, while in TRX_OFF state. In this case, no special procedures are required.</div>
<div>If registers are written while the transceiver is not in TRX_OFF state (e.g. PLL_ON,RX_LISTEN, TX_ACTIVE, ...) a separate update request for the internal temporary registers is needed. Read back of the registers does not necessarily reflect the state of the internal temporary registers. The values returned show merely the previously written content.</div>
<div>The update request can be forced by either these two:</div>
<div>1. Repeat the write to the last written register</div>
<div>or</div>
<div>2. Read and write back register PART_NUM."</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.3.4] TX Start Interrupt - The txstart is present in RFR2 but not in RFA1. WARNING: this interrupt signal the start of the preamble, not SFD!!!</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.4.2.5] MAF &ndash; Multiple Address Filter is present in RFR2 but not in RFA1. "The address filter was extended to support four PANs." There are Additional register set for Multiple Address Filter. It might be used in extended operating mode. Not in the current driver that only uses basic operating mode.</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.6.2.4] TX Power Ramping - WARNING: external front end management has changed, there is the PARCR register instead of PHY_TX_PWR register. Additional options to control external PA: "When using en external RF front-end (refer to "RX/TX Indicator" on page 97) it may be required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved by PARCR register in the bits PALTU/PALTD."</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.6.2.5] TX Spectrum side lobe suppression - Lobe suppression is present in RFR2 but not in RFA1, it's an interesting feature when using a front end.</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.6.6.5] RF Channel Selection - "Additionally, the PLL supports all frequencies from 2322 MHz to 2527 MHz with 500 kHz frequency spacing. The frequency is selected by CC_BAND (see "CC_CTRL_1 &ndash; Channel Control Register 1" on page 135) and CC_NUMBER"</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.8.9] Receiver Override - "When an incoming received frame is overlayed by a later starting stronger signal, the overlayed signal would surely destroy the received frame. With an enabled RX Override</div>
<div>feature, the receiver breakes the reception and restarts synchronisation to the stronger signal. The IRQs are set like after reception of a wrong FCS.The feature RX Override is enabled if the bit RX_OVERRIDE in register RX_SYN is set.". It's a very interesting feature, however there are some control registers not well documented (see later)</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.8.10] Reduced Power Consumption Mode (RPC) - "The RPC mode of the ATmega256/128/64RFR2 offers a variety of independent techniques and methods to significantly reduce the power consumption of the radio transceiver. RPC is applicable to selected operating modes and is transparent to other extended features.". This is the main difference w.r.t. RFA1.</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.8.11] Phase Difference Measurement - is present in RFR2 but not in RFA1 (don't know what is useful for...)</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.7] TRX_CTRL_0 - phase measurements register present in RFR2 but not in RFA1</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.8] TRX_CTRL_1 &ndash; Transceiver Control Register 1 - Bit 4 &ndash; PLL_TX_FLT - Enable PLL TX Filter is present in RFR2 but not in RFA1 (see lobe suppression)</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.9] PHY_TX_PWR &ndash; Transceiver Transmit Power Control Register - Bit 7:6 &ndash; PA_BUF_LT1:0 - Power Amplifier Buffer Lead Time (lead time internal PA buffer to control external front-end, relative to internal PA), Bit 5:4 &ndash; PA_LT1:0 - Power Amplifier Lead Time (lead time of the internal PA rlative to transmitted frame SHR) are present in RFA1 but not longer in RFR2</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.10] PARCR &ndash; Power Amplifier Ramp up/down Control Register - lead time of external PA and frequency inversion. It has replaced the 4 MSB in PHY_TX_PWR used in RFA1.</div>
<div><br></div>
<div>-&gt; [RFR2 -9.12.15] RX_CTRL &ndash; Transceiver Receive Control Register - settings reserved for internal use</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.20] IRQ_MASK1 &ndash; Transceiver Interrupt Enable Register 1 - interrupts related to TX_START and additional address filters (0..3)</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.22] IRQ_STATUS1 &ndash; Transceiver Interrupt Status Register 1 - see previous comment</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.26] RX_SYN &ndash; Transceiver Receiver Sensitivity Control Register - Bit 6 &ndash; RX_OVERRIDE - Receiver Override Function - Bit 5 &ndash; RXO_CFG1 - RX_OVERRIDE - Bit 4 &ndash; RXO_CFG0 - RX_OVERRIDE (not documented)</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.25] FTN_CTRL &ndash; Transceiver Filter Tuning Control Register - additional fields but reserved for internal use</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.26] PLL_CF &ndash; Transceiver Center Frequency Calibration Control Register - additional fields but reserved for internal use</div>
<div><br></div>
<div>-&gt; [RFR2 -9.12.30] PLL_DCU &ndash; Transceiver Delay Cell Calibration Control Register - additional bits reserved for internal use</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.31] CC_CTRL_0 &ndash; Channel Control Register 0 - sets the channel number - see 9.6.6.5 RF channel selection</div>
<div><br></div>
<div>-&gt; [RFR2 -9.12.32] CC_CTRL_1 &ndash; Channel Control Register 1 - sets the band (only updated if CC_CTRL0 is written) &nbsp;- see 9.6.6.5 RF channel selection</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.33] TRX_RPC &ndash; Transceiver Reduced Power Consumption Control - see 9.8.10 Reduced Power Consumption Mode (RPC)</div>
<div><br></div>
<div>-&gt; [RFR2 - from 9.12.54 MAFCR0 &ndash; Multiple Address Filter Configuration Register 0 to 9.12.71 MAFSA3L] &ndash; Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) - additional register for address filtering (0..3)</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.72 TST_CTRL_DIGI] &ndash; Transceiver Digital Test Control Register - additional bits but for internal use only</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.74 TST_AGC] &ndash; Transceiver Automatic Gain Control and Test Register - automatic gain control settings (don't know the effects of these settings...)</div>
<div><br></div>
<div>-&gt; [RFR2 - 9.12.75 TST_SDM] &ndash; Transceiver Sigma-Delta Modulator Control and Test Register - sigma delta modulator settings (don't know the effects of these settings...)</div>
<div><br></div>
<div>Chapter 10: MAC Symbol Counter</div>
<div>------------------------------</div>
<div>-&gt; [RFR2 - 10.11.1] Symbol Counter Compare Source Register (SCCSR) exists in rfr2 but not in RFA1: "The Register describes the source timestamp register used for the relative compare</div>
<div>mode. The time stamp source can be selected separately for each compare unit. Possible sources for the relative compare are the Transmit Timestamp, the Receive Timestamp or the Beacon Timestamp (default)"</div>
<div>-&gt; [RFR2 - 10.11.10-13] Symbol Counter Transmit Frame Timestamp Register (SCTSTRxx) exists in rfr2 but not in rfa1: "The Transmit Frame Timestamp Register is updated one symbol before the beginning of the frame transmission (preamble transmission). To allign the Transmit Frame Timestamp with a Received Frame Timestamp (SFD Timestamp),a fixed offset of 11 symbols (1 Symbol Startup + 8 Symbols Preamble + 2 Symbols SFD) need to be added to the Transmit Timestamp."</div>
<div><br></div>
<div>-&gt; [RFR2 - 10.11.14-17] Symbol Counter Received Frame Timestamp Register (SCRSTRxx) exists in rfr2 but not in rfa1: "The Received Frame Timestamp Register is updated at the end of the frame reception with the contents of the Frame Timestamp Register (SFD timestamp) if the received frame was valid (FCS ok). If the transceiver auto modes are enabled and address filtering is active, the Received Frame Timestamp is only updated, if there was an address match also."</div>
<div><br></div>
<div>-&gt; [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 5 &ndash; SCBTSM - Symbol Counter Beacon Timestamp Mask Register exists in rfr2 but not in rfa1: "This bit must be set to disable automatic beacon timestamping. All other timestamps as well as manual beacon timestamping is not effected by this setting."</div>
<div><br></div>
<div>-&gt; [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 4:2 &ndash; SCCKDIV2:0 - Clock divider for synchronous clock source (16MHz Transceiver Clock) exists in rfr2 but not in rfa1: "The 3 Bit value controls the symbol counter clock prescaler. The input clock to the prescaler is the 16MHz transceiver clock. The different prescaler values are defined in the table below. The default prescaler setting is 62.5kHz. If the transceiver clock is selected, the counter continues on the RTC time base during sleep mode, regardless of the SCCKDIV setting."</div>
<div><br></div>
<div>-&gt; [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 1 &ndash; SCEECLK - Enable External Clock Source on PG2 exists on rfr2 but not on rfa1: "If this bit is set, a asynchronous clock provided on PG2 can be used to run the symbol counter. SCEECLK overrieds SCCKSEL and forces the selection of the external clock source. The clock source on PG2 can have a maximum frequency of 1/4 of the controller clock speed. If selected, the clock on PG2 is used during sleep mode also."</div>
<div><br></div>
<div><br></div>
<div>Chapter 11: System Clock and Clock Options</div>
<div>------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 12: Power Management and Sleep Modes</div>
<div>---------------------------------------------</div>
<div>-&gt; [RFR2 - 12.6.5] Transceiver Pin Register (TRXPR): Bit 3 &ndash; ATBE - Analog Test-bus Enable is present in rfr2 but not in rfa1: "The analog test-bus can be enabled by setting this bit to one. The test-bus can only be activated in the test-mode. Internal analog signals are then available at the TSTOP,TSTON, TSIP and TSTIN pins"</div>
<div><br></div>
<div>-&gt; [RFR2 - 12.6.5] Transceiver Pin Register (TRXPR): Bit 2 &ndash; TRXTST - Transceiver Test-mode Enable is present in rfr2 but not in rfa1: "The TRXTST bit enables the test-functionality of the transceiver. In addition the general device test-mode must be enabled by applying the appropriate test-signature."</div>
<div><br></div>
<div>-&gt; [RFR2 - 12.6.6] Data Retention Configuration Register #0 (DRTRAM0) &ndash; Bit 3:2 &ndash; DRTMP1:0 - Positive Data Retention Voltage Setting // Bit 1:0 &ndash; DRTMN1:0 - Negative Data Retention Voltage Setting</div>
<div>-&gt; [RFR2 - 12.6.7] Data Retention Configuration Register #1 (DRTRAM1) - idem</div>
<div>-&gt; [RFR2 - 12.6.8] Data Retention Configuration Register #2 (DRTRAM2) - idem + Bit 7 &ndash; DISPC - Disable Power-chain of SRAM 2</div>
<div>-&gt; [RFR2 - 12.6.9] Data Retention Configuration Register #3 (DRTRAM3) - idem&nbsp;</div>
<div><br></div>
<div>Chapter 13: System Control and Reset</div>
<div>------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div><br></div>
<div>Chapter 14: I/O-Ports</div>
<div>---------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 15: Interrupts</div>
<div>----------------------</div>
<div>Interrupt vector table -&gt; there are TX_START and ADDRESS matching interrupts at the end of the table on the rfr2 that are missing from rfa1.</div>
<div>Interrupt addresses changes accordingly based on the presence of boot section. The new interrupts are at the end.</div>
<div><br></div>
<div>Chapter 16: External Interrupts</div>
<div>-----------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 17: 8-bit Timer/Counter0 with PWM</div>
<div>-----------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 18: 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)</div>
<div>----------------------------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 19: Timer/Counter 0, 1, 3, 4, and 5 Prescaler</div>
<div>-----------------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 20: Output Compare Modulator (OCM1C0A)</div>
<div>----------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 21: 8-bit Timer/Counter2 with PWM and Asynchronous Operation</div>
<div>--------------------------------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 22: SPI- Serial Peripheral Interface</div>
<div>--------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 23: USART</div>
<div>-----------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 24: USART in SPI Mode</div>
<div>-----------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 25: 2-wire Serial Interface</div>
<div>-----------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 26: AC &ndash; Analog Comparator</div>
<div>----------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 27: ADC &ndash; Analog to Digital Converter</div>
<div>---------------------------------------------</div>
<div>Too many changes in this chapter, analyze it later.</div>
<div><br></div>
<div>Chapter 28: JTAG Interface and On-chip Debug System</div>
<div>---------------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 29: IEEE 1149.1 (JTAG) Boundary-scan</div>
<div>--------------------------------------------</div>
<div>no changes</div>
<div><br></div>
<div>Chapter 30: Boot Loader Support &ndash; Read-While-Write Self-Programming</div>
<div>--------------------------------------------------------------------</div>
<div>[RFR2 - 30.6.14] Boot Loader Parameters for 64 kByte of Flash Memory -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 30.6.16] Boot Loader Parameters for 256 kByte of Flash Memory -&gt; is present in rfr2 but not in rfa1</div>
<div><br></div>
<div>Chapter 31: Memory Programming</div>
<div>-------------------------------</div>
<div>[RFR2 - 31.4] User Signature Data -&gt; present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.6] Page Size -&gt; different values for different sizes in rfr2</div>
<div>[RFR2 - 31.8.15] Chip Erase of EEPROM only -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.8.16] Erase EEPROM Page -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.8.17] Writing User Signature Data -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.8.18] Erasing User Signature Data -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.8.19] Reading User Signature Data -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - Table 31-19] Chip Erase EEPROM only/Enter EEPROM Erase/Enter User Signature Page Write/Enter User Signature Page Erase/ instruction present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.10.25] Performing Chip Erase of only the EEPROM -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.10.26] Erasing an EEPROM Page -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.10.27] Programming User Signature Data -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.10.28] Erasing User Signature Data -&gt; is present in rfr2 but not in rfa1</div>
<div>[RFR2 - 31.10.29] Reading User Signature Data -&gt; is present in rfr2 but not in rfa1</div>
<div><br></div>
<div>Chapter 32: Application Circuits</div>
<div>--------------------------------</div>
<div>ignored</div>
<div><br></div>
<div>Chapter 33: Register Summary</div>
<div>----------------------------</div>
<div>need to have a look to the register summary</div>
<div><br></div>
<div>Chapter 34: Instruction Set Summary</div>
<div>-----------------------------------</div>
<div>no changes (instruction set is identical)</div>
</div>
<div><br></div>
<div>&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt; END ATTACHED FILE</div>
<div><br></div>
<div>&nbsp;</div>
<blockquote class="gmail_quote"><div class=""><div class="h5">
<div class="gmail_extra">
<div class="gmail_quote">2014-10-17 16:39 GMT+02:00 Andreas Weigel <span dir="ltr">&lt;<a href="mailto:andreas.weigel <at> tuhh.de" target="_blank">andreas.weigel <at> tuhh.de</a>&gt;</span>:<br><blockquote class="gmail_quote">Hi everyone,<br><br>
Suggestion: Add the following line somewhere to the init code:<br>
RX_SYN &amp;= ~(1 &lt;&lt; 6);<br><br>
Rationale:<br>
I just had some "fun time" with a self-made C-port (not very beautiful,<br>
but it does its job) of the atm128rfa1 RFA1DriverLayerP (and the<br>
corresponding rfxlink layers).<br><br>
Letting four ATmega256rfr2-based nodes send out broadcast packets as<br>
fast as possible (having the whole stack in place, including backoffs<br>
etc.), lead to RADIO_ASSERT(!radioIrq) being triggered in the RX_END<br>
ISR. After some happy debugging and thinking (is my protocolstack<br>
actually to slow in processing the tasklet code stuff?) I was sure that<br>
this should not be possible.<br><br>
I then stumbled across a new and greatly-documented feature of the rfr2<br>
named RX_OVERRIDE, which is enabled on this chip by default (who does<br>
such things?). This seems to lead to RX_END interrupts which are<br>
triggered very soon (&lt; 20 us) after the corresponding RX_START. In rare<br>
circumstances when RX_START was interrupted again by the RadioAlarm<br>
interrupt (and correspondingly, the TosRandomCollisionLayer<br>
RadioAlarm.fired() code was executed), service_radio got deferred long<br>
enough to allow for the RX_END to occur and the RADIO_ASSERT to happen.<br>
Deactivating RX_OVERRIDE solved the problem.<br><br>
I do not know (as I could not try out or know how fast the actual TinyOS<br>
stack handles the code), if this problem would really affect an<br>
ATmega256rfr2 running TinyOS (which I did not), but I think it at least<br>
very possible. Considering this, I suggest to add the code shown above<br>
to the init function of the driver to make the current radio driver safe<br>
for all rfr2-type chips (also in case someone "ports" the code to rfr2<br>
and is -- like me -- unaware of this new feature), so that other people<br>
are spared the pain I just lived through during the last few days<br><br>
Regards,<br>
Andreas<br>
_______________________________________________<br>
Tinyos-help mailing list<br><a href="mailto:Tinyos-help <at> millennium.berkeley.edu" target="_blank">Tinyos-help <at> millennium.berkeley.edu</a><br><a href="https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help" target="_blank">https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help</a><br>
</blockquote>
</div>
<br>
</div>
</div></div></blockquote>
</div>
<br>
</div>
</div>
</div></div>
Clement Nyirenda | 21 Oct 18:04 2014
Picon

Measuring MICAz Battery Voltage Reading in TinyOS2-1.2 TOSSIM simulations

Dear Colleagues:

I am running TOSSIM simulations of the CTP algorithm by using codes in tinyos-2.1.2/apps/testsTestNetwork. I am using make micaz sim under the TinyOs2.1.2 environment.

I would like to evaluate the energy aspects of CTP. I, therefore, need to get battery voltage level. I tried to use the DemoSensorC component, but it was always giving a huge constant value (48879), which is clearly not correct. This is also confirmed in http://tinyos.stanford.edu/tinyos-wiki/index.php/Sensing, where it has been mentioned that DemoSensorC gives fake voltage readings for MICAz.

When I tried to used the VoltageC component directly, I got the following error:

In component `Atm128AdcC':
/opt/tinyos-2.1.2/tos/chips/atm128/adc/Atm128AdcC.nc:74: no match
make: *** [sim-exe] Error 1

I commented out Atm128AdcP.Atm128Calibrate -> PlatformC; in line 74 of Atm128AdcC.nc, which causes the above error and initialized prescaler in Atm128AdcP.nc, which is in the same folder as Atm128AdcC.nc, to ATM128_ADC_PRESCALE_16 and disabled the platform prescaler option (ATM128_ADC_PRESCALE). I run make micaz sim again. This time, it complied successfully. But when I run python test.py, I am getting 0 for battery voltage. I tried to change the ADC Channel in VoltageP the following options:
    ATM128_ADC_SNGL_ADC0
    ATM128_ADC_SNGL_ADC1
    ATM128_ADC_SNGL_ADC2
    ATM128_ADC_SNGL_ADC3
    ATM128_ADC_SNGL_ADC4
    ATM128_ADC_SNGL_ADC5
    ATM128_ADC_SNGL_ADC6
    ATM128_ADC_SNGL_ADC7
I recompiled and run python test.py but I was still getting zero values for battery voltage.

I, therefore, would like to find out the proper steps that I must take in order to read battery voltage in TOSSIM when simulating MICAz motes under the TinyOs2.1.2 environment.

Your assistance will be greatly appreciated.

Best regards

*****
 Clement

<div><div dir="ltr">
<div>
<div>Dear Colleagues:<br><br>
</div>I am running TOSSIM simulations of the CTP algorithm by using codes in tinyos-2.1.2/apps/testsTestNetwork. I am using make micaz sim under the TinyOs2.1.2 environment.<br><br>
</div>I would like to evaluate the energy aspects of CTP. I, therefore, need to get battery voltage level. I tried to use the DemoSensorC component, but it was always giving a huge constant value (48879), which is clearly not correct. This is also confirmed in <a href="http://tinyos.stanford.edu/tinyos-wiki/index.php/Sensing">http://tinyos.stanford.edu/tinyos-wiki/index.php/Sensing</a>, where it has been mentioned that DemoSensorC gives fake voltage readings for MICAz.<br><br>When I tried to used the VoltageC component directly, I got the following error:<br><br><blockquote class="gmail_quote">In component `Atm128AdcC':<br>/opt/tinyos-2.1.2/tos/chips/atm128/adc/Atm128AdcC.nc:74: no match<br>make: *** [sim-exe] Error 1<br>
</blockquote>
<div><br></div>
<div>I commented out Atm128AdcP.Atm128Calibrate -&gt; PlatformC; in line 74 of Atm128AdcC.nc, which causes the above error and initialized prescaler in Atm128AdcP.nc, which is in the same folder as Atm128AdcC.nc, to ATM128_ADC_PRESCALE_16 and disabled the platform prescaler option (ATM128_ADC_PRESCALE). I run make micaz sim again. This time, it complied successfully. But when I run python test.py, I am getting 0 for battery voltage. I tried to change the ADC Channel in VoltageP the following options:<br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC0 <br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC1<br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC2<br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC3<br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC4<br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC5<br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC6<br>&nbsp;&nbsp;&nbsp; ATM128_ADC_SNGL_ADC7 <br>
</div>
<div>I recompiled and run python test.py but I was still getting zero values for battery voltage.<br><br>
</div>
<div>I, therefore, would like to find out the proper steps that I must take in order to read battery voltage in TOSSIM when simulating MICAz motes under the TinyOs2.1.2 environment.<br><br>
</div>
<div>Your assistance will be greatly appreciated.<br><br>
</div>
<div>Best regards<br>
</div>
<div>
<br clear="all"><div><div>
<div>
<div>&#65290;&#65290;&#65290;&#65290;&#65290;</div>
<div>&nbsp;Clement <br>
</div>
<a href="http://nthambazale.com/" target="_blank"></a><br>
</div>
</div></div>
</div>
</div></div>
IBRAHIM AHMED NEMER | 20 Oct 11:04 2014
Picon

I need a help

Really I want to modified the FTSP protocol to do another function within the code that is: each node when receive the local time of other nodes and the global time of the root node; this node will make an average value for all these values and update its time to this time!

any help, comments and suggestions 

Many thanks to all.
<div>
<div>Really I want to modified the FTSP protocol to do another function within the code that is: each node when receive the local time of other nodes and the global time of the root
 node; this node will make an average value for all these values and update its time to this time!
<div><br></div>
<div>any help, comments and suggestions&nbsp;</div>
<div><br></div>
<div>Many thanks to all.</div>
</div>
</div>
Rinoa Harasashi | 20 Oct 07:58 2014
Picon

Adding a second SHT11 sensor to TelosB

Hi,

We are trying to add a second SHT11 sensor to our TelosB - we replicated and renamed HplSensirionSht11C.nc, HalSensirionSht11C.nc, SensirionSht11C.nc, and HplSensirionSht11C.nc in platforms/telosa/chips/sht11. We also made sure than the references inside the files were correct.

In addition, we edited hardware.h in both platforms/telosa and platforms/telosb:

// HUMIDITY
TOSH_ASSIGN_PIN(HUM_SDA, 1, 5);
TOSH_ASSIGN_PIN(HUM_SCL, 1, 6);
TOSH_ASSIGN_PIN(HUM_PWR, 1, 7);

// HUMIDITY 2, RINOA ADDED

TOSH_ASSIGN_PIN(HUM_SDA, 2, 0);
TOSH_ASSIGN_PIN(HUM_SCL, 2, 1);
TOSH_ASSIGN_PIN(HUM_PWR, 1, 3);

We used GIO0, GIO1, and GIO2 for the data line, clock line, and power line respectively.

Our test program compiles, but it seems like the second SHT11 isn't working. Did we forget anything?

Thanks! ^_^ 
<div><div dir="ltr">Hi,<div><br></div>
<div>We are trying to add a second SHT11 sensor to our TelosB - we replicated and renamed HplSensirionSht11C.nc, HalSensirionSht11C.nc, SensirionSht11C.nc, and HplSensirionSht11C.nc in platforms/telosa/chips/sht11. We also made sure than the references inside the files were correct.</div>
<div><br></div>
<div>In addition, we edited hardware.h in both platforms/telosa and platforms/telosb:</div>
<div><br></div>
<div>
<div>// HUMIDITY</div>
<div>TOSH_ASSIGN_PIN(HUM_SDA, 1, 5);</div>
<div>TOSH_ASSIGN_PIN(HUM_SCL, 1, 6);</div>
<div>TOSH_ASSIGN_PIN(HUM_PWR, 1, 7);</div>
<div><br></div>
<div>// HUMIDITY 2, RINOA ADDED</div>
<div><br></div>
<div>
<div>TOSH_ASSIGN_PIN(HUM_SDA, 2, 0);</div>
<div>TOSH_ASSIGN_PIN(HUM_SCL, 2, 1);</div>
<div>TOSH_ASSIGN_PIN(HUM_PWR, 1, 3);</div>
<div><br></div>
<div>We used GIO0, GIO1, and GIO2 for the data line, clock line, and power line respectively.</div>
<div><br></div>
<div>Our test program compiles, but it seems like the second SHT11 isn't working. Did we forget anything?</div>
<div><br></div>
<div>Thanks! ^_^&nbsp;</div>
</div>
</div>
</div></div>
Vandana Bhasin | 20 Oct 07:28 2014
Picon

(no subject)


Hi,

When I compile my program with 'make micaz', my exe file is built,, but when I compile with 'make micaz sim'

In interface `HplAt45db':
/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:120: syntax error before `data'
/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:135: syntax error before `data'
/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:179: syntax error before `data'
In file included f rom /opt/tinyos-main-master/tos/chips/at45db/At45dbC.nc:33,
                 from /opt/tinyos-main-master/tos/chips/at45db/WireBlockStorageP.nc:20,
                 from /opt/tinyos-main-master/tos/chips/at45db/BlockStorageC.nc:35,
                 from PartitionToIndexAppC.nc:27:
In component `At45dbP':
/opt/tinyos-main-master/tos/chips/at45db/At45dbP.nc:411: conflicting types for `At45db.read'
/opt/tinyos-main-master/tos/chips/at45db/At45db.nc:166: previous declaration of `At45db.read'
/opt/tinyos-main-master/tos/chips/at45db/At45dbP.nc:424: conflicting types for `At45db.write'
/opt/tinyos-main-master/tos/chips/at45db/At45db.nc:73: previous declaration of `At45db.write'
In file included from /opt/tinyos-main-master/tos/chips/at45db/HplAt45dbC.nc:24,
                 from /opt/tinyos-main-master/tos/chips/at45db/At45dbC.nc:33,
                 from /opt/tinyos-main-master/tos/chips/at45db/WireBlockStorageP.nc:20,
                 from /opt/tinyos-main-master/tos/chips/at45db/BlockStorageC.nc:35,
   &n bsp;             from PartitionToIndexAppC.nc:27:
In component `HplAt45dbByteC':
/opt/tinyos-main-master/tos/chips/at45db/HplAt45dbByteC.nc:235: conflicting types for `HplAt45db.read'
/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:134: previous declaration of `HplAt45db.read'
/opt/tinyos-main-master/tos/chips/at45db/HplAt45dbByteC.nc:240: conflicting types for `HplAt45db.readBuffer'
/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:119: previous declaration of `HplAt45db.readBuffer'
/opt/tinyos-main-master/tos/chips/at45db/HplAt45dbByteC.nc:253: conflicting types for `HplAt45db.write'
/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:178: previous declaration of `HplAt45db.write'
In file included from /opt/tinyo s-main-master/tos/chips/cc1000/CC1000Const.h:51,
                 from /opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:41:
/opt/tinyos-main-master/tos/chips/atm128/sim/atm128const.h:19:22: error: pgmspace.h: No such file or directory
In file included from PartitionToIndexAppC.nc:43:
In component `CC1000ControlM':
/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc: In function `cc1000SetFrequency':
/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:166: implicit declaration of function `pgm_read_dword'
/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:187: implicit declaration of function `pgm_read_word'
/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc: In function `CC1000Control.tunePreset':
/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:302: implicit declaration of function `pgm_read_byte'
make: *** [sim-exe] Error 1

1.I searched for pgmspace.h file using find command, it was present in .zip format. But I am unable to unzip the file using unzip commad. It says it is retreiving but doesn't show a retrieved file in the same directory.
2. Why are errors coming when compiling for sim directory.

Please help...

Regards

Vandana



<div><div>
<div class=""><br></div>
<div class="">Hi,</div>
<div class=""><br class=""></div>
<div class="">When I compile my program with 'make micaz', my exe file is built,, but when I compile with 'make micaz sim' <br class="">
</div>
<div class=""><br class=""></div>
<div class="">In interface `HplAt45db':<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:120: syntax error before `data'<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:135: syntax error before `data'<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:179: syntax error before `data'<br class="">In file included f
 rom /opt/tinyos-main-master/tos/chips/at45db/At45dbC.nc:33,<br class="">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from /opt/tinyos-main-master/tos/chips/at45db/WireBlockStorageP.nc:20,<br class="">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from /opt/tinyos-main-master/tos/chips/at45db/BlockStorageC.nc:35,<br class="">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from PartitionToIndexAppC.nc:27:<br class="">In component `At45dbP':<br class="">/opt/tinyos-main-master/tos/chips/at45db/At45dbP.nc:411: conflicting types for `At45db.read'<br class="">/opt/tinyos-main-master/tos/chips/at45db/At45db.nc:166: previous declaration of `At45db.read'<br class="">/opt/tinyos-main-master/tos/chips/at45db/At45dbP.nc:424: conflicting types for `At45db.write'<br class="">/opt/tinyos-main-master/tos/chips/at45db/At45db.nc:73: previous declaration of `At45db.write'<br class="">In file included from /opt/tinyos-main-master/tos/chips/at45db/HplAt45dbC.nc:24,<br class="">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from /opt/tinyos-main-master/tos/chips/at45db/At45dbC.nc:33,<br class="">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from /opt/tinyos-main-master/tos/chips/at45db/WireBlockStorageP.nc:20,<br class="">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from /opt/tinyos-main-master/tos/chips/at45db/BlockStorageC.nc:35,<br class="">&nbsp;&nbsp;&nbsp;&amp;n
 bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from PartitionToIndexAppC.nc:27:<br class="">In component `HplAt45dbByteC':<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45dbByteC.nc:235: conflicting types for `HplAt45db.read'<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:134: previous declaration of `HplAt45db.read'<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45dbByteC.nc:240: conflicting types for `HplAt45db.readBuffer'<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:119: previous declaration of `HplAt45db.readBuffer'<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45dbByteC.nc:253: conflicting types for `HplAt45db.write'<br class="">/opt/tinyos-main-master/tos/chips/at45db/HplAt45db.nc:178: previous declaration of `HplAt45db.write'<br class="">In file included from /opt/tinyo
 s-main-master/tos/chips/cc1000/CC1000Const.h:51,<br class="">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 from /opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:41:<br class="">/opt/tinyos-main-master/tos/chips/atm128/sim/atm128const.h:19:22: error: pgmspace.h: No such file or directory<br class="">In file included from PartitionToIndexAppC.nc:43:<br class="">In component `CC1000ControlM':<br class="">/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc: In function `cc1000SetFrequency':<br class="">/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:166: implicit declaration of function `pgm_read_dword'<br class="">/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:187: implicit declaration of function `pgm_read_word'<br class="">/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc: In function
  `CC1000Control.tunePreset':<br class="">/opt/tinyos-main-master/tos/chips/cc1000/CC1000ControlM.nc:302: implicit declaration of function `pgm_read_byte'<br class="">make: *** [sim-exe] Error 1<br class="">
</div>
<div class=""><br></div>
<div class="">1.I searched for pgmspace.h file using find command, it was present in .zip format. But I am unable to unzip the file using unzip commad. It says it is retreiving but doesn't show a retrieved file in the same directory.</div>
<div class="">2. Why are errors coming when compiling for sim directory.</div>
<div class=""><br></div>
<div class="">Please help... <br>
</div>
<div class=""><br></div>
<div class="">Regards</div>
<div class=""><br></div>
<div class="">Vandana<br>
</div>
<div class=""><br></div>
<div class=""><br class=""></div>
<div class=""><br class=""></div>
</div></div>
Andreas Weigel | 17 Oct 16:39 2014
Picon

Change-suggestion for atm128rfa1 RadioDriverLayer to make it safe to use for atmega64/128/256rfr2

Hi everyone,

Suggestion: Add the following line somewhere to the init code:
RX_SYN &= ~(1 << 6);

Rationale:
I just had some "fun time" with a self-made C-port (not very beautiful, 
but it does its job) of the atm128rfa1 RFA1DriverLayerP (and the 
corresponding rfxlink layers).

Letting four ATmega256rfr2-based nodes send out broadcast packets as 
fast as possible (having the whole stack in place, including backoffs 
etc.), lead to RADIO_ASSERT(!radioIrq) being triggered in the RX_END 
ISR. After some happy debugging and thinking (is my protocolstack 
actually to slow in processing the tasklet code stuff?) I was sure that 
this should not be possible.

I then stumbled across a new and greatly-documented feature of the rfr2 
named RX_OVERRIDE, which is enabled on this chip by default (who does 
such things?). This seems to lead to RX_END interrupts which are 
triggered very soon (< 20 us) after the corresponding RX_START. In rare 
circumstances when RX_START was interrupted again by the RadioAlarm 
interrupt (and correspondingly, the TosRandomCollisionLayer 
RadioAlarm.fired() code was executed), service_radio got deferred long 
enough to allow for the RX_END to occur and the RADIO_ASSERT to happen. 
Deactivating RX_OVERRIDE solved the problem.

I do not know (as I could not try out or know how fast the actual TinyOS 
stack handles the code), if this problem would really affect an 
ATmega256rfr2 running TinyOS (which I did not), but I think it at least 
very possible. Considering this, I suggest to add the code shown above 
to the init function of the driver to make the current radio driver safe 
for all rfr2-type chips (also in case someone "ports" the code to rfr2 
and is -- like me -- unaware of this new feature), so that other people 
are spared the pain I just lived through during the last few days

Regards,
Andreas
Abhishek Trivedi | 17 Oct 04:10 2014
Picon

From: Abhishek Trivedi

Hi

http://nhconstitucion.cl/center.php?general=dwqd3em7mrb4v5

abhishek_2180 <at> hotmail.com

IBRAHIM AHMED NEMER | 13 Oct 05:35 2014
Picon

What this sign mean |= in nesc language ?

 

What does this sign mean |= in nesc language ?

Any comment !

 

BR.

<div>
<div class="WordSection1">
<p class="MsoNormal"><p>&nbsp;</p></p>
<p class="MsoNormal">What does this sign mean <span>|=</span> in nesc language ?<p></p></p>
<p class="MsoNormal">Any comment !<p></p></p>
<p class="MsoNormal"><p>&nbsp;</p></p>
<p class="MsoNormal">BR.<p></p></p>
</div>
</div>
Wen Wen | 8 Oct 22:24 2014
Picon

Compiling C file (.c, .h) with TinyOS using GMP library

Hi All,

Thank you in advance!

I wrote my own .c and .h file using gmp library, but I need to use functions wrote in my .c file in my TinyOS application. How should I include this .h file, and how can I link gmp library to my TinyOS application? 

I think I should do something to the makefile, however, I am new to NesC, would you please show me an example?

Thanks!

Owen
<div><div dir="ltr">Hi All,<div><br></div>
<div>Thank you in advance!</div>
<div><br></div>
<div>I wrote my own .c and .h file using gmp library, but I need to use functions wrote in my .c file in my TinyOS application. How should I include this .h file, and how can I link gmp library to my TinyOS application?&nbsp;</div>
<div><br></div>
<div>I think I should do something to the makefile, however, I am new to NesC, would you please show me an example?</div>
<div><br></div>
<div>Thanks!</div>
<div><br></div>
<div>Owen</div>
</div></div>

Gmane