Masao Uebayashi | 1 Oct 16:41 2011
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mipsX_subr.S:tlb_invalid_exception

In the following code:

1693         bnez    k0, MIPSX(kern_tlbi_odd)
1694          nop
1695
1696         INT_L   k0, 0(k1)                       # get PTE entry
1697         _SLL    k0, k0, WIRED_SHIFT             # get rid of "wired" bit
1698         _SRL    k0, k0, WIRED_SHIFT
1699         _MTC0   k0, MIPS_COP_0_TLB_LO0          # load PTE entry
1700         COP0_SYNC
1701         and     k0, k0, MIPS3_PG_V              # check for valid entry
1702 #ifdef MIPS3
1703         nop                                     # required for QED5230
1704 #endif
1705         beqz    k0, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid
1706          nop                                    # - delay slot -

- Why load PTE before checking V bit?  If invalid,
kern_gen_exception() will load PTE later (uvm_fault() -> pmap_enter()
-> tlb_update()), right?

1708         INT_L   k0, 4(k1)                       # get odd PTE entry
1709         _SLL    k0, k0, WIRED_SHIFT
1710         mfc0    k1, MIPS_COP_0_TLB_INDEX
1711         _SRL    k0, k0, WIRED_SHIFT
1712         sltiu   k1, k1, MIPS3_TLB_WIRED_UPAGES  # Luckily this is
MIPS3_PG_G
1713         or      k1, k1, k0
1714         _MTC0   k0, MIPS_COP_0_TLB_LO1          # load PTE entry
1715         COP0_SYNC
(Continue reading)

Masao Uebayashi | 2 Oct 07:58 2011
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Re: mipsX_subr.S:tlb_invalid_exception

http://mail-index.netbsd.org/port-mips/2002/11/17/0005.html

According to this, the G bit is nothing to do with "wiring".

I also wonder how the wired bit in pte is used in mips.

On Sat, Oct 1, 2011 at 11:41 PM, Masao Uebayashi <uebayasi <at> gmail.com> wrote:
> In the following code:
>
> 1693         bnez    k0, MIPSX(kern_tlbi_odd)
> 1694          nop
> 1695
> 1696         INT_L   k0, 0(k1)                       # get PTE entry
> 1697         _SLL    k0, k0, WIRED_SHIFT             # get rid of "wired" bit
> 1698         _SRL    k0, k0, WIRED_SHIFT
> 1699         _MTC0   k0, MIPS_COP_0_TLB_LO0          # load PTE entry
> 1700         COP0_SYNC
> 1701         and     k0, k0, MIPS3_PG_V              # check for valid entry
> 1702 #ifdef MIPS3
> 1703         nop                                     # required for QED5230
> 1704 #endif
> 1705         beqz    k0, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid
> 1706          nop                                    # - delay slot -
>
> - Why load PTE before checking V bit?  If invalid,
> kern_gen_exception() will load PTE later (uvm_fault() -> pmap_enter()
> -> tlb_update()), right?
>
> 1708         INT_L   k0, 4(k1)                       # get odd PTE entry
> 1709         _SLL    k0, k0, WIRED_SHIFT
(Continue reading)

Ryo Shimizu | 14 Oct 07:53 2011

Re: Ralink RT305x NetBSD


>I learned that NetBSD CVS tree now has Ralink RT305x Soc
>support.  Does anyone out there have recommendations to
>run NetBSD on Ralink products?  320MHz 32K/16K cache
>MIPS core is a good vehicle to stick on.  Hack friendly, easy
>to go products are welcome.

Im trying to run NetBSD on Fonera FON2405E.
but this board has no console, so we need serial cable hack. (e.g. MAX232C)

   http://www.nerv.org/~ryo/d/img/FON2405E_007.jpg

power on with pressing microswitch, I could enter U-boot prompt menu.
this board is very cheap and hack friendly :-)

	U-Boot 1.1.3 (Jan  6 2010 - 07:10:30)
	RT3052 # tftp 80010000 netbsd.bin
	
	 netboot_common, argc= 3 
	
	 NetTxPacket = 0x81FE4DC0 
	Trying Eth0 (10/100-M)
	
	 ETH_STATE_ACTIVE!! 
	Using Eth0 (10/100-M) device
	TFTP from server 10.10.10.3; our IP address is 10.10.10.200
	Filename 'netbsd.bin'.
	
	 TIMEOUT_COUNT=10,Load address: 0x80010000
	Loading: Got ARP REPLY, set server/gtwy eth addr (00:02:2a:dd:58:24)
(Continue reading)


Gmane