Hi, guys, I learned that NetBSD CVS tree now has Ralink RT305x Soc support. Does anyone out there have recommendations to run NetBSD on Ralink products? 320MHz 32K/16K cache MIPS core is a good vehicle to stick on. Hack friendly, easy to go products are welcome. Toru Nishimura / ALKYL Technology
On Sep 8, 2011, at 10:03 PM, Toru Nishimura wrote: > Hi, guys, > > I learned that NetBSD CVS tree now has Ralink RT305x Soc > support. Does anyone out there have recommendations to > run NetBSD on Ralink products? 320MHz 32K/16K cache > MIPS core is a good vehicle to stick on. Hack friendly, easy > to go products are welcome. Actually, the RT3883. I have no idea if it works on the earlier RT305x. Currently I have the Cradlepoint MBR1400. These also contain the RT3883 - TRENDnet TEW-691GR (single band ap/router) - TRENDnet TEW-687GA (single band sta/bridge) - Belkin N450 F9K1003 (single band ap/router) - Belkin N750 F9K1103 (dual band concurrent ap/router) The Belkin N750 has USB which is needed for root unless you want to run diskless. Now that you will need to add a serial port connector to the motherboard plus uses a 3.3V serial frob or cable.
In the following code: 1693 bnez k0, MIPSX(kern_tlbi_odd) 1694 nop 1695 1696 INT_L k0, 0(k1) # get PTE entry 1697 _SLL k0, k0, WIRED_SHIFT # get rid of "wired" bit 1698 _SRL k0, k0, WIRED_SHIFT 1699 _MTC0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry 1700 COP0_SYNC 1701 and k0, k0, MIPS3_PG_V # check for valid entry 1702 #ifdef MIPS3 1703 nop # required for QED5230 1704 #endif 1705 beqz k0, _C_LABEL(MIPSX(kern_gen_exception)) # PTE invalid 1706 nop # - delay slot - - Why load PTE before checking V bit? If invalid, kern_gen_exception() will load PTE later (uvm_fault() -> pmap_enter() -> tlb_update()), right? 1708 INT_L k0, 4(k1) # get odd PTE entry 1709 _SLL k0, k0, WIRED_SHIFT 1710 mfc0 k1, MIPS_COP_0_TLB_INDEX 1711 _SRL k0, k0, WIRED_SHIFT 1712 sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G 1713 or k1, k1, k0 1714 _MTC0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry 1715 COP0_SYNC(Continue reading)
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