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Pramod Srinivasan | 4 Apr 2006 23:35
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SMP support

Hi Folks,

I was wondering if NetBSD has SMP supported on MIPS paltform, can
someone help me with this?

Any help greatly appreciated.

Thanks,
Pramod
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Izumi Tsutsui | 22 Apr 2006 07:41
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separate statclock(9) with mips3 CP0 timer interrupt

Hi,

Current several mips ports with MIP3 CPUs (evbmips, sgimips etc.)
use CPU internal CP0 clock timer interrupts for hardclock(9),
but some other ports (arc, cobalt etc) use their own external
timer interrupts for hardclock(9) and CPU CP0 clock interrupt
(i.e. CPU INT5) is not used.

Is it worth to prepare a separate interrupt handler for
statclock(9) with CP0 clock interrupt on such mips port?
I guess it may provide more precise statistics on the system,
but I'm afraid number of interrupts (and its overhead) is also
increased ~two times.

I've written some code for NetBSD/cobalt (derived from hp300 and
arm/footbridge), but is there any good benchmark for this?
---
Izumi Tsutsui

Index: cobalt/autoconf.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/autoconf.c,v
retrieving revision 1.19
diff -u -r1.19 autoconf.c
--- cobalt/autoconf.c	21 Apr 2006 18:17:45 -0000	1.19
+++ cobalt/autoconf.c	22 Apr 2006 01:21:48 -0000
 <at>  <at>  -52,11 +52,13  <at>  <at> 
 	(void)splhigh();

 	evcnt_attach_static(&hardclock_ev);
(Continue reading)

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Garrett D'Amore | 22 Apr 2006 08:52

Re: separate statclock(9) with mips3 CP0 timer interrupt

Out of curiosity, why not use CPU INT5 (CP0 clock interrupt) for
hardclock? 

I never even knew there was support for a separate statistics clock.

    -- Garrett

Izumi Tsutsui wrote:
> Hi,
>
> Current several mips ports with MIP3 CPUs (evbmips, sgimips etc.)
> use CPU internal CP0 clock timer interrupts for hardclock(9),
> but some other ports (arc, cobalt etc) use their own external
> timer interrupts for hardclock(9) and CPU CP0 clock interrupt
> (i.e. CPU INT5) is not used.
>
> Is it worth to prepare a separate interrupt handler for
> statclock(9) with CP0 clock interrupt on such mips port?
> I guess it may provide more precise statistics on the system,
> but I'm afraid number of interrupts (and its overhead) is also
> increased ~two times.
>
> I've written some code for NetBSD/cobalt (derived from hp300 and
> arm/footbridge), but is there any good benchmark for this?
> ---
> Izumi Tsutsui
>
>
> Index: cobalt/autoconf.c
> ===================================================================
(Continue reading)

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Izumi Tsutsui | 22 Apr 2006 09:23
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Re: separate statclock(9) with mips3 CP0 timer interrupt

In article <4449D2AF.2070308 <at> tadpole.com>
garrett_damore <at> tadpole.com wrote:

> Out of curiosity, why not use CPU INT5 (CP0 clock interrupt) for
> hardclock? 

Not sure, but I guess:
- native OSes (Ultrix, WindowsNT etc.) don't use it
- MIPS1 CPUs don't have it (but have common external timers?)
- external timers could be more flexible then internal one
- no certain way to get precise CPU clock frequency on all models
  (but external timer clock is CPU indepenedent?)
etc?

> I never even knew there was support for a separate statistics clock.

It is mentioned in the D&I of 4.4BSD section 3.4,
but I don't know it's still useful for modern systems.
(the example in the book is hp300)
---
Izumi Tsutsui
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