D cahe flush in cpu_lwp_fork()

Hi,

There is the following code segment in cpu_lwp_fork()::vm_machdep.c

#ifdef MIPS3_PLUS
        /*
         * To eliminate virtual aliases created by pmap_zero_page(),
         * this cache flush operation is necessary.
         * VCED on kernel stack is not allowed.
         * XXXJRT Confirm that this is necessry, and/or fix 
         * XXXJRT pmap_zero_page().
         */
        if (CPUISMIPS3 && mips_sdcache_line_size)
                mips_dcache_wbinv_range((vaddr_t) l2->l_addr, USPACE);
#endif

I think it's wrong to flush Dcache pointed by l_addr since the storage (USPACE
of l2) is going to be filled _very first time_ by two memcpy() below.  The code
trys to wbinv() for never-written address range.

The person who added the code segment looks concerned about VCED.
I emphasis here 1) VCE makes sence in L2 equipped R4000 processors.  No
other MIPS processor does post VCE.  R10000 resolves VCE condition by
hardware.  2)  As Jason mentions, the fundamental issue lies where the USPACE
contents (two 4K pages) is pre-zeroed by pmap_zero_page(), but the routine
is designed to do the work by zeroing KSEG0 of PA.  It's b-o-g-u-s.   The right
solution is to fix pmap_zero_page() taking the target VA (l_addr in this case) into
account for VIPA cache machinary, however,  uvm_uarea_alloc() looks very naive
and there is much room to make things correct....

PCI bus 66MHz configuration

hi all,

i m working on evbmips port of NetBSD. How can i configure PCI bus for 66MHz. 
Should i do it in mach_init function or can i also perform the same at the 
time of PCI-BUS scan where we detect the pci devices.(probe_bus).

Since the setting to 66Mhz involves resetting of the PCI controller. Do i have 
to reinitializa everything(PCI controller) from the sratch.
--

-- 
Regards,
Rishabh Kumar Goel
Software Engineer
SoCrates Software India Pvt. Ltd.
Bangalore

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Re: PCI bus 66MHz configuration

Rishabh Kumar Goel asked;

> i m working on evbmips port of NetBSD. How can i configure PCI bus for 66MHz. 

It's a target hardware specific question.  Please consult hardware references.

> Should i do it in mach_init function or can i also perform the same at the 
> time of PCI-BUS scan where we detect the pci devices.(probe_bus).

Neither.   I assume here your target hardware design is similar to a conventional
PCI-enabled SoC available today.  These days such the processor has large
number of hardware registers to adjust many functional options like as knobs and
levers switch, which are sometimes called "strap options".   Every option must be
prepared appropriately for the target product parametrics *prior to* NetBSD
kernel is loaded.   That's, detailed knob/lever preparation is "ROM monitor
(BIOS in PC term) duty, not by NetBSD kernel.

However, sometimes it'd be necessary to have the system controller
("NorthBridge")  as a real device entity to control, probably as "pcih".  Please
*carefully* source codes of other NetBSD ports have similar designs to understand
what I'm trying to tell.   The rule of thumb of understanding "NetBSD way" is to
look and search the source code that does have similar design.

> Since the setting to 66Mhz involves resetting of the PCI controller. Do i have 
> to reinitializa everything(PCI controller) from the sratch.

You need to modify your ROM monitor.

Toru Nishimura/ALKYL Technology

How to verify PCI Bus Speed

Hi,
after all the jugglery i am able to configure the PCI bus for 66Mhz. How can i 
verify whether it is actually working on 66Mhz or not. I have checked it with 
the processor reg. which says its 66Mhz. but apart from that is there any 
other way to verify this.
--

-- 
Regards,
Rishabh Kumar Goel
Software Engineer
SoCrates Software India Pvt. Ltd.
Bangalore

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DMA Framework (more than 1 dma peripheral)

No minimo, dê o beneficio da dúvida!

Boas, antes de mais gostaria de informar que o seu email foi retirado de uma ou mais páginas
da Internet e que este seu email será apagado, logo após o envio desta mensagem.

O que me faz enviar esta mensagem, é muio simples, tenho estado a desenvolver um negócio independente
a partir de casa no últmos 9 meses, o qual já conhecia ŕ mais de 10 anos, mas só há 9 meses tive a
curiosidade e motivo para o analizar. Como podem entender abraceio-o e, gostaria de lhe dar a conhecer
esta oportunidade. Se por qualquer motivo os seus sonhos de estilo de vida lhe parecem cada vez
mais longinquos, se por algum motivo acha que, independentemente da sua idade, nunca os vai conseguir
alcançar, gostaria de lhe poder dar a analizar esta oportunidade.

Quantos de nós trabalha-mos um vida inteira para construir algo e chega-mos ao fim da vida sem ter nada
ou tendo apenas uma parte muito pequena daquilo que ambiciona-mos.

Gostaria de lhe perguntar se estaria disposto(a), a apenas com algumas horas por semana, e fazendo um
sacrificio e
esforço extra, durante os próximo 3 a 4 anos, dedicar essas horas por semana e daí fazer crescer um
rendimento tal que năo se teria de preocupar com a sua vida fincanceira.

O que me diz a poder ganhar 500€ extra, juntando ao dinheiro que já ganha, e fazer com que estes 500€
crescam de męs pra męs a uma velocidade impressionante. Estaria disposto a fazer esse esforço?

Se esta no minimo curioso para analizar esta oportunidade, entăo contacte-me de forma a poder assitir
via internet a uma apresentaçăo no conforto da sua casa, e talvez, quem sabe, começar a mudar algo na sua vida.

Fernanda Manuela
as1531033 <at> sapo.pt

Interrupt Priority

Hi,

I am working on MIPS Target Board, In the source code I found that they have assigned the priorities for each
interrupt like dma[0-3], sio[0-1], sdram, INT[0-5], tmr[0-3]...., I want to know on what basis they are
prioritising? Please put some light on it.

Regards

____________________________________________________________
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Removing MIPS3_L2CACHE_ABSENT

All,

Tsutsui-san (I think) committed changes to arch/mips/mips/pmap.c a while back
that rendered MIPS3_L2CACHE_ABSENT redundant -- all code wrapped within the
conditional is in turn wrapped in a conditional testing whether
mips_sdcache_line_size is zero.

The below patch removes the offending #ifdefs.  If there is no objection, I'd
like to commit this next Monday.

-- Chris
	GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5  938E 023E EEFB FEB9 DE7F)

Index: pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/pmap.c,v
retrieving revision 1.153
diff -u -r1.153 pmap.c
--- pmap.c	1 Nov 2003 14:48:16 -0000	1.153
+++ pmap.c	12 Dec 2003 02:02:13 -0000
 <at>  <at>  -264,7 +264,6  <at>  <at> 
 void mips_dump_segtab(struct proc *);
 #endif

-#if defined(MIPS3_L2CACHE_ABSENT)
 /*
  * Flush virtual addresses associated with a given physical address
  */
 <at>  <at>  -288,7 +287,6  <at>  <at> 
 	}
 #endif
 }
-#endif	/* MIPS3_L2CACHE_ABSENT */

 /*
  *	Bootstrap the system enough to run with virtual memory.
 <at>  <at>  -1583,7 +1581,7  <at>  <at> 

 	mips_pagezero((caddr_t)MIPS_PHYS_TO_KSEG0(phys));

-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS)	/* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged WB cache,
 	 * and no L2 cache to warn of aliased mappings,	we must force a
 <at>  <at>  -1595,7 +1593,7  <at>  <at> 
 	 */
 	if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
-#endif	/* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 }

 /*
 <at>  <at>  -1616,7 +1614,7  <at>  <at> 
 		printf("pmap_copy_page(%lx) dst nonphys\n", (u_long)dst);
 #endif

-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS) /* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged cache,
 	 * and no L2 cache to warn of aliased mappings, we must force an
 <at>  <at>  -1635,12 +1633,12  <at>  <at> 
 		mips_flushcache_allpvh(src);
 /*		mips_flushcache_allpvh(dst); */
 	}
-#endif	/* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */

 	mips_pagecopy((caddr_t)MIPS_PHYS_TO_KSEG0(dst),
 		      (caddr_t)MIPS_PHYS_TO_KSEG0(src));

-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS) /* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged WB cache,
 	 * and no L2 cache to warn of aliased mappings,	we must force a
 <at>  <at>  -1656,7 +1654,7  <at>  <at> 
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
 	}
-#endif	/* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 }

 /*
 <at>  <at>  -1882,7 +1880,7  <at>  <at> 
 		pv->pv_pmap = pmap;
 		pv->pv_next = NULL;
 	} else {
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS) /* XXX mmu XXX */
 		if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
 			/*
 			 * There is at least one other VA mapping this page.
 <at>  <at>  -1935,7 +1933,7  <at>  <at> 
 			}
 #endif	/* !MIPS3_NO_PV_UNCACHED */
 		}
-#endif /* MIPS3_PLUS && MIPS3_L2CACHE_ABSENT */
+#endif /* MIPS3_PLUS */

 		/*
 		 * There is at least one other VA mapping this page.

Re: Removing MIPS3_L2CACHE_ABSENT

In message <20031212020253.GB12092 <at> rezrov.net>, you write: 

-> The below patch removes the offending #ifdefs.  If there is no objection,
-> I'd like to commit this next Monday.

Please do; I've had this change sitting in one of my source trees for a
long time, just never got around to checking it in.

--rafal

----
Rafal Boni                                                     rafal <at> pobox.com
  We are all worms.  But I do believe I am a glowworm.  -- Winston Churchill

Re: Removing MIPS3_L2CACHE_ABSENT

On Fri, Dec 12, 2003 at 09:30:55AM -0500, Rafal Boni wrote:

> Please do; I've had this change sitting in one of my source trees for a
> long time, just never got around to checking it in.

You and me both :)

My initial concern was that various platforms might leave mips_sdcache_line_size
uninitialized, with disasterous results ... but a quick grep reveals that
mips3_get_cache_config() does the right thing, so things should be okay.

I'll go ahead and commit it, then ... this will fix one of the two showstoppers
for sgimips, at least.

-- Chris
	GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5  938E 023E EEFB FEB9 DE7F)