Mouse | 6 Feb 00:08 2012

interrupt hardware?

I've got some bare-metal code written on my Dreamcast (I'm playing with
the BBA) and now I'm trying to use interrupts.  But I'm not receiving
any interrupts even though, everything I've found is set up right: the
BBA interrupt mask register has the relevant enables set, the interrupt
status register says it's trying to interrupt, and BL and the interrupt
level bits are all clear in the SR.  But I'm still not getting any
interrupt.  So I assume there's some other piece of hardware in the
interrupt path which is getting in the way.

The NetBSD code is somewhat of a twisty maze of data structures, all
different; I may be able to untangle it, but it would be difficult and
error-prone.  So I've been searching for "interrupt" in various places,
especially Marcus Comstedt's stuff, and so far the most informative
stuff I've found has been in KallistiOS, which gives me the impression
there's an ASIC there, but it doesn't seem to include much
documentation.

I'm going to be trying to figure out what I can from the KOS and NetBSD
code, but if there's a document somewhere I missed, I'd very much
appreciate a pointer - especially if my guess is wrong.

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Academy | 6 Feb 22:17 2012

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Marcus Comstedt | 13 Feb 12:46 2012
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Re: interrupt hardware?


Mouse <mouse <at> Rodents-Montreal.ORG> writes:

> I've got some bare-metal code written on my Dreamcast (I'm playing with
> the BBA) and now I'm trying to use interrupts.
[...]
> The NetBSD code is somewhat of a twisty maze of data structures, all
> different; I may be able to untangle it, but it would be difficult and
> error-prone.
[...]
> which gives me the impression
> there's an ASIC there, but it doesn't seem to include much
> documentation.

Yes.  The BBA is a PCI device behind the "GAPSPCI" host adapter,
so you should look at gaps_intr_establish() in gapspci_pci.c,
which in turn calls sysasic_intr_establish() in sysasic.c.  There
you'll see how to unmask the interrupt.  The sysasic basically has 32
interrupt sources, each of which can be enabled at different CPU IRQ
levels by setting the corresponding source bit in the
corresponding level register.  You can check which events are
currently fired by reading 0xa05f6900.  The enable words are at

0xa05f6910  enable at CPU IRQ level 13
0xa05f6920  enable at CPU IRQ level 11
0xa05f6930  enable at CPU IRQ level 9

  // Marcus

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