Greg A. Woods | 16 Oct 2011 05:32
X-Face
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Performance Monitoring Counters (PMC, PERFCTRS) and SMP?

Is anyone by any chance working on SMP support for PMC / PERFCTRS?

Apparently FreeBSD is now able to support PMC on SMP machines, but I
can't find any hint of anything related for NetBSD.

I ask mostly because I'm flustered by getrusage(2) being as good as
useless for even the most basic of benchmarking purposes, and
gettimeofday() also being useless in a multi-user environment.

I guess a second question might be if anyone's thought of pulling over
FreeBSD's fix, or re-implementing something similar, to at least make
getrusage() monotonic?

(on a related note, does anyone know of any decent CPU measurement tool
for use inside a process on OS X?  getrusage() is broken there too.)

--

-- 
						Greg A. Woods

+1 250 762-7675                                RoboHack <woods <at> robohack.ca>
Planix, Inc. <woods <at> planix.com>      Secrets of the Weird <woods <at> weird.com>
Erik Fair | 19 Apr 2010 18:49
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state of NetBSD SMP

So, what's the current state of NetBSD SMP, i.e. how many kernel  
subsystems do we still have to get out from under the big lock?

	curious,

	Erik <fair <at> netbsd.org>

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Andrew Doran | 23 Mar 2009 23:46
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>32 core support

For anyone interested in working on >32 core support here is a interesting
link. It suggests that `bochs' can be patched to emulate a 48 core system.

	http://forum.osdev.org/viewtopic.php?f=1&t=19192

x86 currently supports 32 cores/threads out of the box, but it may not be
enough for commodity servers within a couple of years. The low-level issues
I am aware of are:

- There are static arrays that will not scale (MAXCPUS). Some of these could
  be folded into cpu_data, leaving us with a single array to worry about
  sizing dynamically.

- There are 32-bit masks, the majority of which are in platform-specific
  code. The kcpuset code needs work to do stuff that the kernel uses, like
  atomic operations, scans and so on. A few masks are in MI code and some
  will #error if MAXCPUS > 32.

- 32-bit systems don't have enough kernel address space to support large
  numbers of cores effectively, although i386 could be interesting as a
  bring-up target with an emulator like bochs.

- The x86 apic code currently supports 255 cores max (assuming 255 cores
  plus 1 IOAPIC). x2apic support may be required in the future. As far as I
  understand it, future systems may have cores that can only be addressed
  with the x2apic's 32-bit IDs.

- The mutex/rwlock code will not scale to large numbers of cores because it
  does a linear scan of the CPU list. There are memory order and data
  structure visibility issues to be overcome.
(Continue reading)

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(Continue reading)

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Anthony Mallet | 13 Jan 2008 21:21
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new xemacs segfault, can anyone reproduce this?

Hi,

Since about 2-3 monthes, my xemacs is segfaulting from times to times
under -current SMP. Should I say this never (ever) happened before and I
did not change xemacs version, etc. (although everything has been
recompiled with current userland).

Today I finally isolated some reproducible behaviour, which disapear when
I put all but one CPU offline (thus my posting in this list).
I would like to know if some of you can also reproduce this problem (you
need to 'make extract' in pkgsrc/editor/xemacs):

ficus[~]# uname -a
NetBSD ficus 4.99.49 NetBSD 4.99.49 (FICUS) #96: Sun Jan 13 17:58:31 CET 2008 
troot <at> ficus:/usr/obj/sys/arch/i386/compile/FICUS i386

ficus[~]# cpuctl list
ID   Unbound LWPs Interrupts     Last change
---- ------------ -------------- ----------------------------
0    online       intr           Sun Jan 13 19:50:51 2008
3    online       intr           Sun Jan 13 21:01:23 2008
2    online       intr           Sun Jan 13 21:01:24 2008
1    online       intr           Sun Jan 13 21:01:25 2008

And as a regular user with X display:
ficus[~] > xemacs -vanilla -eval '(setq progress-feedback-use-echo-area t)' -eval
'(font-lock-mode)' /usr/pkgsrc/editors/xemacs/work/xemacs-21.4.17/src/extents.c

xemacs should segfault 9 times out of 10, and at least exhibit wrong
keyword decoration.
(Continue reading)

Marcelo Schmidt | 27 Oct 2007 19:26

cpu1: failed to become ready

Problem:
cpu1 at mainbus0: apid 6 (application processor)
cpu1: starting
cpu1: failed to become ready

The system has 2 Xeon 2.66Mhz with HT.  Randomly one cpu or another might
fail become ready between reboots.  Anyone had found this issue before?

NetBSD moon 4.0_RC3 NetBSD 4.0_RC3 (GENERIC.MP) #0: Tue Oct 16 01:41:36 PDT 2007 
builds <at> wb34:/home/builds/ab/netbsd-4-0-RC3/i386/200710160011Z-obj/home/builds/ab/netbsd-4-0-RC3/src/sys/arch/i386/compile/GENERIC.MP i386

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 4.0_RC3 (GENERIC.MP) #0: Tue Oct 16 01:41:36 PDT 2007
	builds <at> wb34:/home/builds/ab/netbsd-4-0-RC3/i386/200710160011Z-obj/home/builds/ab/netbsd-4-0-RC3/src/sys/arch/i386/compile/GENERIC.MP
total memory = 3071 MB
rbus: rbus_min_start set to 0xc0000000
avail memory = 3005 MB
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
BIOS32 rev. 0 found at 0xfd6e0
mainbus0 (root)
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel Xeon (686-class), 2657.98 MHz, id 0xf25
cpu0: features bfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features bfebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>
(Continue reading)

Ming Lei | 3 Oct 2007 21:17
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softintr running on boot CPU only?


I am running 3.0.1 kernel on Dell SC430(two pentium cores) and run 
vmstats saw softinterrupt only on boot CPU. Is it the way that the 3.0.1 
kernel code supported to do? How about 4.0 and upcoming 5.0?

There is really not much documents on SMP/APCI implementation on x86 
besides a few email threads. Does someone know more can share with me?

Thanks
Ming

John Klos | 17 Aug 2007 19:48

Looking for help with high volume MySQL

Hi, all,

I'm looking for help with setting up NetBSD machines in a MySQL cluster. I 
have lots of questions, such as:

Is SMP efficient enough with NetBSD that a single 4, 6, or 8 processor 
system would be as capable or perhaps more capable than, say, 2, 3, or 4 
separate dual processor systems?

Why, on an amd64 system with 4 gigs of memory and MySQL ulimited as such:

         ulimit -n 4096
         ulimit -d 1572864
         ulimit -n 600
         ulimit -s 32768

do I sometimes get out of memory errors from MySQL? The total size of 
MySQL seems to grow to about 1 gig, but never any larger, and I've had to 
lower memory usage in my.cnf.

Why is my.cnf in /usr/local/ and not in /usr/local/etc/?

Does anyone have recommendations for setting up an arbitrary number of 
replication slaves easily? Experience and suggestions? What's the best way 
to benchmark two machines against each other? AMD or Intel?

Any suggestions or help would be most welcome.

Thanks,
John Klos
(Continue reading)

Andrew Doran | 5 Feb 2007 17:14
Picon

MP safe syscall changes

Hi,

I just made a bunch more syscalls MP safe on the newlock2 branch, and ran a
quick test on this machine: 4 x 700MHz P-III Xeon, 1MB L2 cache per CPU, 2GB
RAM. Cleaning out a clean source tree with make -j16 cleandir:

                real            user            system

MP, newlock2    103.55s         174.51s         246.26s
MP, HEAD        114.21s         175.46s         287.01s
UP, newlock2    198.34s         152.67s         61.30s
UP, HEAD        199.18s         150.60s         59.20s

The results aren't astounding and are not particularly accurate (system and
user time are subject to sampling error), but the indicated difference
relative to HEAD is:

                real            system

MP              -9%             -14%
UP              -0.5%           +3.5%

At a guess, part of the additional two seconds system time in the UP case is
a result of all the jumping through hoops that needs to be done to support
both locking against interrupt handlers and LWPs. With interrupts as threads
that cost can be eliminated..

Cheers,
Andrew

(Continue reading)


Gmane