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Sri Ram Vemulpali | 1 Oct 2010 23:38
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segmentation question

Hi All,

      I am developing segmentation for my kernel. In that process I
choose to divide whole memory in to fixed size segments. So a 4GB
memory can be divided in to 8192 segments. So I initialize segment
descriptors in to the GTD withs segments base address and limit. Here
base address are 0,0x10000,0x20000,..... and limit is 64kb always for
every segment. For a task if I choose a segment to assign, I will
place the index of that segment descriptor in to CS, DS. Now when
process generates address to put on address bus, then it will do
computation from logical address to linear address.
After processor picks logical address, it chooses segment descriptor
and adds this 32-bit logical address to segment base address to
generate linear address. Now my question is, if my segment size is
64kb, how is that 32-bit offset is added to segment base address,
which is not right. It should only consider 16-bit offset to add to
base to generate linear address. How can I tell to my processor to
choose only 16-bit offset. Does processor drives offset bit width
automatically based on limit defined in segment descriptor.

Any insight in to this will help me. please clarify my doubt. Waiting
for you reply.

Regards,
Sri.

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Sri.
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Daniel Baluta | 2 Oct 2010 12:06
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Re: segmentation question

Hi,

On Sat, Oct 2, 2010 at 12:38 AM, Sri Ram Vemulpali
<sri.ram.gmu06 <at> gmail.com> wrote:
> Hi All,
>
>      I am developing segmentation for my kernel. In that process I
> choose to divide whole memory in to fixed size segments. So a 4GB
> memory can be divided in to 8192 segments. So I initialize segment
> descriptors in to the GTD withs segments base address and limit. Here
> base address are 0,0x10000,0x20000,..... and limit is 64kb always for
> every segment. For a task if I choose a segment to assign, I will
> place the index of that segment descriptor in to CS, DS. Now when
> process generates address to put on address bus, then it will do
> computation from logical address to linear address.
> After processor picks logical address, it chooses segment descriptor
> and adds this 32-bit logical address to segment base address to
> generate linear address. Now my question is, if my segment size is
> 64kb, how is that 32-bit offset is added to segment base address,
> which is not right. It should only consider 16-bit offset to add to
> base to generate linear address. How can I tell to my processor to
> choose only 16-bit offset. Does processor drives offset bit width
> automatically based on limit defined in segment descriptor.

You don't have to "tell" your processor to choose only 16-bit offset.
If the offset is greater than segment limit an exception will occur.

>
> Any insight in to this will help me. please clarify my doubt. Waiting
> for you reply.
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Sri Ram Vemulpali | 2 Oct 2010 18:53
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Re: segmentation question

Also, can I modify GDT when I am managing memory allocation to tasks.
I mean a task need 120kb, but my segments are divided in to 64kb each.
So, I have to merge two segments to allocate requested memory for
task. In that case I think I need to modify GDT for a descriptor
setting limit.
Usually GDT's are initialized at boot time. But how about at the time
of memory allocation.

NOTE: I am not using any paging at all.

Here GDT means global descriptor table.

Please let me know. Thanks.
Sri.

Here are the links to how to develop kernel.
Also, read intel system programming guide, which gives very good
guidance to architecture
and OS development.

http://www.osdever.net/tutorials/view/brans-kernel-development-tutorial

On Sat, Oct 2, 2010 at 6:15 AM, Raz <raziebe <at> gmail.com> wrote:
> Can you share the code?
>
> On 02/10/2010 12:10, "Daniel Baluta" <daniel.baluta <at> gmail.com> wrote:
>
> Hi,
>
> On Sat, Oct 2, 2010 at 12:38 AM, Sri Ram Vemulpali
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Carsten Emde | 3 Oct 2010 15:56
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[PATCH 0/1] Add summary column to cyclictest histograms

Clark,

With this patch, a summary column is optionally displayed
to provide an overview of latency histograms when cyclictest
runs more than a single thread. For this purpose, the new
option -H/histofall was introduced. I am fully aware that
cyclictest does not suffer from too few options, but I did
not want to break existing scripts that rely on the number
of columns in cyclictest's output.

	Carsten.

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Carsten Emde | 3 Oct 2010 15:56
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[PATCH 1/1] cyclictest-histogram-add-summary-column.patch

To compare histograms of several SMP machines or to gain an
overview when cyclictest is running more than a single thread,
an overall histogram is required that contains a summary of
the individual thread latencies.

This patch adds this functionality and introduces the new
option -H/--histofall for this purpose.

Signed-off-by: Carsten Emde <C.Emde <at> osadl.org>

---
 src/cyclictest/cyclictest.8 |    3 ++
 src/cyclictest/cyclictest.c |   50 ++++++++++++++++++++++++++++++++++++--------
 2 files changed, 45 insertions(+), 8 deletions(-)

Index: rt-tests/src/cyclictest/cyclictest.8
===================================================================
--- rt-tests.orig/src/cyclictest/cyclictest.8
+++ rt-tests/src/cyclictest/cyclictest.8
 <at>  <at>  -93,6 +93,9  <at>  <at>  Enable function tracing using ftrace as 
 .B \-h, \-\-histogram=MAXLATENCYINUS
 Dump latency histogram to stdout. US means the max time to be be tracked in microseconds. When you use \-h
option to get histogram data, Cyclictest runs many threads with same priority without priority\-\-.
 .TP
+.B \-H, \-\-histofall=MAXLATENCYINUS
+Same as -h except that an additional histogram column is displayed at the right that contains summary data
of all thread histograms. If cyclictest runs a single thread only, the -H option is equivalent to -h.
+.TP
 .B \-i, \-\-interval=INTV
 Set the base interval of the thread(s) in microseconds (default is 1000us). This sets the interval of the
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Sven-Thorsten Dietrich | 6 Oct 2010 08:40
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RT on 2.6.34

If I read this correctly, WR ported RT to 2.6.34.

Anyone out there to confirm?

http://www.linuxfordevices.com/c/a/News/Wind-River-and-AlcatelLucent-common-platform/
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Sri Ram Vemulpali | 7 Oct 2010 00:58
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Kernel start code

Hi all,

  Can anyone, please help me on pointing to kernel boot code after
grubs loads the kernel and transfers control to it.
  I want in which files this resides, location. Any explanation on the
code or any link would be helpful to me.
  I know this is kind of lousy question, but entry.S is where I looked
at. It is overwhelming for me where to start in that file.
  Thanks in advance.

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Regards,
Sri.
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Pavan Kandepet | 7 Oct 2010 01:19
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Re: Kernel start code

Embedded Linux primer has a good introduction to
kernel bootup (chapter 5, kernel initialization). You can
try that.
Regards,
Pavan

On Wed, Oct 6, 2010 at 3:58 PM, Sri Ram Vemulpali
<sri.ram.gmu06 <at> gmail.com> wrote:
> Hi all,
>
>  Can anyone, please help me on pointing to kernel boot code after
> grubs loads the kernel and transfers control to it.
>  I want in which files this resides, location. Any explanation on the
> code or any link would be helpful to me.
>  I know this is kind of lousy question, but entry.S is where I looked
> at. It is overwhelming for me where to start in that file.
>  Thanks in advance.
>
> --
> Regards,
> Sri.
>
> --
> To unsubscribe from this list: send an email with
> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
> Please read the FAQ at http://kernelnewbies.org/FAQ
>
>
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Detlev Zundel | 7 Oct 2010 16:44
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Strange behaviour on MPC5200

Hi,

during tests with the rt-preempt kernel on PowerPC, I stumbled across
this really weird phenomenon of cyclictest latencies > 30ms.  The test
system is a TQM5200 supported mainline, so the complete kernel source is
unmodified mainline + rt-patch.  The -00001 in the kernel revision is
due to the fact that I commited the results of applying the respective
rt-patch to my local git repo.

To debug the problem, I turned the latency tracers on and started
cyclictest with 'cyclictest -n -p80'.  This looks quite good, hackbench
and the cache calibrator do not do much harm, _until_ I start to do a
ping flood from outside.  Then within a few seconds the high latencies
occur.  To test for a regression, I did the same test under
2.6.33.7-rt29 and 2.6.31.12-rt21.  Both versions yield similar results.

Attached are the trace outputs for those events (gziped as they are
larger than 300KiB).  

It looks like the scheduling goes completely wrong as there is even the
idle task running before the runnable cyclictest gets scheduled in.  Can
someone give me a hint on what may be wrong here?

Thanks
  Detlev

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walimis | 8 Oct 2010 04:07
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Re: Strange behaviour on MPC5200

On Thu, Oct 07, 2010 at 04:44:58PM +0200, Detlev Zundel wrote:
>Hi,
>
>during tests with the rt-preempt kernel on PowerPC, I stumbled across
>this really weird phenomenon of cyclictest latencies > 30ms.  The test
>system is a TQM5200 supported mainline, so the complete kernel source is
>unmodified mainline + rt-patch.  The -00001 in the kernel revision is
>due to the fact that I commited the results of applying the respective
>rt-patch to my local git repo.
>
>To debug the problem, I turned the latency tracers on and started
>cyclictest with 'cyclictest -n -p80'.  This looks quite good, hackbench
>and the cache calibrator do not do much harm, _until_ I start to do a
>ping flood from outside.  Then within a few seconds the high latencies
>occur.  To test for a regression, I did the same test under
>2.6.33.7-rt29 and 2.6.31.12-rt21.  Both versions yield similar results.
did you try mpc5121ads board with cyclictest test?                                                                                  
I wonder whether it's about powerpc arch common issue or 5200 special                                                               
issue.                                                                                                                              

Thanks                                                                                                                              
walimis
>
>Attached are the trace outputs for those events (gziped as they are
>larger than 300KiB).  
>
>It looks like the scheduling goes completely wrong as there is even the
>idle task running before the runnable cyclictest gets scheduled in.  Can
>someone give me a hint on what may be wrong here?
>
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