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Ashwith Rego | 20 May 11:29
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[free-electronic-lab] asimut: Getting a ?u in the output pattern with structural simulation

Hi,

I have the following code for an inverter:

============================
--inverter (NOT) gate
entity invg is port
(
  a   : in  bit;
  x   : out bit;
  vdd : in bit;
  vss : in bit
);
end invg;

architecture vbe of invg is begin
  x <= not (a);
end vbe;
============================

I saved this in invg.vbe Next I ran the following commands:
  boom -l 3 -d invg
  boog invg_o invg -x 1 -m 2

This resulted in the file invg.vst which contains the following:

============================
entity invg is
   port (
      a   : in      bit;
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Ashwith Rego | 19 May 19:41
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[free-electronic-lab] asimut core dumps when there is a save in the pattern file

Hi,

I was trying a structural simulation using asimut (I've attached the
files in mux.tar). The files andg.vst, org.vst and invg.vst were
generated by boog.I ran the following command:
    asimut mux mux_in mux_out

The output I got is the following:
###----- processing pattern 0 : 0 ps -----###
###----- processing pattern 1 : 0 ps -----###
###----- processing pattern 2 : 0 ps -----###
###----- processing pattern 3 : 0 ps -----###
###----- processing pattern 4 : 0 ps -----###
###----- processing pattern 5 : 0 ps -----###
###----- processing pattern 6 : 0 ps -----###
###----- processing pattern 7 : 0 ps -----###
###----- processing pattern 8 : 0 ps -----###
###----- processing pattern 9 : 0 ps -----###
###----- processing pattern 10 : 0 ps -----###
###----- processing pattern 11 : 0 ps -----###
###----- processing pattern 12 : 0 ps -----###
###----- processing pattern 13 : 0 ps -----###
###----- processing pattern 14 : 0 ps -----###
###----- processing pattern 15 : 0 ps -----###
Segmentation fault (core dumped)

I'm not sure where would be the right place to report this so I
thought I'd post it here. I also don't know where the core dump is
located or what to do with it.
I have generated a log file using the report feature in Fedora. That
(Continue reading)

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liu | 18 May 18:10
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Re: [free-electronic-lab] electronic-lab Digest, Vol 43, Issue 5

于 2012年05月18日 20:00, electronic-lab-request <at> lists.fedoraproject.org 
写道:
> gnucap and ngspice usage and feedback
the ngspice simulation of large-scale circuit is very slow.Two NE555 
circuit, the use of“ tran 10ms 10s”
Command simulation takes about 10 minutes
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Yusuf Matcheswala | 17 May 23:42
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[free-electronic-lab] gnucap and ngspice usage and feedback

If you have used gnucap and/or ngspice, what has been your experience with the usage of these tools for simulation especially of larger analog blocks regarding the tool's speed, accuracy, issues with convergence etc? I will appreciate the valuable feedback form this forum. 

Thanks,
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Ashwith Rego | 13 May 15:34
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[free-electronic-lab] Xilinx System Generator Alternative

Hi,

I have two questions.

1. Are there any alternatives to Xilinx's System generator? Possibly
something that converts octave or scilab (preferably xcos) code to
VHDL or Verilog.
2. What sort of support is available for SystemVerilog in FEL?

Thanks
Ashwith J. Rego
-----------------
My Webpage: http://ashwith.wordpress.com/
Find me on LinkedIn at: http://www.linkedin.com/in/ashwith
Follow Me on Twitter at: http://twitter.com/Louisda16th
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Shakthi Kannan | 4 May 18:30
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[free-electronic-lab] FEL added to easyfix

Hi,

I have added Fedora Electronic Lab Trac to easyfix:

  http://fedoraproject.org/easyfix/#fedora-electronic-lab

If there is a particular task/ticket that is easy for newbies to get
started with, one needs to add the word "easyfix" in the keyword
section of the ticket, and it will show up at the above URL.

Regards,

SK

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Jose Carlos Garcia Diaz | 4 May 08:39
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[free-electronic-lab] Help with installation

I have serious problems with the live-cd just blows up in intalacion and not actual mind is wrong, someone can help me

"Primero Muerto Antes de Dejar Algo Inconcluso"

Jose Carlos Garcia Diaz

My profiles:
Contact me: feliciachepe <at> gmail.com carlos.garcia.expor feliciachepe <at> hotmail.com chepecarlos <at> alswblog.org
Mis ultima aporte en ALSW(Anime y linux): Un css para vestidos gala :)
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Shakthi Kannan | 6 Apr 01:57
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[free-electronic-lab] Test: FEL F17 Nightly build

Hi,

I would appreciate if anyone could install and test the F17 Fedora
Electronic Lab nightly spin and report any issues:

  http://alt.fedoraproject.org/pub/alt/nightly-composes/

  http://koji.fedoraproject.org/koji/taskinfo?taskID=3940839

Thanks!

SK

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Shakthi Kannan | 22 Feb 07:28
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[free-electronic-lab] Tools used by EE, IITM for semiconductor device modelling

Hi,

Some of the tools required/used by EE, IIT, Madras [1] for
semiconductor device modelling:

1. Linear algebra

- gmm++  http://home.gna.org/getfem/download.html

  $ sudo yum install gmm-devel

2. Finite element libraries

- getfem++ http://download.gna.org/getfem/html/homepage/
- libmesh http://libmesh.sourceforge.net/
- deal.II  http://www.dealii.org/

  Need to be packaged. Tickets at:
  https://fedorahosted.org/fedora-electronic-lab/ticket/122
  https://fedorahosted.org/fedora-electronic-lab/ticket/123
  https://fedorahosted.org/fedora-electronic-lab/ticket/124

3. Meshing tools

- Gmsh http://geuz.org/gmsh/

  Need to be packaged. Ticket at:
  https://fedorahosted.org/fedora-electronic-lab/ticket/125

4. Visualization tools

- Paraview http://www.paraview.org/
- VisIt https://wci.llnl.gov/codes/visit/

  $ sudo yum install paraview

  VisIt needs to be packaged. Ticket is at:
  https://fedorahosted.org/fedora-electronic-lab/ticket/99

5. Drawing / Presentation

- sketch http://www.frontiernet.net/~eugene.ressler/
- ipe http://ipe7.sourceforge.net/

  $ sudo yum install sketch ipe

6. Device simulation

- Genius TCAD https://github.com/cogenda

  Need to be packaged. Ticket is at:
  https://fedorahosted.org/fedora-electronic-lab/ticket/61

SK

[1] EE, IIT, Madras. http://www.ee.iitm.ac.in/

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Free Electronic Lab | 22 Feb 07:23

[free-electronic-lab] [Free Electronic Lab] #125: Package gmsh

#125: Package gmsh
-------------------------+-----------------------
 Reporter:  shakthimaan  |       Owner:  chitlesh
     Type:  task         |      Status:  new
 Priority:  major        |   Milestone:  EPEL-6
Component:  FEL          |     Version:  devel
 Keywords:               |  Blocked By:
 Blocking:               |
-------------------------+-----------------------
 Gmsh is a 3D finite element grid generator with a build-in CAD engine and
 post-processor. Its design goal is to provide a fast, light and user-
 friendly meshing tool with parametric input and advanced visualization
 capabilities. Gmsh is built around four modules: geometry, mesh, solver
 and post-processing. The specification of any input to these modules is
 done either interactively using the graphical user interface or in ASCII
 text files using Gmsh's own scripting language.

 http://geuz.org/gmsh/

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Design, Simulate and Program electronics.
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Free Electronic Lab | 22 Feb 07:21

[free-electronic-lab] [Free Electronic Lab] #124: Package deal.II

#124: Package deal.II
-------------------------+-----------------------
 Reporter:  shakthimaan  |       Owner:  chitlesh
     Type:  task         |      Status:  new
 Priority:  major        |   Milestone:  EPEL-6
Component:  FEL          |     Version:  devel
 Keywords:               |  Blocked By:
 Blocking:               |
-------------------------+-----------------------
 deal.II is a C++ program library targeted at the computational solution of
 partial differential equations using adaptive finite elements. It uses
 state-of-the-art programming techniques to offer you a modern interface to
 the complex data structures and algorithms required.

 http://dealii.org/

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Design, Simulate and Program electronics.
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