Re: Differentiate between two e500 core (in mult-core e500)

Hi Kumar,

Thanks for the pointers. This POST will run from the
bootcode. 

I looked into the block diagram for MPC8572, and it
seems that apart from L1 caches other component are
shared (foe ex, L2, table look-up unit, gigE, SDRAM).
So, I was wondering whether we can do something like -
run _all_ the POST from core 1 and run only L1 cache
test from core 2. 

Actually I referred 'e500 core Family Ref Manual', but
could not get answer to my below question. 

Thanks,
Vinay.

--- Kumar Gala <galak <at> kernel.crashing.org> wrote:

> 
> On Jan 31, 2007, at 2:02 AM, vinay hegde wrote:
> 
> > Hi,
> >
> > Actually, what I mean is, there are two
> independent L1
> > caches (one in first e500 core and other in second
> > e500 core) in mpc8572. Now, if I am running cache
> > test(POST) on mpc8572, I must somehow make sure

MV64360 ethernet controller

Hi everyone,

I recently got a few Force/Motorola PowerPMC-280 PMC modules  
consisting mainly of a MPC7447 G4 an the Marvell MV64360 system  
controller. Since this a hobbyist project only I don't have  
Montavista Linux which seems to already support the board. Instead I  
ported the stock Linux kernel. Works quite well so far. The only  
thing I did not get to work is the integrated ethernet. The  
mv64360_eth driver loads fine and sees both ports. It does not get  
any interrupts for incoming packets (activity led blinks though).  
Only unplugging the cable generates an interrupt.

Since I do not have any documentation on the Marvell chip and the  
company does not answer my request I am quite lost.

The PHY interrupts are routed to one of the GPIO/interrupt pins. I  
did not find any code in the ethernet driver that would be able to  
use it though. Is it needed at all?

Any hint is appreciated!
Sebastian

RE: Audigy SE / ca0106 driver for PowerPC?

All,

Well I figured out part of the problem, maybe we can figure out why this was
causing an issue??

On a hunch I changed the U-boot and Blob files, to be different on one of
the addresses for the PCI IO space.

-----OLD-----
#define CFG_PCI_IO_BASE		0x00000000
#define CFG_PCI_IO_PHYS		0xF0300000
#define CFG_PCI_IO_SIZE		0x00100000 /* 1M */

-----NEW-----
#define CFG_PCI_IO_BASE		0xF0300000  <--- CHANGED THIS
#define CFG_PCI_IO_PHYS		0xF0300000
#define CFG_PCI_IO_SIZE		0x00100000 /* 1M */

The system no longer locks up now, so it looks like the bus hang is fixed.

However, now the sound driver never exits the interrupt routine. So I have
to figure out why I am getting continuous interrupts.

-Russ
-----Original Message-----
From: Kumar Gala [mailto:galak <at> kernel.crashing.org] 
Sent: Wednesday, January 31, 2007 4:04 PM
To: rmcguire <at> videopresence.com
Subject: Re: Audigy SE / ca0106 driver for PowerPC?

Re: MV64360 ethernet controller

sb <at> thebackend.de wrote:
> I recently got a few Force/Motorola PowerPMC-280 PMC modules  
> consisting mainly of a MPC7447 G4 an the Marvell MV64360 system  
> controller. Since this a hobbyist project only I don't have  
> Montavista Linux which seems to already support the board. Instead I  
> ported the stock Linux kernel. Works quite well so far. The only  
> thing I did not get to work is the integrated ethernet. The  
> mv64360_eth driver loads fine and sees both ports. It does not get  
> any interrupts for incoming packets (activity led blinks though).  
> Only unplugging the cable generates an interrupt.
> 
> Since I do not have any documentation on the Marvell chip and the  
> company does not answer my request I am quite lost.
> 
> The PHY interrupts are routed to one of the GPIO/interrupt pins. I  
> did not find any code in the ethernet driver that would be able to  
> use it though. Is it needed at all?
> 
> Any hint is appreciated!
> Sebastian

Hi Sebastian,

Yes, the driver needs receive and transmit interrupts.  However, the
same irq number is used for PHY status change as well as for packet
receive and transmit.  I don't see how you could see PHY status change
interrupts and not rx/tx interrupts.  mv643xx_eth_int_handler() should
be called for all ethernet-related interrupts*.  Are you certain that
you're not seeing rx and tx interrupts?

Profiler on PPC405 on Xilinx ML403

Dear all,
Can anyone suggest me a best profiler on ppc405 architecture with linux 
2.6, specifically on ML403 board? I need to find out the CPU consumption 
problem of the device drivers in my system. Thanks for your telling.

BR
Ming

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Re: Audigy SE / ca0106 driver for PowerPC?

On Feb 1, 2007, at 3:00 AM, Russell McGuire wrote:

> All,
>
> Well I figured out part of the problem, maybe we can figure out why  
> this was
> causing an issue??
>
> On a hunch I changed the U-boot and Blob files, to be different on  
> one of
> the addresses for the PCI IO space.
>
> -----OLD-----
> #define CFG_PCI_IO_BASE		0x00000000
> #define CFG_PCI_IO_PHYS		0xF0300000
> #define CFG_PCI_IO_SIZE		0x00100000 /* 1M */
>
> -----NEW-----
> #define CFG_PCI_IO_BASE		0xF0300000  <--- CHANGED THIS
> #define CFG_PCI_IO_PHYS		0xF0300000
> #define CFG_PCI_IO_SIZE		0x00100000 /* 1M */
>
>
> The system no longer locks up now, so it looks like the bus hang is  
> fixed.

This really boggles me, maybe the processor is doing something  
different from what I've been expecting.

8360E - PCI / DTC Blob Setup

Since I am hip deep in debugging the PCI system.

In the .dts files there is the section for the PCI setup.

The interrupt-map = < > 

Does this need to include:
1) A mapping for every IDSEL line in the system?
2) Only those IDSELs that are used on the slots on the motherboard?
3) A custom entry for every card we want to support?
4) How does a bridge chip and slave busses affect the entries, if at all?

Looking at the mpc8360 / 8349 setups that are part of the latest kernel
trees, some are place many and some are placing just a single entry?

Which should be the preferred method?

-Russ

Re: 8360E - PCI / DTC Blob Setup

On Feb 1, 2007, at 8:27 AM, Russell McGuire wrote:

> Since I am hip deep in debugging the PCI system.
>
> In the .dts files there is the section for the PCI setup.
>
> The interrupt-map = < >
>
> Does this need to include:
> 1) A mapping for every IDSEL line in the system?
> 2) Only those IDSELs that are used on the slots on the motherboard?

I'm not sure I follow the difference between 1/2. The map needs to  
cover every IDSEL that has an IRQ line wired to it.

> 3) A custom entry for every card we want to support?

See above.

> 4) How does a bridge chip and slave busses affect the entries, if  
> at all?

Uugh, I'm not sure how bridges are handled at this point.

> Looking at the mpc8360 / 8349 setups that are part of the latest  
> kernel
> trees, some are place many and some are placing just a single entry?
>
> Which should be the preferred method?

Re: Led astray? Xilinx ml410 + u-boot + Linux?

Joe,

please have a look at http://www.xilinx.com/ml410-p. The pages do 
contain information, documentation, and examples on how to use U-Boot 
and Linux 2.4 on the ML410.
There are Linux 2.6 solutions for the ML40x boards (ML403 and ML405) 
from MontaVista and Wind River. Since the ML40x boards are in key parts 
identical to the ML410 you can use those ports as a starting point for a 
port to the ML410.

- Peter

Joe wrote:
> I was told (by Xilinx reps!) that the Xilinx ML410 "supported" Linux.
>
> My goal is to have something "load" Linux and then execute it -- 
> preferably over NFS / Ethernet (for development purposes).
>
> As far as I can tell from searching the 'Net the ML403 is fairly well 
> supported but I have yet to see any level of confirmation that the 
> ML410 fully supports u-boot, Linux and Ethernet.
>
> When I download the u-boot file(s) from Xilinx they basically don't work:
>
>   0)  I get a u-boot command prompt via the serial port!! ;)
>   1)  The u-boot loadb command fails to accept any data via the kermit 
> protocol
>   2)  The u-boot 'dhcp' command fails to obtain an address -- either 
> by simply crashing or by sitting there indicating that it is re-trying 
> (in which case an Ethernet sniffer shows no activity from the Ethernet 

Re: MV64360 ethernet controller

Hi Dale,

with these files it just works. Thank you very much! 
It seems I messed up the interrupt setup. At least I learned a few  
things about the kernel and PCI as well...

But now that the CPU module does as its told I got the next problem:  
Lack of documentation for the Prodrive MCCB-3 carrier board. Always  
the same...

Sebastian

Am 01.02.2007 um 13:13 schrieb Dale Farnsworth:

> Hi Sebastian,
>
> Yes, the driver needs receive and transmit interrupts.  However, the
> same irq number is used for PHY status change as well as for packet
> receive and transmit.  I don't see how you could see PHY status change
> interrupts and not rx/tx interrupts.  mv643xx_eth_int_handler() should
> be called for all ethernet-related interrupts*.  Are you certain that
> you're not seeing rx and tx interrupts?
>
> * You may not see an interrupt on every packet because of the
> transmit irq coalescing mechanism and the use of NAPI on receive.
>
> Mark Greer and I are starting on arch/powerpc support for the mv64x60
> and ppmc280.  We will submit it as when we have something useful.
> In the meantime, the arch/ppc code below may serve as a hint.
> (Just to be clear, I didn't write this code and don't mean to take