Helge Deller | 3 Sep 22:45 2015
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[PATCH] parisc: Filter out spurious interrupts in PA-RISC irq handler

When detecting a serial port on newer PA-RISC machines (with iosapic) we have a
long way to go to find the right IRQ line, registering it, then registering the
serial port and the irq handler for the serial port. During this phase spurious
interrupts for the serial port may happen which then crashes the kernel because
the action handler might not have been set up yet.

So, basically it's a race condition between the serial port hardware and the
CPU which sets up the necessary fields in the irq sructs. The main reason for
this race is, that we unmask the serial port irqs too early without having set
up everything properly before (which isn't easily possible because we need the
IRQ number to register the serial ports).

This patch is a work-around for this problem. It adds checks to the CPU irq
handler to verify if the IRQ action field has been initialized already. If not,
we just skip this interrupt (which isn't critical for a serial port at bootup).
The real fix would probably involve rewriting all PA-RISC specific IRQ code
(for CPU, IOSAPIC, GSC and EISA) to use IRQ domains with proper parenting of
the irq chips and proper irq enabling along this line.

This bug has been in the PA-RISC port since the beginning, but the crashes
happened very rarely with currently used hardware.  But on the latest machine
which I bought (a C8000 workstation), which uses the fastest CPUs (4 x PA8900,
1GHz) and which has the largest possible L1 cache size (64MB each), the kernel
crashed at every boot because of this race. So, without this patch the machine
would currently be unuseable.

For the record, here is the flow logic:
1. serial_init_chip() in 8250_gsc.c calls iosapic_serial_irq().
2. iosapic_serial_irq() calls txn_alloc_irq() to find the irq.
3. iosapic_serial_irq() calls cpu_claim_irq() to register the CPU irq
(Continue reading)

Andreas Ziegler | 3 Sep 11:23 2015
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Re: parisc: adjust L1_CACHE_BYTES to 128 bytes on PA8800 and PA8900 CPUs

Hi Helge,

today's linux-next tree (next-20150903) contains commit 20f924902ff6
("parisc: adjust L1_CACHE_BYTES to 128 bytes on PA8800 and PA8900 CPUs")
which you authored.

I noticed it because we[0] are running a daily analysis on all commits
in linux-next as part of our research and our tools reported it.

In the patch, you create the following #if defined() structure in
arch/parisc/include/asm/cache.h (lines 16 and following):

 #if defined(CONFIG_PA8X00)
  ...
 #elif defined(CONFIG_PA20)
  ...
 #else
  ...
 #endif

In Kconfig, CONFIG_PA20 is defined as the following
(arch/parisc/Kconfig, line 163):

config PA20
  def_bool y
  depends on PA8X00

This means that CONFIG_PA20 can and will only be enabled if
CONFIG_PA8X00 has already been enabled, which means that the contents of
the "#elif defined(CONFIG_PA20)" block can never be reached: its
(Continue reading)

Helge Deller | 2 Sep 21:38 2015
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[PATCH] parisc: Align locks for LWS syscalls to L1 cache size

Align the locks for the Light weight syscall (LWS) which is used for
atomic userspace operations (e.g. gcc atomic builtins) on L1 cache
boundaries. This should speed up LWS calls on PA20 systems.

Reported-by: John David Anglin <dave.anglin <at> bell.net>
Signed-off-by: Helge Deller <deller <at> gmx.de>

diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index 7ef22e3..80c2306 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
 <at>  <at>  -561,9 +561,9  <at>  <at>  lws_compare_and_swap:
 	extru  %r26, 27, 4, %r20

 	/* Find lock to use, the hash is either one of 0 to
-	   15, multiplied by 16 (keep it 16-byte aligned)
+	   15, multiplied by L1_CACHE_BYTES (keep it L1 cache aligned)
 	   and add to the lock table offset. */
-	shlw	%r20, 4, %r20
+	shlw	%r20, L1_CACHE_SHIFT, %r20
 	add	%r20, %r28, %r20

 # if ENABLE_LWS_DEBUG
 <at>  <at>  -751,9 +751,9  <at>  <at>  cas2_lock_start:
 	extru  %r26, 27, 4, %r20

 	/* Find lock to use, the hash is either one of 0 to
-	   15, multiplied by 16 (keep it 16-byte aligned)
+	   15, multiplied by L1_CACHE_BYTES (keep it L1 cache aligned)
 	   and add to the lock table offset. */
(Continue reading)

Helge Deller | 2 Sep 18:20 2015
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[PATCH] parisc: adjust L1_CACHE_BYTES to 128 bytes on PA8800 and PA8900 CPUs

PA8800 and PA8900 processors have a cache line length of 128 bytes.

Reported-by: John David Anglin <dave.anglin <at> bell.net>
Signed-off-by: Helge Deller <deller <at> gmx.de>

diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 47f11c7..a775f60 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
 <at>  <at>  -7,17 +7,19  <at>  <at> 

 
 /*
- * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
- * 32-byte cachelines.  The default configuration is not for SMP anyway,
- * so if you're building for SMP, you should select the appropriate
- * processor type.  There is a potential livelock danger when running
- * a machine with this value set too small, but it's more probable you'll
- * just ruin performance.
+ * Most PA 2.0 processors have 64-byte cachelines, but PA8800 and PA8900
+ * processors have a cache line length of 128 bytes.
+ * PA 1.1 processors have 32-byte cachelines.
+ * There is a potential livelock danger when running a machine with this value
+ * set too small, but it's more probable you'll just ruin performance.
  */
-#ifdef CONFIG_PA20
+#if defined(CONFIG_PA8X00)
+#define L1_CACHE_BYTES 128
+#define L1_CACHE_SHIFT 7
+#elif defined(CONFIG_PA20)
(Continue reading)

Helge Deller | 2 Sep 18:18 2015
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[PATCH] parisc: additionally check for in_atomic() in page fault handler

Craig Estey noticed that we didn't checked for in_atomic() in our page fault
handler like other architectures. This commit adds this check by using
faulthandler_disabled() which includes a check for pagefault_disabled() and
in_atomic().

Reported-by: Craig Estey <cae370 <at> gmail.com>
Signed-off-by: Helge Deller <deller <at> gmx.de>

diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c
index 15503ad..ac6f174 100644
--- a/arch/parisc/mm/fault.c
+++ b/arch/parisc/mm/fault.c
 <at>  <at>  -207,7 +207,7  <at>  <at>  void do_page_fault(struct pt_regs *regs, unsigned long code,
 	int fault;
 	unsigned int flags;

-	if (pagefault_disabled())
+	if (faulthandler_disabled())
 		goto no_context;

 	tsk = current;
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Vicky | 28 Aug 14:51 2015
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1

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