Rob Clark | 18 Dec 22:16 2014
Picon

[pull] drm/msm: msm-fixes-3.19

Hi Dave,

A few msm fixes for 3.19:
 * hdmi regulators fix
 * hdmi fix for spurious HPD interrupts
 * fix for sync atomic update after async update (which could show
   up with a setcrtc following a pageflip)
 * couple little Coccinelle cleanups

The following changes since commit 4e0cd68115620bc3236ff4e58e4c073948629b41:

  drm: sti: fix module compilation issue (2014-12-15 17:07:57 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~robclark/linux msm-fixes-3.19

for you to fetch changes up to ff2f974e5c9d6b67444364605c758a9707edf1ca:

  drm/msm/hdmi: rework HDMI IRQ handler (2014-12-18 14:32:15 -0500)

----------------------------------------------------------------
Jilai Wang (2):
      drm/msm/hdmi: enable regulators before clocks to avoid warnings
      drm/msm/hdmi: rework HDMI IRQ handler

Markus Elfring (2):
      drm/msm: Deletion of unnecessary checks before two function calls
      drm/msm: Deletion of unnecessary checks before the function call
"release_firmware"
(Continue reading)

Andy Gross | 18 Dec 21:59 2014

[PATCH 0/4] pinctrl: qcom: Add multiple copy support

These patches add multiple copy support for functions which require additional
mux configurations on specific Qualcomm processor pincontrol blocks.  Functions
which may have multiple copies are slimbus, mi2s, pdm, pcie, and GSBI.

Andy Gross (4):
  pinctrl: qcom: Add multiple copy base support
  pinctrl: qcom: ipq8064: Add multi copy support
  pinctrl: qcom: apq8064: Add multi copy support
  pinctrl: qcom: msm8960: Add multi copy support

 .../bindings/pinctrl/qcom,apq8064-pinctrl.txt      |    3 +-
 .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt      |   16 +-
 .../bindings/pinctrl/qcom,msm8960-pinctrl.txt      |   19 +-
 drivers/pinctrl/qcom/pinctrl-apq8064.c             |   29 ++-
 drivers/pinctrl/qcom/pinctrl-ipq8064.c             |  244 ++++++++++++++------
 drivers/pinctrl/qcom/pinctrl-msm.c                 |   10 +
 drivers/pinctrl/qcom/pinctrl-msm.h                 |    4 +
 drivers/pinctrl/qcom/pinctrl-msm8960.c             |   32 ++-
 8 files changed, 257 insertions(+), 100 deletions(-)

--

-- 
Qualcomm Innovation Center, Inc
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Vikram Mulukutla | 18 Dec 03:50 2014

[PATCH] tracing: Fix unmapping loop in tracing_mark_write

Commit 6edb2a8a385f0cdef51dae37ff23e74d76d8a6ce introduced
an array map_pages that contains the addresses returned by
kmap_atomic. However, when unmapping those pages, map_pages[0]
is unmapped before map_pages[1], breaking the nesting requirement
as specified in the documentation for kmap_atomic/kunmap_atomic.

This was caught by the highmem debug code present in kunmap_atomic.
Fix the loop to do the unmapping properly.

Reviewed-by: Stephen Boyd <sboyd <at> codeaurora.org>
Reported-by: Lime Yang <limey <at> codeaurora.org>
Signed-off-by: Vikram Mulukutla <markivx <at> codeaurora.org>
---
 kernel/trace/trace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index ab76b7b..bceed34 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
 <at>  <at>  -4931,7 +4931,7  <at>  <at>  tracing_mark_write(struct file *filp, const char __user *ubuf,
 	*fpos += written;

  out_unlock:
-	for (i = 0; i < nr_pages; i++){
+	for (i = nr_pages - 1; i >= 0; i--) {
 		kunmap_atomic(map_page[i]);
 		put_page(pages[i]);
 	}
--

-- 
(Continue reading)

Ivan T. Ivanov | 16 Dec 11:21 2014

[PATCH] spi: qup: Add SPI_CPOL configuration support

Device support SPI_CPOL, but driver have missed to add
support for this configuration.

Signed-off-by: Ivan T. Ivanov <iivanov <at> mm-sol.com>
---
 drivers/spi/spi-qup.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 390ed71..1c3329c 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
 <at>  <at>  -337,7 +337,7  <at>  <at>  static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 {
 	struct spi_qup *controller = spi_master_get_devdata(spi->master);
-	u32 config, iomode, mode;
+	u32 config, iomode, mode, control;
 	int ret, n_words, w_size;

 	if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
 <at>  <at>  -392,6 +392,15  <at>  <at>  static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)

 	writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);

+	control = readl_relaxed(controller->base + SPI_IO_CONTROL);
+
+	if (spi->mode & SPI_CPOL)
+		control |= SPI_IO_C_CLK_IDLE_HIGH;
+	else
(Continue reading)

Stanimir Varbanov | 12 Dec 18:13 2014

[PATCH 0/5] Qualcomm PCIe and PCIe/PHY drivers

This patchset introduces a Qualcomm PCIe root complex driver for
Snapdragon 805 (APQ8084). It also adds a PCIe PHY driver in generic
phy framework. The PCIe hardware use Designware IP core plus
Qualcomm application specific hw.

The first two patches add a PHY driver binding document and the 
PHY driver. Patches 3/5 and 4/5 add PCIe DT document and the driver.
Last 5/5 adds APQ8084 in mach-qcom as next multiplatform Qualcomm
SoC.

Comments are welcome!

regards,
Stan

Stanimir Varbanov (5):
  DT: phy: qcom: Add PCIe PHY devicetree bindings
  phy: qcom: Add Qualcomm PCIe PHY
  DT: PCI: qcom: Document PCIe devicetree bindings
  PCI: qcom: Add Qualcomm PCIe controller driver
  ARM: qcom: Add Qualcomm APQ8084 SoC

 .../devicetree/bindings/pci/qcom,pcie.txt          |  159 ++++++++
 .../devicetree/bindings/phy/qcom-pcie-phy.txt      |   62 +++
 arch/arm/mach-qcom/Kconfig                         |    7 +
 drivers/pci/host/Kconfig                           |    9 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pcie-qcom.c                       |  415 ++++++++++++++++++++
 drivers/phy/Kconfig                                |    7 +
 drivers/phy/Makefile                               |    1 +
(Continue reading)

Asutosh Das | 10 Dec 07:46 2014

Re: [PATCH 4/5] mmc: cmdq: support for command queue enabled host

Hi Ziji,
Thanks for your comments.

On 12/10/2014 4:37 AM, Ziji Hu wrote:
> Hi Asutosh,
>
>           Could you check me comments please?
>
>      Please correct me if I misunderstand you.
>
>      Thank you.
>
> +irqreturn_t cmdq_irq(struct mmc_host *mmc, u32 intmask)
>
> +{
>
> +       u32 status;
>
> +       unsigned long tag = 0, comp_status;
>
> +       struct cmdq_host *cq_host = (struct cmdq_host
> *)mmc_cmdq_private(mmc);
>
> +
>
> +       spin_lock(&cq_host->cmdq_lock);
>
> +
>
> +       status = cmdq_readl(cq_host, CQIS);
(Continue reading)

Kenneth Westfield | 8 Dec 23:07 2014

Re: [PATCH 9/9] ARM: dts: Model IPQ LPASS audio hardware

On Wed, November 19, 2014 2:54 pm, Courtney Cavin wrote:
> On Wed, Nov 19, 2014 at 07:52:49PM +0100, Kenneth Westfield wrote:
>> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
>> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
>>  <at>  <at>  -2,6 +2,7  <at>  <at> 
>>  #include "skeleton.dtsi"
>>  #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
>> +#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
> Neither this file nor an associated clock controller driver exists in mainline.  Is there some
other series this depends on?
> -Courtney

This patch series has a dependency on the following patch series from linux-arm-msm: [PATCH v2
0/8] qcom audio clock control drivers
http://thread.gmane.org/gmane.linux.ports.arm.msm/10793

--

-- 
Kenneth Westfield
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,  a Linux Foundation
Collaborative Project

Kenneth Westfield | 8 Dec 23:06 2014

Re: [PATCH 3/9] ASoC: ipq806x: add native LPAIF driver

On Tue, November 25, 2014 1:44 pm, Mark Brown wrote:
> On Wed, Nov 19, 2014 at 10:52:43AM -0800, Kenneth Westfield wrote:
>> +static int lpaif_pcm_int_enable(uint8_t dma_ch)
>> +{
>> +	uint32_t intr_val;
>> +	uint32_t status_val;
>> +	unsigned long flags;
>> +
>> +	if (dma_ch >= LPAIF_MAX_CHANNELS) {
>> +		pr_err("%s: invalid DMA channel given: %hhu\n",
>> +				__func__, dma_ch);
> dev_err().

Now using it in most cases, except for two or three functions that would need to have a handle
passed to it solely for the purpose of using dev_*.

>> +	while (intrsrc) {
>> +		dma_ch = lpaif_dai_find_dma_channel(intrsrc);
>> +		if (dma_ch != -1) {
>> +			if (lpaif_dai[dma_ch]->callback) {
>> +
>> +				ret = lpaif_dai[dma_ch]->callback(intrsrc,
>> +					lpaif_dai[dma_ch]->private_data);
>> +			}
>> +			intrsrc &= ~LPAIF_PER_CH(dma_ch);
>> +		} else {
>> +			pr_err("%s: error getting channel\n", __func__);
>> +			break;
>> +		}
>> +	}
(Continue reading)

Kenneth Westfield | 8 Dec 23:01 2014

[Patch v2 00/11] ASoC: QCOM: Add support for ipq806x SOC

From: Kenneth Westfield <kwestfie <at> codeaurora.org>

This set of patches adds support for audio on the Qualcomm Technologies ipq806x SOC.

The ipq806x SOC has audio-related hardware blocks in its low-power audio subsystem (or LPASS).  One of the
relevant blocks in the LPASS is its low-power audio interface (or LPAIF).  This encapsulates the MI2S
port, which is what these drivers are configured to use.  The I2S pins are connected to an external DAC/amp
chip.  In addition, a single GPIO is connected to the same DAC/amp, which gives the SOC enable/disable control.

The specific drivers added are:
 - a Codec DAI driver that controls the SOC external pins
 - a CPU DAI driver for controlling the LPASS-LPAIF block
 - a PCM MI2S platform driver
 - a machine driver that ties the three drivers together

Corresponding additions to the device tree for the ipq806x and its documentation has also been added. 
Also, as this is a new directory, the MAINTAINERS file has been updated as well.

== Updates from my previous post:

[PATCH 00/9] ASoC: QCOM: Add support for ipq806x SOC
http://thread.gmane.org/gmane.linux.ports.arm.msm/10701

 - remove the native LPAIF driver, and move its functionality to the CPU DAI driver
 - add a codec driver to manage the pins going to the external DAC (previously managed by the machine driver)
 - use devm_* and dev_* where possible
 - ISR only handles relevant DMA channel now
 - update device tree documentation to reflect changes
 - general code cleanup

(Continue reading)

Stephane Viau | 8 Dec 16:46 2014

[PATCH] rnndb: Add registers for msm YUV support

Note:
chroma_samp_type can be used by both MDP4 and MDP5, thus
moved to mdp_common.

Signed-off-by: Stephane Viau <sviau <at> codeaurora.org>
---
 rnndb/mdp/mdp4.xml       | 16 ++++++++++++
 rnndb/mdp/mdp5.xml       | 64 +++++++++++++++++++++++++++++++++++++++++-------
 rnndb/mdp/mdp_common.xml | 13 ++++++++++
 3 files changed, 84 insertions(+), 9 deletions(-)

diff --git a/rnndb/mdp/mdp4.xml b/rnndb/mdp/mdp4.xml
index d4747e0..3d5e4df 100644
--- a/rnndb/mdp/mdp4.xml
+++ b/rnndb/mdp/mdp4.xml
 <at>  <at>  -50,6 +50,16  <at>  <at>  xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 		<value name="CURSOR_ARGB" value="1"/>
 		<value name="CURSOR_XRGB" value="2"/>
 	</enum>
+	<enum name="mdp4_frame_format">
+		<value name="FRAME_LINEAR" value="0"/>
+		<value name="FRAME_TILE_ARGB_4X4" value="1"/>
+		<value name="FRAME_TILE_YCBCR_420" value="2"/>
+	</enum>
+	<enum name="mdp4_scale_unit">
+		<value name="SCALE_FIR" value="0"/>
+		<value name="SCALE_MN_PHASE" value="1"/>
+		<value name="SCALE_PIXEL_RPT" value="2"/>
+	</enum>

(Continue reading)

Rickard Strandqvist | 7 Dec 02:16 2014
Picon

[PATCH] arch: arm: mach-msm: vreg.c: Remove unused function

Remove the function vreg_put() that is not used anywhere.

This was partially found by using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist <at> spectrumdigital.se>
---
 arch/arm/mach-msm/include/mach/vreg.h |    1 -
 arch/arm/mach-msm/vreg.c              |    4 ----
 2 files changed, 5 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/vreg.h b/arch/arm/mach-msm/include/mach/vreg.h
index 6626e78..28351ff 100644
--- a/arch/arm/mach-msm/include/mach/vreg.h
+++ b/arch/arm/mach-msm/include/mach/vreg.h
 <at>  <at>  -20,7 +20,6  <at>  <at> 
 struct vreg;

 struct vreg *vreg_get(struct device *dev, const char *id);
-void vreg_put(struct vreg *vreg);

 int vreg_enable(struct vreg *vreg);
 int vreg_disable(struct vreg *vreg);
diff --git a/arch/arm/mach-msm/vreg.c b/arch/arm/mach-msm/vreg.c
index bd66ed0..0bf891d 100644
--- a/arch/arm/mach-msm/vreg.c
+++ b/arch/arm/mach-msm/vreg.c
 <at>  <at>  -96,10 +96,6  <at>  <at>  struct vreg *vreg_get(struct device *dev, const char *id)
 	return ERR_PTR(-ENOENT);
 }

(Continue reading)


Gmane