Bjorn Andersson | 30 Aug 01:14 2014

[PATCH v2] hwspinlock/msm: Add support for Qualcomm MSM HW Mutex block

From: Kumar Gala <galak <at> codeaurora.org>

Add driver for Qualcomm MSM Hardware Mutex block that exists on
newer Qualcomm SoCs.

Cc: Jeffrey Hugo <jhugo <at> codeaurora.org>
Cc: Eric Holmberg <eholmber <at> codeaurora.org>
Cc: Courtney Cavin <courtney.cavin <at> sonymobile.com>
Signed-off-by: Kumar Gala <galak <at> codeaurora.org>
[bjorn: added pm_runtime calls, from Courtney,
	added sfpb-mutex compatible,
	updated DT binding documentation formatting]
Signed-off-by: Bjorn Andersson <bjorn.andersson <at> sonymobile.com>
---

We need this driver to add support for the shared memory manager, so I'm
reviving Kumars patch from a year ago, with some additional sprinkles on top.

Changes since v1:
 - Added the pm_runtime calls needed to be able to boot a kernel with
   pm_runtime and this driver, patch from Courtney.
 - Added sfpb-mutex compatible, for re-use of the driver in family A platforms.
 - Updated formatting of DT binding documentation, while adding the extra
   compatible.
 - Dropped Stephen Boyds Reviewed-by due to these changes.

 .../devicetree/bindings/hwlock/msm-hwspinlock.txt  |  35 +++++
 drivers/hwspinlock/Kconfig                         |  11 ++
 drivers/hwspinlock/Makefile                        |   1 +
 drivers/hwspinlock/msm_hwspinlock.c                | 155 +++++++++++++++++++++
(Continue reading)

Stephen Boyd | 29 Aug 21:49 2014

[PATCH] clk: qcom: Fix sdc 144kHz frequency entry

The pre-divider for the sdc clocks only has 2 bits in it, so we
can't possibly divide by anything larger than 4 here.
Furthermore, we program the value of ~(n - m) and the n value is
larger than 8 bits (max of 256). Replace this entry with 200kHz
which is close enough to 144kHz to be usable.

Cc: Kumar Gala <galak <at> codeaurora.org>
Cc: Andy Gross <agross <at> codeaurora.org>
Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---
 drivers/clk/qcom/gcc-ipq806x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 4032e510d9aa..3b83b7dd78c7 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
 <at>  <at>  -1095,7 +1095,7  <at>  <at>  static struct clk_branch prng_clk = {
 };

 static const struct freq_tbl clk_tbl_sdc[] = {
-	{    144000, P_PXO,   5, 18,625 },
+	{    200000, P_PXO,   2, 2, 125 },
 	{    400000, P_PLL8,  4, 1, 240 },
 	{  16000000, P_PLL8,  4, 1,   6 },
 	{  17070000, P_PLL8,  1, 2,  45 },
--

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
(Continue reading)

Pramod Gurav | 29 Aug 16:30 2014

[PATCH v3 0/4] Add reset support for apq8064

The reset on apq8064 is provided on gpio78 function1. We need to configure
gpio78 to function as ps_hold and write to base of the register to get the
device rebooted. 

First two patches in this patchset adds necessary DT support for apq8064-pinctrl
and DT support to mux gpio_78 as ps_hold function.

Third patch documents the ps_hold function in apq8064-pinctrl DT binding

Fourth implements the actual reset by initialising arm_pm_restart to a reset
function if ps_hold function is programmed in the pinctrl driver.

Changes since v2 to v3:
1. As per Bjorn's review suggestions consolidated all code which detects ps_hold function and
   initializes arm_pm_restart in a single function named msm_pinctrl_setup_pm_reset under 
   #ifdef CONFIG_ARM
2. Removed 10 second delay after carrying out reset which was copied by mistake
3. Renamed pinctl DT node to tlmm_pinumux from msm_gpio 

Changes since v1 to v2:
1. Added #error log as suggested by Kumar Gala 
2. Correct interrupts in DT from 32 to 16 based on Bjorn's new patch in bindings
3. Replaced hardcoding in DT with IRQ_TYPE_LEVEL_HIGH for interrupt level type

Pramod Gurav (4):
  ARM: DT: APQ8064: Add pinctrl support
  ARM: DT: APQ8064: Add node for ps_hold function in pinctrl
  pinctrl: msm: Add ps_hold function in pinctrl-apq8064 binding
    documentation
  pinctrl: qcom: Add support for reset for apq8064
(Continue reading)

Pramod Gurav | 29 Aug 05:22 2014

[PATCH 0/4] Add reset support for apq8064

The reset on apq8064 is provided on gpio78 function1. We need to configure
gpio78 to function as ps_hold and write to base of the register to get the
device rebooted. 

First two patches in this patchset adds necessary DT support for apq8064-pinctrl
and DT support to mux gpio_78 as ps_hold function.

Third patch documents the ps_hold function in apq8064-pinctrl DT binding

Fourth implements the actual reset by initialising arm_pm_restart to a reset
function if ps_hold function is programmed in the pinctrl driver.

This is v2 with below changes since v1:
1. Added #error log as suggested by Kumar Gala 
2. Correct interrupts in DT from 32 to 16 based on Bjorn's new patch in bindings
3. Replaced hardcoding in DT with IRQ_TYPE_LEVEL_HIGH for interrupt level type

Pramod Gurav (4):
  ARM: DT: APQ8064: Add pinctrl support
  ARM: DT: APQ8064: Add node for ps_hold function in pinctrl
  pinctrl: msm: Add ps_hold function in pinctrl-apq8064 binding
    documentation
  pinctrl: qcom: Add support for reset for apq8064

 .../bindings/pinctrl/qcom,apq8064-pinctrl.txt      |    2 +-
 arch/arm/boot/dts/qcom-apq8064.dtsi                |   21 +++++++++++
 drivers/pinctrl/qcom/pinctrl-apq8064.c             |    7 +++-
 drivers/pinctrl/qcom/pinctrl-msm.c                 |   38 ++++++++++++++++++++
 4 files changed, 66 insertions(+), 2 deletions(-)

(Continue reading)

Pramod Gurav | 28 Aug 09:00 2014

[PATCH 1/3] cpufreq: cpu0: Release clk and regulator in remove function

This function releases clk and regulator in remove function for clean
unloading.

CC: Shawn Guo <shawn.guo <at> linaro.org>
CC: "Rafael J. Wysocki" <rjw <at> rjwysocki.net>
CC: Viresh Kumar <viresh.kumar <at> linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav <at> smartplayin.com>
---
 drivers/cpufreq/cpufreq-cpu0.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
index 0d2172b..e1574f8 100644
--- a/drivers/cpufreq/cpufreq-cpu0.c
+++ b/drivers/cpufreq/cpufreq-cpu0.c
 <at>  <at>  -229,6 +229,8  <at>  <at>  static int cpu0_cpufreq_remove(struct platform_device *pdev)
 	cpufreq_cooling_unregister(cdev);
 	cpufreq_unregister_driver(&cpu0_cpufreq_driver);
 	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
+	clk_put(cpu_clk);
+	regulator_put(cpu_reg);

 	return 0;
 }
--

-- 
1.7.0.4

Pramod Gurav | 27 Aug 12:57 2014

[PATCH] pinctrl: qcom: Release pin ranges when gpiochip_irqchip_add fails

This patches adds a call to gpiochip_remove_pin_ranges when
gpiochip_irqchip_add fails to release memory allocated for pin_ranges.

CC: Ivan T. Ivanov <iivanov <at> mm-sol.com>
CC: Bjorn Andersson <bjorn.andersson <at> sonymobile.com>
CC: Linus Walleij <linus.walleij <at> linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav <at> smartplayin.com>
---
 drivers/pinctrl/qcom/pinctrl-msm.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index f4e4f8f..aa34b5a 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
 <at>  <at>  -845,6 +845,7  <at>  <at>  static int msm_gpio_init(struct msm_pinctrl *pctrl)
 				   IRQ_TYPE_NONE);
 	if (ret) {
 		dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
+		gpiochip_remove_pin_ranges(chip);
 		return -ENOSYS;
 	}

--

-- 
1.7.9.5

Pramod Gurav | 27 Aug 11:43 2014

[PATCH 3/4] pinctrl: msm: Add ps_hold function in pinctrl-apq8064 binding documentation

This adds a function ps_hold (Power Suppy Hold Signal) in pinctrl-ap8064
documentation which was missing. This function is used to reset the targets
with apq8064 soc.

CC: Linus Walleij <linus.walleij <at> linaro.org>
CC: Bjorn Andersson <bjorn.andersson <at> sonymobile.com>
CC: "Ivan T. Ivanov" <iivanov <at> mm-sol.com>
CC: Stephen Boyd <sboyd <at> codeaurora.org>
CC: Andy Gross <agross <at> codeaurora.org>

Signed-off-by: Pramod Gurav <pramod.gurav <at> smartplayin.com>
---
 .../bindings/pinctrl/qcom,apq8064-pinctrl.txt      |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
index 0211c6d..ca5bfa5 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
 <at>  <at>  -50,7 +50,7  <at>  <at>  Valid values for function are:
   gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
   gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
   gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
-  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
+  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold

 Example:

--

-- 
1.7.9.5
(Continue reading)

Pramod Gurav | 26 Aug 20:31 2014

[PATCH 1/2] ARM: DT: APQ8064: Add pinctrl support This patch adds device tree nodes to support pinctrl for apq8064 SOC

CC: Rob Herring <robh+dt <at> kernel.org>
CC: Pawel Moll <pawel.moll <at> arm.com>
CC: Mark Rutland <mark.rutland <at> arm.com>
CC: Ian Campbell <ijc+devicetree <at> hellion.org.uk>
CC: Kumar Gala <galak <at> codeaurora.org>
CC: devicetree <at> vger.kernel.org
CC: linux-arm-kernel <at> lists.infradead.org

Signed-off-by: Pramod Gurav <pramod.gurav <at> smartplayin.com>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index d66fb25..681e194 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
 <at>  <at>  -73,6 +73,17  <at>  <at> 
 		ranges;
 		compatible = "simple-bus";

+		msm_gpio: pinctrl <at> 800000 {
+			compatible = "qcom,apq8064-pinctrl";
+			reg = <0x800000 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <0 32 0x4>;
(Continue reading)

Georgi Djakov | 26 Aug 14:45 2014

[PATCH v2 0/3] pinctrl: qcom: Add APQ8084 pinctrl support

This set of patches adds pinctrl support for the Qualcomm APQ8084 platform.
The first patch adds the pin definitions. The second patch contains the
devicetree binding documentation. The last patch adds the DT node.

Tested on IFC6540 board.

Changes since v1:
 - Updated the total number of pins (suggested by Bjorn Andersson)
 - Added the missing pin info (provided by Andy Gross)
 - Updated groups and functions to be consistent with other pinctrls.
   (suggested by Andy Gross)
 - Removed unused functions, qdss and test pins. (suggested by Andy Gross)
 - Updated the documentation with the possible functions.

Georgi Djakov (3):
  pinctrl: qcom: Add APQ8084 pinctrl support
  dt: Document Qualcomm APQ8084 pinctrl binding
  ARM: dts: qcom: Add TLMM DT node for APQ8084

 .../bindings/pinctrl/qcom,apq8084-pinctrl.txt      |  104 ++
 arch/arm/boot/dts/qcom-apq8084.dtsi                |   10 +
 drivers/pinctrl/qcom/Kconfig                       |    8 +
 drivers/pinctrl/qcom/Makefile                      |    1 +
 drivers/pinctrl/qcom/pinctrl-apq8084.c             | 1243 ++++++++++++++++++++
 5 files changed, 1366 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
 create mode 100644 drivers/pinctrl/qcom/pinctrl-apq8084.c

--

-- 
1.7.9.5
(Continue reading)

Kiran Padwal | 26 Aug 13:30 2014

[PATCH v3] ARM: apq8064: Add pinmux and i2c pinctrl nodes

This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
It also adds necessary DT support for i2c eeprom which is present on
IFC6410.

Tested on IFC6410 board.

Signed-off-by: Kiran Padwal <kiran.padwal <at> smartplayin.com>
---
Changes since v2:
 - Renamed pinmux i2c subnode "i2c1_pinmux" to "i2c1".
 - Removed labes of node.
 - Used canonical value as "okay" instead of "ok".
 - Used macros.

Changes since v1:
 - Renamed pinmux phandle "qcom_pinmux" to "tlmm_pinmux".
 - Updated pinmux interrupt.

 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |   27 ++++++++++++++
 arch/arm/boot/dts/qcom-apq8064.dtsi        |   53 ++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 7c2441d..ef0857e 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
 <at>  <at>  -5,6 +5,24  <at>  <at> 
 	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";

 	soc {
(Continue reading)

Lina Iyer | 20 Aug 00:15 2014

[PATCH v4 0/8] QCOM 8074 cpuidle driver

Changes since v3:
[ https://www.mail-archive.com/linux-arm-msm <at> vger.kernel.org/msg10288.html ]
- Fix CONFIG_QCOM_PM Kconfig as bool
- More clean ups in spm.c and spm-devices.c
	- Removed and re-organized data structures to make initialization simple
	- Remove export of sequence flush functions
	- Updated commit text
	- Comments for use of barriers.
- Rebase on top of 3.17-rc1

Changes since v2:
[ https://www.mail-archive.com/linux-arm-msm <at> vger.kernel.org/msg10148.html ]
- Prune all the drivers to support basic WFI and power down cpuidle
  functionality. Remove debug code.
- Integrate KConfig changes into the drivers' patches.
- Use Lorenzo's ARM idle-states patches as the basis for reading cpuidle
  c-states from DT.
  [ http://marc.info/?l=linux-pm&m=140794514812383&w=2 ]
- Incorporate review comments
- Rebase on top of 3.16

Changes since v1/RFC:
[ https://www.mail-archive.com/linux-arm-msm <at> vger.kernel.org/msg10065.html ]
- Remove hotplug from the patch series. Will submit it seprately.
- Fix SPM drivers per the review comments
- Modify patch sequence to compile SPM drivers independent of msm-pm, so as to
  allow wfi() calls to use SPM even without SoC interface driver.

8074 like any ARM SoC can do architectural clock gating, that helps save on
power, but not enough of leakage power.  Leakage power of the SoC can be
(Continue reading)


Gmane