isabelle | 15 Apr 21:47 2014
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spende /Donation

Hallo
Wenn ich diese Nachricht zu senden wollte, ist dies nicht einfach Zufall. Dies ist, weil Ihre e-Mail vom
elektronischen Roboter gesichert meine WX.7AR BW ausgewählt wurde.
Zunächst möchte ich mich für dieses Eindringen in Ihr Leben zu entschuldigen, obwohl ich zugeben, dass
es mir sehr wichtig. Ich bin Isabelle Vasudev. Ich leide an Krebs im Hals seit nun mehr als 3 Jahre und eine
halbe und es leider, mein Arzt hat gerade informiert mich, dass ich bin voller unheilbar und, dass meine
Tage, wegen meinen etwas gezählt sind abgebaut Zustand. Ich bin eine Witwe und ich habe keine Kind, das
ich beginne zu bedauern.
In der Tat ist der Grund, warum ich Sie kontaktieren bin, möchte ich einen Teil von meinem Grundstück zu
spenden, weil ich niemand, wer die Erben konnte. Ich habe fast mein ganzes Zeug, darunter ein Unternehmen
der Export von Holz, Gummi und Stahl-Industrie in Afrika, wo ich wohne nun mehr 10 Jahren, verkauft. Ein
großer Teil der Gelder gesammelt wurde mit unterschiedlichen Verbänden humanitären Charakter
überall in der Welt, aber besonders hier in Afrika bezahlt.
Im Hinblick auf den Rest der Summe genau in Höhe von 750.000, 00euros (sieben hundert und fünfzig tausend
Euro) auf eine gesperrte Mitarbeiter-Account, meine letzte wünschen würde Sie es spenden, so dass Sie
in Ihrer Branche und vor allem den humanitären investieren können. Ich bin ganz bewusst was ich zu tun
beabsichtigen, und ich denke, trotz der Tatsache, die wir nicht wissen, werdet ihr diese Summe gut
nutzen. Ich bitte Sie, bitte dieses Erbe zu akzeptieren, ohne jedoch Fragen Sie alles, was in
zurückgeben wenn es nicht immer denken, gutes zu tun, um dich herum, was ich nicht getan habe, in meiner Existenz.
Das heißt, wird auf einer verantwortlichen Person und besonders gutem Glauben fallen zu lassen
beruhigt, ich möchte bitten, dass Sie bitte mich bei den meisten schnell kontaktieren, um weitere
Erklärung über die Gründe für meine Geste und den Verlauf der Dinge zu geben. Bitte kontaktieren Sie
mich so bald wie möglich, wenn Sie mein Angebot akzeptieren.
Gott möge mit dir sein!
Ich fordere Sie auf, mich über meine persönliche e-Mail-Adresse zu kontaktieren:
Isabelle.claude654 <at> laposte.net
Der Frieden und Barmherzigkeit Gottes möge mit dir sein.
Mrs Isabelle

(Continue reading)

Daniel Thompson | 15 Apr 12:44 2014

Change of TEXT_OFFSET for multi_v7_defconfig

Hi Folks

I've just been rebasing some of my development branches against v3.15rc1
and observed some boot regressions due to TEXT_OFFSET changing from
0x8000 to 0x208000.

Now the boot regression turned out to be fault in the JTAG boot tools I
was using (it had internally hardcoded to TEXT_OFFSET to 0x8000 when
calculating what physical load address to use). I've fixed the JTAG
loader and my own boards now boots fine.

However this did get me looking at what had causes the offset to change.
I think that as some of the Qualcomm platforms have been converted to
multi-arch then, for the first time some older code in arch/arm/Kernel
gets enabled on the multi_v7 kernels:

--- cut here ---
textofs-y       := 0x00008000
textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
# We don't want the htc bootloader to corrupt kernel during resume
textofs-$(CONFIG_PM_H1940)      := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able
memory
ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000
endif
textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
--- cut here ---
(Continue reading)

Andy Gross | 15 Apr 05:10 2014

[PATCH 0/3] pinctrl: qcom: Add IPQ8064 pinctrl support

This set of patches adds pinctrl support for the Qualcomm IPQ8064 platform.
The IPQ8064 uses the same TLMM block as the APQ8064, but has a different number
of pins, functions, and function assignments.  The second patch contains the
devicetree documentation.  The last patch selects PINCTRL for all ARCH_QCOM
platforms.  This allows for selection of pinctrl support via a make menuconfig.

Andy Gross (3):
  pinctrl: qcom: Add definitions for IPQ8064
  dt: Document Qualcomm IPQ8064 pinctrl binding
  ARM: qcom: Select PINCTRL by default for ARCH_QCOM

 .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt      |   95 +++
 arch/arm/mach-qcom/Kconfig                         |    1 +
 drivers/pinctrl/Kconfig                            |    8 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-ipq8064.c                  |  653 ++++++++++++++++++++
 5 files changed, 758 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-ipq8064.c

--

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Stanimir Varbanov | 14 Apr 14:48 2014

[RFC PATCH v2 0/9] Add Qualcomm crypto driver

Hi,

Here is the second version of the patch set. This time tagged
as an RFC to avoid confusions. The driver is splitted by files
and is buildable at the last patch. When the review has finished
1/9 to 7/9 could be squashed in one patch.

Any comments appreciated!

Changes since v1:

core
 - added MODULE_DEVICE_TABLE
 - reorganise includes
 - kernel doc comments
 - fix probe error path, forgot to destroy workqueue
 - rework clocks and kill loops for enabling
 - restructure the interfaces between core part of the driver
   and crypto type algorithms. Now struct qce_algo_ops has
   .unregister_algs operation and it is implemented by every
   algorithm type (unregister_algs was common in v1).
   Also async_req_queue/done are now part of core structure
   qce_device

regs-v5
 - use GENMASK and include bitops.h

dma-sg helpers
 - do not check !IS_ERR on error path
 - various fixes as per review comments
(Continue reading)

Saravana Kannan | 11 Apr 04:54 2014

[PATCH] PM / devfreq: Use freq_table for available_frequencies

Some devices use freq_table instead of OPP. For those devices, the
available_frequencies file shows up empty. Fix that by using freq_table to
generate the available_frequencies data when OPP is not present.

Signed-off-by: Saravana Kannan <skannan <at> codeaurora.org>
---
 drivers/devfreq/devfreq.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 2042ec3..a715d15 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
 <at>  <at>  -912,19 +912,26  <at>  <at>  static ssize_t available_frequencies_show(struct device *d,
 	struct devfreq *df = to_devfreq(d);
 	struct device *dev = df->dev.parent;
 	struct dev_pm_opp *opp;
+	unsigned int i = 0, max_state = df->profile->max_state;
+	bool use_opp;
 	ssize_t count = 0;
 	unsigned long freq = 0;

 	rcu_read_lock();
+	use_opp = dev_pm_opp_get_opp_count(dev) > 0;
 	do {
-		opp = dev_pm_opp_find_freq_ceil(dev, &freq);
-		if (IS_ERR(opp))
-			break;
+		if (use_opp) {
+			opp = dev_pm_opp_find_freq_ceil(dev, &freq);
(Continue reading)

Josh Cartwright | 11 Apr 00:17 2014

[PATCH RFC] WIP: mfd: add support for Qualcomm RPM

The Resource Power Manager (RPM) is responsible managing SoC-wide
resources (clocks, regulators, etc) on MSM and other Qualcomm SoCs.
This driver provides an implementation of the message-RAM-based
communication protocol.

Note, this is a rewrite of the driver as it exists in the downstream
tree[1], making a few simplifying assumptions to clean it up, and adding
device tree support.

[1]: https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/mach-msm/rpm.c?h=msm-3.4

Signed-off-by: Josh Cartwright <joshc <at> codeaurora.org>
---
This patch is intended to act as a starting point for discussions on how we
should proceed going forward supporting RPM.  In particular, figuring out how
to model RPM and it's controlled resources in device tree.

I've chosen a path where a subnode logically separates the RPM resources; it's
intended each set of resources will be controlled by a single driver.  For
example, an RPM-controlled regulator might consume two RPM_TYPE_REQ resources
described in 'reg'.

Effectively, this pushes the "generic resource ID" -> "SoC-specific resource
ID" mapping out of the large data tables that exist in msm-3.4 into the device
tree.  An alternative approach would be to still maintain the SoC-specific
tables, and have each node matched to it's resources using a unique compatible
string.

Any comments appreciated!

(Continue reading)

Stephen Boyd | 9 Apr 03:25 2014

[PATCH 1/2] ARM: dts: msm: Add 8921 PMIC to ssbi bus

Add the PMIC and the sub-devices that are currently supported in
the kernel to the DT.

Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---
 arch/arm/boot/dts/qcom-msm8960-cdp.dts | 16 +++++++++++++++
 arch/arm/boot/dts/qcom-msm8960.dtsi    | 37 ++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88315f6..6f61c54a653e 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
 <at>  <at>  -1,6 +1,22  <at>  <at> 
+#include <dt-bindings/input/input.h>
+
 #include "qcom-msm8960.dtsi"

 / {
 	model = "Qualcomm MSM8960 CDP";
 	compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+
+};
+
+&pmicintc {
+	keypad <at> 148 {
+		linux,keymap = <
+			MATRIX_KEY(0, 0, KEY_VOLUMEUP)
+			MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
+			MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
(Continue reading)

Stephen Boyd | 9 Apr 02:14 2014

[PATCH] mfd: pm8921: Remove pm8xxx API now that sub-devices use regmap

The pm8xxx read/write wrappers are no longer necessary now that
all the sub-device drivers are using the regmap API. Remove it.

Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---

Based on Linus' tip as of a7963eb7f4c4 (Merge branch 'for_linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs, 2014-04-07)

 drivers/mfd/pm8921-core.c       | 123 +---------------------------------------
 include/linux/mfd/pm8xxx/core.h |  81 --------------------------
 2 files changed, 2 insertions(+), 202 deletions(-)
 delete mode 100644 include/linux/mfd/pm8xxx/core.h

diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index b97a97187ae9..959513803542 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
 <at>  <at>  -26,7 +26,6  <at>  <at> 
 #include <linux/regmap.h>
 #include <linux/of_platform.h>
 #include <linux/mfd/core.h>
-#include <linux/mfd/pm8xxx/core.h>

 #define	SSBI_REG_ADDR_IRQ_BASE		0x1BB

 <at>  <at>  -57,7 +56,6  <at>  <at> 
 #define PM8921_NR_IRQS		256

 struct pm_irq_chip {
(Continue reading)

Kumar Gala | 8 Apr 17:53 2014

[PATCH v2] ARM: qcom: Add initial APQ8064 SoC and IFC6410 board device trees

Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board.

Signed-off-by: Kumar Gala <galak <at> codeaurora.org>
---
v2:
* created a v2.0 apq8064.dtsi to handle differences in Si rev in future
* changed /include/ to #include
* added PMU node
* dropped interrupts from cpus node, not currently part of binding

 arch/arm/boot/dts/Makefile                 |   1 +
 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts |  12 +++
 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi   |   1 +
 arch/arm/boot/dts/qcom-apq8064.dtsi        | 154 +++++++++++++++++++++++++++++
 arch/arm/mach-qcom/board.c                 |   1 +
 5 files changed, 169 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
 create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0591ed0..1223fa89 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
 <at>  <at>  -232,6 +232,7  <at>  <at>  dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_QCOM) += \
+	qcom-apq8064-ifc6410.dtb \
(Continue reading)

Kumar Gala | 4 Apr 22:19 2014

[PATCH v2] clk: qcom: Add support for IPQ8064's global clock controller (GCC)

Add a driver for the global clock controller found on IPQ8064 based
platforms. This should allow most non-multimedia device drivers to probe
and control their clocks.

This is currently missing clocks for SATA, USB, and networking devices.

Signed-off-by: Kumar Gala <galak <at> codeaurora.org>
---
v2:
* dropped audio clock from commit message
* changed Kconfig symbol to IPQ_GCC_806X
* Fixed PXO/CXO clk freq to 25Mhz

 .../devicetree/bindings/clock/qcom,gcc.txt         |    1 +
 drivers/clk/qcom/Kconfig                           |    8 +
 drivers/clk/qcom/Makefile                          |    1 +
 drivers/clk/qcom/gcc-ipq806x.c                     | 1957 ++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-ipq806x.h       |  297 +++
 include/dt-bindings/reset/qcom,gcc-ipq806x.h       |  124 ++
 6 files changed, 2388 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq806x.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq806x.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq806x.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 767401f..74974d6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
 <at>  <at>  -4,6 +4,7  <at>  <at>  Qualcomm Global Clock & Reset Controller Binding
 Required properties :
(Continue reading)

Stephen Boyd | 4 Apr 21:57 2014

[PATCH v6 0/5] Krait L1/L2 EDAC driver

This patchset adds support for the Krait L1/L2 cache error detection
hardware. The second patch adds the Krait L2 indirection
register code. This patch is in need of an ACK from ARM folks.
The next two patches add the driver and the binding and 
the final patch fixes up the DT nodes to match the binding (this last
one should go through the arm-soc tree).

NOTE: the DT binding patches rely on Lorenzo's cache DT binding document[1]

Changes since v5:
 * Don't rely on platform device being created from cpus node
 * Get interrupts from L1 cache node
 * Rework binding to be in cache document

Changes since v4:
 * Prefixed l2 accessors functions with krait_
 * Dropped first two patches as Boris says he picked them up

Changes since v3:
 * Fixed l1_irq handler to properly dereference dev_id

Changes since v2:
 * Picked up acks
 * s/an/a/ in DT binding

Stephen Boyd (5):
  genirq: export percpu irq functions for module usage
  ARM: Add Krait L2 register accessor functions
  devicetree: bindings: Document Krait cache error interrupts
  edac: Add support for Krait CPU cache error detection
(Continue reading)


Gmane