Kumar Gala | 27 Feb 22:29 2015

[PATCH 4/4] firmware: qcom: scm: Move the scm driver to drivers/firmware

Architectural changes in the ARM Linux kernel tree mandate the eventual
removal of the mach-* directories. Move the scm driver to
drivers/firmware and the scm header to include/linux to support that
removal.

Signed-off-by: Kumar Gala <galak <at> codeaurora.org>
---
v2:
* Moved to -M style diff output
* Added in missing include of drivers/firmware/Kconfig into arch/arm/Kconfig

 MAINTAINERS                                             | 1 +
 arch/arm/Kconfig                                        | 2 ++
 arch/arm/mach-qcom/Kconfig                              | 3 ---
 arch/arm/mach-qcom/Makefile                             | 3 ---
 arch/arm/mach-qcom/platsmp.c                            | 2 +-
 drivers/firmware/Kconfig                                | 4 ++++
 drivers/firmware/Makefile                               | 2 ++
 arch/arm/mach-qcom/scm.c => drivers/firmware/qcom_scm.c | 2 +-
 arch/arm/mach-qcom/scm.h => include/linux/qcom_scm.h    | 0
 9 files changed, 11 insertions(+), 8 deletions(-)
 rename arch/arm/mach-qcom/scm.c => drivers/firmware/qcom_scm.c (99%)
 rename arch/arm/mach-qcom/scm.h => include/linux/qcom_scm.h (100%)

diff --git a/MAINTAINERS b/MAINTAINERS
index ddc5a8c..beb8aa4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
 <at>  <at>  -1317,6 +1317,7  <at>  <at>  L:	linux-soc <at> vger.kernel.org
 S:	Maintained
(Continue reading)

Stephen Boyd | 27 Feb 04:37 2015

[PATCH] clk: qcom: Fix ipq806x LCC frequency tables

These frequency tables list the wrong rates. Either they don't
have the correct frequency at all, or they're specified in kHz
instead of Hz. Fix it.

Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Cc: Kenneth Westfield <kwestfie <at> codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---
 drivers/clk/qcom/lcc-ipq806x.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index fb276522173a..b23f8069fac1 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
 <at>  <at>  -294,14 +294,14  <at>  <at>  static struct clk_regmap_mux pcm_clk = {
 };

 static struct freq_tbl clk_tbl_aif_osr[] = {
-	{  22050, P_PLL4, 1, 147, 20480 },
-	{  32000, P_PLL4, 1,   1,    96 },
-	{  44100, P_PLL4, 1, 147, 10240 },
-	{  48000, P_PLL4, 1,   1,    64 },
-	{  88200, P_PLL4, 1, 147,  5120 },
-	{  96000, P_PLL4, 1,   1,    32 },
-	{ 176400, P_PLL4, 1, 147,  2560 },
-	{ 192000, P_PLL4, 1,   1,    16 },
+	{  2822400, P_PLL4, 1, 147, 20480 },
+	{  4096000, P_PLL4, 1,   1,    96 },
+	{  5644800, P_PLL4, 1, 147, 10240 },
(Continue reading)

Kumar Gala | 26 Feb 22:59 2015

[PATCH 1/4] ARM: qcom: Merge scm and scm boot code together

Put all scm related code into a single file as a first step in cleaning
up the scm interface to just expose functional behavior insteam of making
direct scm calls.

Signed-off-by: Kumar Gala <galak <at> codeaurora.org>
---
 arch/arm/mach-qcom/Makefile   |  2 +-
 arch/arm/mach-qcom/platsmp.c  |  2 +-
 arch/arm/mach-qcom/scm-boot.c | 39 ---------------------------------------
 arch/arm/mach-qcom/scm-boot.h | 26 --------------------------
 arch/arm/mach-qcom/scm.c      | 17 +++++++++++++++++
 arch/arm/mach-qcom/scm.h      | 11 +++++++++++
 6 files changed, 30 insertions(+), 67 deletions(-)
 delete mode 100644 arch/arm/mach-qcom/scm-boot.c
 delete mode 100644 arch/arm/mach-qcom/scm-boot.h

diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile
index 8f756ae..10b6841 100644
--- a/arch/arm/mach-qcom/Makefile
+++ b/arch/arm/mach-qcom/Makefile
 <at>  <at>  -1,5 +1,5  <at>  <at> 
 obj-y			:= board.o
 obj-$(CONFIG_SMP)	+= platsmp.o
-obj-$(CONFIG_QCOM_SCM)	+= scm.o scm-boot.o
+obj-$(CONFIG_QCOM_SCM)	+= scm.o

 CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 09cffed..8f4962e 100644
--- a/arch/arm/mach-qcom/platsmp.c
(Continue reading)

Stephen Boyd | 25 Feb 23:32 2015

[PATCH] clk: qcom: Properly change rates for ahbix clock

The ahbix clock can never be turned off. To switch the rates we
need to switch the mux off the M/N counter to an always on source
(XO), reprogram the M/N counter to get the rate we want and
finally switch back to the M/N counter. Add a new ops structure
for this type of clock so that we can set the rate properly.

Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Cc: Kenneth Westfield <kwestfie <at> codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---
 drivers/clk/qcom/clk-rcg.c     | 30 ++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-rcg.h     |  1 +
 drivers/clk/qcom/lcc-ipq806x.c |  5 +----
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 0039bd7d3965..49a1b58d4f8c 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
 <at>  <at>  -495,6 +495,27  <at>  <at>  static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
 	return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
 }

+static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long parent_rate)
+{
+	struct clk_rcg *rcg = to_clk_rcg(hw);
+	const struct freq_tbl *f;
+	int ret;
+	u32 gfm = BIT(10);
(Continue reading)

Georgi Djakov | 25 Feb 17:44 2015

[PATCH v2] clk: qcom: Add MSM8916 Global Clock Controller support

This patch adds support for the global clock controller found on the MSM8916
based devices. It allows the various device drivers to probe and control
their clocks and resets.

Signed-off-by: Georgi Djakov <georgi.djakov <at> linaro.org>
---

Changes since v1:
 * Addressed comments from Stephen Boyd and Archit Taneja
 * Fixed some incorrect offsets, parents etc.
 * Driver is tested on MSM8916-MTP device.

 .../devicetree/bindings/clock/qcom,gcc.txt         |    1 +
 drivers/clk/qcom/Kconfig                           |    8 +
 drivers/clk/qcom/Makefile                          |    1 +
 drivers/clk/qcom/gcc-msm8916.c                     | 2871 ++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8916.h       |  156 ++
 include/dt-bindings/reset/qcom,gcc-msm8916.h       |  108 +
 6 files changed, 3145 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-msm8916.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8916.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-msm8916.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index aba3d254e037..54c23f34f194 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
 <at>  <at>  -8,6 +8,7  <at>  <at>  Required properties :
 			"qcom,gcc-apq8084"
 			"qcom,gcc-ipq8064"
(Continue reading)

Kenneth Westfield | 25 Feb 07:39 2015

[Patch V6 00/10] ASoC: QCOM: Add support for ipq806x SOC

From: Kenneth Westfield <kwestfie <at> codeaurora.org>

This patch series adds support for I2S audio playback on the Storm board, which
contains a Qualcomm Technologies ipq806x SOC and a Maxim max98357a DAC/amp.

The ipq806x SOC has audio-related hardware blocks in its low-power audio
subsystem (or LPASS).  One of the relevant blocks in the LPASS is its low-power
audio interface (or LPAIF).  This contains an MI2S port, which is what these
drivers are configured to use.  The LPAIF also contains a DMA engine that is
dedicated to moving audio samples into the transmit FIFO of the MI2S port.

One bus from the MI2S port of the SOC is connected to the DAC/amp for stereo
playback.  This bus is configured so that the SOC is bus master and consists of
DATA, LRCLK, and BCLK.  The DAC/amp does not need MCLK to operate.  In addition,
a single GPIO pin from the SOC is connected to the same DAC/amp, which gives
enable/disable control over the DAC/amp.

The specific drivers added are:
  * a CPU DAI driver for controlling the MI2S port
  * a platform driver for controlling the LPAIF DMA engine
  * a machine driver that instantiates a dai-link for playback

The LPASS also contains clocks that need to be controlled.  Those drivers have
been submitted as a separate patch series:  
  [PATCH v3 0/8] qcom audio clock control drivers
  http://lkml.org/lkml/2015/1/19/656

Even though the ipq806x LPASS does not contain an audio DSP, other SOCs do have
one.  For those SOCs, the audio DSP typically controls the hardware blocks in
the LPASS.  Hence, different CPU DAI driver(s) would need to be used in order to
(Continue reading)

Bjorn Andersson | 25 Feb 04:49 2015

[PATCH v3 1/2] leds: add DT binding for Qualcomm PM8941 WLED block

From: Courtney Cavin <courtney.cavin <at> sonymobile.com>

This adds device tree binding documentation for the WLED ('White' LED)
block on Qualcomm's PM8941 PMICs.

Signed-off-by: Courtney Cavin <courtney.cavin <at> sonymobile.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson <at> sonymobile.com>
---

Changes since v2:
- None

Changes since v1:
- None

 .../devicetree/bindings/leds/leds-pm8941-wled.txt  | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/leds/leds-pm8941-wled.txt

diff --git a/Documentation/devicetree/bindings/leds/leds-pm8941-wled.txt b/Documentation/devicetree/bindings/leds/leds-pm8941-wled.txt
new file mode 100644
index 0000000..a85a964
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/leds-pm8941-wled.txt
 <at>  <at>  -0,0 +1,43  <at>  <at> 
+Binding for Qualcomm PM8941 WLED driver
+
+Required properties:
+- compatible: should be "qcom,pm8941-wled"
+- reg: slave address
(Continue reading)

Rob Clark | 24 Feb 21:33 2015
Picon

[PATCH 1/2] drm/msm/mdp5: fix cursor ROI

If cursor is set near the edge of the screen, it is not valid to use the
new cursor width/height as the ROI dimensions.  Split out the ROI calc
and use it both cursor_set and cursor_move.

Signed-off-by: Rob Clark <robdclark <at> gmail.com>
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 68 +++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 2aeae73..4c4be43 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
 <at>  <at>  -62,8 +62,8  <at>  <at>  struct mdp5_crtc {

 		/* current cursor being scanned out: */
 		struct drm_gem_object *scanout_bo;
-		uint32_t width;
-		uint32_t height;
+		uint32_t width, height;
+		uint32_t x, y;
 	} cursor;
 };
 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
 <at>  <at>  -411,6 +411,32  <at>  <at>  static int mdp5_crtc_set_property(struct drm_crtc *crtc,
 	return -EINVAL;
 }

+static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
+{
(Continue reading)

Srinivas Kandagatla | 23 Feb 08:56 2015

[PATCH 12/12] ARM: dts: apq8064 add i2c3 node for panel.

This patch adds i2c3 node which is used for panel control on IFC6410.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla <at> linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 10 ++++++++++
 arch/arm/boot/dts/qcom-apq8064.dtsi        | 25 +++++++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index ab7aee2..70fa747 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
 <at>  <at>  -20,6 +20,16  <at>  <at> 
 			};
 		};

+		gsbi3: gsbi <at> 16200000 {
+			status = "okay";
+			qcom,mode = <GSBI_PROT_I2C>;
+			i2c3: i2c <at> 16280000 {
+				status = "okay";
+				pinctrl-0 = <&i2c3_pins>;
+				pinctrl-names = "default";
+			};
+		};
+
 		gsbi <at> 12440000 {
 			status = "okay";
 			qcom,mode = <GSBI_PROT_I2C>;
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
(Continue reading)

Gilad Avidov | 19 Feb 23:54 2015

[PATCH V4 0/2] [PATCH V4 0/2] add support for pmic_arb v2 and correct framework

pmic_arb v2 has no support for spmi non-data commands and thus
returns -EOPNOTSUPP on .cmd callback. This causes a failure in
spmi_drv_probe() which sends a wakeup command to the slave before
probing its driver. This patchset removes the wakeup from
spmi_drv_probe() since the spmi spec stipulates that a slaves
default state is active and doesn't need a wakeup.

Changelog from v3 to v4:

spmi: remove wakeup command before slave probe:
1. Remove the claim that this is a bug fix off the commit text.

spmi: pmic_arb: add support for hw version 2
1. Unmap the core register space as soon as we know that it will not be used
   (on v2 it is used only to read the hw version in probe).
3. Assign the core reg space to a local until we know if it appropriate to use
   it to configure the controller fields (on v1) or unmap it (on v2).

Gilad Avidov (2):
  spmi: remove wakeup command before slave probe
  spmi: pmic_arb: add support for hw version 2

 .../bindings/spmi/qcom,spmi-pmic-arb.txt           |   6 +-
 drivers/spmi/spmi-pmic-arb.c                       | 315 +++++++++++++++++----
 drivers/spmi/spmi.c                                |   9 +-
 3 files changed, 266 insertions(+), 64 deletions(-)

--

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
(Continue reading)

Stanimir Varbanov | 19 Feb 17:45 2015

[PATCH] dmaengine: qcom_bam_dma: fix wrong register offsets

The commit fb93f520e (dmaengine: qcom_bam_dma: Generalize BAM
register offset calculations) wrongly populated base offsets
for event registers for bam v1.4.

Signed-off-by: Stanimir Varbanov <svarbanov <at> mm-sol.com>
---
 drivers/dma/qcom_bam_dma.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index debe106..95b7668 100644
--- a/drivers/dma/qcom_bam_dma.c
+++ b/drivers/dma/qcom_bam_dma.c
 <at>  <at>  -162,9 +162,9  <at>  <at>  static const struct reg_offset_data bam_v1_4_reg_info[] = {
 	[BAM_P_IRQ_STTS]	= { 0x1010, 0x1000, 0x00, 0x00 },
 	[BAM_P_IRQ_CLR]		= { 0x1014, 0x1000, 0x00, 0x00 },
 	[BAM_P_IRQ_EN]		= { 0x1018, 0x1000, 0x00, 0x00 },
-	[BAM_P_EVNT_DEST_ADDR]	= { 0x102C, 0x00, 0x1000, 0x00 },
-	[BAM_P_EVNT_REG]	= { 0x1018, 0x00, 0x1000, 0x00 },
-	[BAM_P_SW_OFSTS]	= { 0x1000, 0x00, 0x1000, 0x00 },
+	[BAM_P_EVNT_DEST_ADDR]	= { 0x182C, 0x00, 0x1000, 0x00 },
+	[BAM_P_EVNT_REG]	= { 0x1818, 0x00, 0x1000, 0x00 },
+	[BAM_P_SW_OFSTS]	= { 0x1800, 0x00, 0x1000, 0x00 },
 	[BAM_P_DATA_FIFO_ADDR]	= { 0x1824, 0x00, 0x1000, 0x00 },
 	[BAM_P_DESC_FIFO_ADDR]	= { 0x181C, 0x00, 0x1000, 0x00 },
 	[BAM_P_EVNT_GEN_TRSHLD]	= { 0x1828, 0x00, 0x1000, 0x00 },
--

-- 
1.7.0.4

(Continue reading)


Gmane