Stephen Boyd | 18 Nov 02:05 2014

[PATCH] ARM: Update processor_modes for hyp and monitor mode

If the kernel is running in hypervisor mode or monitor mode we'll
print UK6_32 or UK10_32 if we call into __show_regs(). Let's
update these strings to indicate the new modes that didn't exist
when this code was written.

Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---
 arch/arm/kernel/process.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index fe972a2f3df3..fdfa3a78ec8c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
 <at>  <at>  -51,8 +51,8  <at>  <at>  EXPORT_SYMBOL(__stack_chk_guard);
 static const char *processor_modes[] __maybe_unused = {
   "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
   "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
-  "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
-  "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
+  "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "MON_32" , "ABT_32" ,
+  "UK8_32" , "UK9_32" , "HYP_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
 };

 static const char *isa_modes[] __maybe_unused = {
--

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

(Continue reading)

Rob Clark | 16 Nov 20:38 2014
Picon

[pull] drm/msm: msm-next for 3.19

Hi Dave,

Main pull for 3.19.  I may have another pull in a few days with some
mdp5 bits (and hopefully mdp5 atomic), but I figured there was no need
to hold up what we have already.  Main highlights so far:

1) a4xx gpu support (userspace gallium bits on mesa master)
2) mdp4/hdmi/core bits for atomic helpers.  Still missing mdp5
conversion, main hold up there is current hard-coded mixer setup isn't
clever enough to deal with disabling primary plane while crtc active.
3) various other misc cleanup/fixes/etc..

The following changes since commit ca5a71de4852e3eeba53a326ddf260b7b2e117b1:

  Merge tag 'drm/gem-cma/for-3.19-rc1' of
git://people.freedesktop.org/~tagr/linux into drm-next (2014-11-15
09:50:21 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~robclark/linux msm-next

for you to fetch changes up to 23bd62fd419755b439152915f4df8ff26346f2b7:

  drm/msm: a4xx support for msm-drm (2014-11-16 14:27:40 -0500)

----------------------------------------------------------------
Aravind Ganesan (2):
      drm/msm: Handle register offset differences between a3xx and a4xx
      drm/msm: a4xx support for msm-drm
(Continue reading)

Hai Li | 14 Nov 23:42 2014

[PATCH 1/2] drm/msm: Register irq handler for each sub-system in mdss

All the sub-systems in mdss share the same irq. This change provides
the sub-systems with the interfaces to register/unregister their own
irq handlers.

With this change, struct mdp5_kms does not have to keep the hdmi or
edp context.

Signed-off-by: Hai Li <hali <at> codeaurora.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c         |  12 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 107 ++++++++++++++++++++++++++++++--
 drivers/gpu/drm/msm/msm_drv.h           |  19 +++++-
 3 files changed, 130 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 9d00dcb..aaf5e2b 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
 <at>  <at>  -39,7 +39,7  <at>  <at>  void hdmi_set_mode(struct hdmi *hdmi, bool power_on)
 			power_on ? "Enable" : "Disable", ctrl);
 }

-irqreturn_t hdmi_irq(int irq, void *dev_id)
+static irqreturn_t hdmi_irq(int irq, void *dev_id)
 {
 	struct hdmi *hdmi = dev_id;

 <at>  <at>  -59,6 +59,9  <at>  <at>  void hdmi_destroy(struct kref *kref)
 	struct hdmi *hdmi = container_of(kref, struct hdmi, refcount);
 	struct hdmi_phy *phy = hdmi->phy;
(Continue reading)

julien.parvole | 13 Nov 03:10 2014
Picon

(unknown)


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President and CEO of The Bank of Tokyo-Mitsubishi UFJ. A sum of Twenty  
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before his death in 2009.

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via this e- mail: mr.nobuyukihirano <at> foxmail.com thanks.

Sincerely,
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Bjorn Andersson | 10 Nov 23:52 2014

[RFC 0/2] Qualcomm RPM sleep states

During the review of the Qualcomm SMD RPM regulators [1], I got (offline)
feedback that my implementation did not handle "sleep states". As the problem
is shared between all families of Qualcomm platforms I use [2] (family A) to
propose a solution (as I hope to get that merged sooner).

The "sleep states" comment boils down to certain regulators (or rpm resources
in general) are used by the currently clocked/running CPU(s) and can not be
disabled while we're still running. Further more, these resources are shared
with peripherals in the system; e.g. LDO12 on PM8941 is used to clock the CPU
and WiFi/BT PLLs as well as providing power to the display in our devices. So
the suspend functionality in the regulator framework doesn't cut it.

The downstream solution to this is to expose 3 regulators per regulator
resource, each specified to control the active mode, sleep mode or both modes
respectively. Peripherals are directed to use the "both" regulator while the
CPUs are directed to the "active only" regulator.

After reviewing this solution and looking at what it's actually achieving I
here propose flagging these regulators to have "deferred disable";
* we consider the specific regulators as always-on _while running_
* hence, disable and enable affect only the sleep state
* we update both active and sleep state with all other properties

This gives us a single regulator exposed for the resource, that will be kept on
with parameters as specified by the clients if it's referenced and upon loosing
the last reference (disabling all consumers) it will be turned off when the
CPU(s) are sleeping.

As far as I can see this should give the same behaviour as we have downstream,
without the need for playing tricks with how we expose the regulators. However
(Continue reading)

Tanya Brokhman | 9 Nov 12:06 2014

[PATCH] UBI: Extend UBI layer debug/messaging capabilities - cosmetics

Some cosmetic fixes to the patch "UBI: Extend UBI layer debug/messaging
capabilities".

Signed-off-by: Tanya Brokhman <tlinder <at> codeaurora.org>
---
Changes from original patch:
	- Added ptr verification  <at>  ubi_err/ubi_msg/ubi_warn
	Removed extra printing of ubi number
	Removed new messages.

 drivers/mtd/ubi/build.c |  6 +++---
 drivers/mtd/ubi/cdev.c  |  9 ++++-----
 drivers/mtd/ubi/io.c    |  3 +--
 drivers/mtd/ubi/ubi.h   |  9 ++++++---
 drivers/mtd/ubi/vtbl.c  |  7 +++----
 drivers/mtd/ubi/wl.c    | 10 ++--------
 6 files changed, 19 insertions(+), 25 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 3405be4..ba01a8d 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
 <at>  <at>  -923,7 +923,7  <at>  <at>  int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,

 		/* Make sure ubi_num is not busy */
 		if (ubi_devices[ubi_num]) {
-			ubi_err(ubi, "ubi%d already exists", ubi_num);
+			ubi_err(ubi, "already exists");
 			return -EEXIST;
 		}
(Continue reading)

Rob Clark | 6 Nov 18:58 2014
Picon

PSA: ifc6410 / upstream kernel / clock status stuck at 'off' issues

Just FYI, newer ifc6410 boards which are shipping with android 4.4
bootloaders, seem to have an issue with upstream kernel.

If you are seeing problems like:

-------
[    2.472644] WARNING: CPU: 3 PID: 51 at
drivers/clk/qcom/clk-branch.c:97 clk_branch_wait+0xd0/0x120()
[    2.472659] mdp_clk status stuck at 'off'
[    2.472667] Modules linked in:
[    2.472688] CPU: 3 PID: 51 Comm: kworker/u8:1 Not tainted 3.18.0-rc1 #912
[    2.472719] Workqueue: deferwq deferred_probe_work_func
[    2.472784] [<c02160fc>] (unwind_backtrace) from [<c0211afc>]
(show_stack+0x10/0x14)
[    2.472824] [<c0211afc>] (show_stack) from [<c0909864>]
(dump_stack+0x88/0x98)
[    2.472859] [<c0909864>] (dump_stack) from [<c0249fa4>]
(warn_slowpath_common+0x6c/0x88)
[    2.472889] [<c0249fa4>] (warn_slowpath_common) from [<c0249ff0>]
(warn_slowpath_fmt+0x30/0x40)
[    2.472917] [<c0249ff0>] (warn_slowpath_fmt) from [<c0792964>]
(clk_branch_wait+0xd0/0x120)
[    2.472952] [<c0792964>] (clk_branch_wait) from [<c0787f78>]
(__clk_enable+0x5c/0x9c)
[    2.472975] [<c0787f78>] (__clk_enable) from [<c0788464>]
(clk_enable+0x18/0x2c)
[    2.473013] [<c0788464>] (clk_enable) from [<c054121c>]
(mdp4_enable+0xe4/0x110)
[    2.473048] [<c054121c>] (mdp4_enable) from [<c0541270>]
(mdp4_hw_init+0x28/0x344)
(Continue reading)

Ivan T. Ivanov | 4 Nov 14:33 2014

[PATCH] mfd: qcom-spmi-pmic: Add support for more chips versions

Update compatible string with runtime detected chip revision
information, for example qcom,pm8941 will become qcom,pm8941-v1.0.

Signed-off-by: Ivan T. Ivanov <iivanov <at> mm-sol.com>
---
 .../devicetree/bindings/mfd/qcom,spmi-pmic.txt     |  18 ++-
 drivers/mfd/qcom-spmi-pmic.c                       | 142 +++++++++++++++++++++
 2 files changed, 156 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
index 7182b88..bbe7db8 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
 <at>  <at>  -15,10 +15,20  <at>  <at>  each. A function can consume one or more of these fixed-size register regions.

 Required properties:
 - compatible:      Should contain one of:
-                     "qcom,pm8941"
-                     "qcom,pm8841"
-                     "qcom,pma8084"
-                     or generalized "qcom,spmi-pmic".
+                   qcom,pm8941,
+                   qcom,pm8841,
+                   qcom,pm8019,
+                   qcom,pm8226,
+                   qcom,pm8110,
+                   qcom,pma8084,
+                   qcom,pmi8962,
+                   qcom,pmd9635,
+                   qcom,pm8994,
(Continue reading)

Ivan T. Ivanov | 3 Nov 16:24 2014

[PATCH v4 0/2] Initial support for voltage ADC

Hi, 

This is the forth version of this driver. V3 could be found here [1].

Changes since v3.

- Addressed review comments from Hartmut Knaack and Mark Rutland:
  Better description of 'reg' property.
  Add # to address-cells and size-cells DT document.
  Dropped interrupt-names property, it was not actually used by driver.
  DT header file, which contain channels names definitions, is part of 
  documentation patch now.
  Clarified 'qcom,decimation' property. Hopefully it make sense now.
  Make more explicit that all reference channels configuration nodes have
  to be defined in DT.
- Promote dev_dbg to dev_err in error paths. Stan, I hope you are ok with this :-)
- Use 32 bit calculations in calibration routine.
- Read ADC result with one regmap call.
- Show status and state registers if ADC conversin fails. Errors should not
  normally happen, so I will like to see content of this registers in such cases.
- Use new struct iio_info::of_xlate for channel number translation.
- Removed device wakeup initialization code, which didn't make sense to me
  for such kind of device.

Patches depend on "iio: inkern: Add of_xlate function to struct iio_info" patch,
which is included in IIO testing branch [2].

[1] http://comments.gmane.org/gmane.linux.ports.arm.msm/9741
[2] http://git.kernel.org/cgit/linux/kernel/git/jic23/iio.git/log/?h=testing

(Continue reading)

MRS GRACE MANDA | 2 Nov 20:54 2014
Picon

(unknown)


This is Mrs Grace Manda (  Please I need your Help is Urgent). 
Attachment (Mrs Grace Manda.rtf): application/rtf, 47 KiB
Ganesan, Aravind | 31 Oct 03:33 2014

[PATCH] drm/msm: Don't split an IB at the end of ring buffer.

Splitting the command sequence for an IB1 submission at the end of
the ring buffer can hang the GPU.  To fix this, if there isn't
enough contiguous space at the end to fit the full command sequence,
insert NOPs at the end, and write the sequence at the start, as space
becomes available.

Signed-off-by: Aravind Ganesan <aravindg <at> codeaurora.org>
---
Resend in patch-set format and with dri-devel <at> lists.freedesktop.org on
the CC.
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 45
++++++++++++++++++++++++++++++---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  8 +++---
 2 files changed, 46 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 1fe7c8d..51901df 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
 <at>  <at>  -281,10 +281,49  <at>  <at>  static uint32_t ring_freewords(struct msm_gpu *gpu)
 	return (rptr + (size - 1) - wptr) % size;
 }

-void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
+void adreno_wait_ring_contiguous(struct msm_gpu *gpu,
+		uint32_t ndwords)
 {
-	if (spin_until(ring_freewords(gpu) >= ndwords))
-		DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
(Continue reading)


Gmane