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Stephen Boyd | 26 Nov 02:35 2014

[PATCH v2 0/8] qcom audio clock control drivers

This patchset adds support for the low power audio subsystem (LPASS)
clock controller hardware. I split out the #define patch for IPQ so that
it can go through the clock tree and the arm-soc tree in parallel
if desired. New in this version is the msm8960/apq8064 support.

Change since v1:
 * Renamed clk-cdiv to clk-regmap-divider
 * Added msm8960/apq8064 support
 * Split out dividers and branches to check for halt bits

Josh Cartwright (1):
  clk: qcom: Add support for regmap divider clocks

Rajendra Nayak (3):
  dt-bindings: Add #defines for IPQ806x lpass clock control
  clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver
  devicetree: bindings: Document qcom,lcc

Stephen Boyd (4):
  clk: Add __clk_mux_determine_rate_closest
  clk: divider: Make generic for usage elsewhere
  clk: qcom: Add simple regmap based muxes
  clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver

 .../devicetree/bindings/clock/qcom,lcc.txt         |  21 +
 drivers/clk/clk-divider.c                          | 195 ++++---
 drivers/clk/clk.c                                  |  47 +-
 drivers/clk/qcom/Kconfig                           |  18 +
 drivers/clk/qcom/Makefile                          |   4 +
 drivers/clk/qcom/clk-regmap-divider.c              |  70 +++
(Continue reading)

mexicans33064 | 25 Nov 18:58 2014
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Fix Penguin Penalty 17th October2014 ( mail-archive.com )

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insupportable40529 | 25 Nov 18:18 2014
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Fix Penguin Penalty 17th October2014 ( mail-archive.com )

Dear Sir

Did your website get hit by Google Penguin update on October 17th 2014? What basically is Google Penguin
Update? It is actually a code name for Google algorithm which aims at decreasing your websites search
engine rankings that violate Google’s guidelines by using black hat SEO techniques to rank your webpage
by giving number of spammy links to the page.

We are one of those few SEO companies that can help you avoid penalties from Google Updates like Penguin and
Panda. Our clients have survived all the previous and present updates with ease. They have never been hit
because we use 100% white hat SEO techniques to rank Webpages.  Simple thing that we do to keep websites away
from any Penguin or Panda penalties is follow Google guidelines and we give Google users the best answers
to their queries.

If you are looking to increase the quality of your websites and to get more targeted traffic or save your
websites from these Google penalties email us back with your interest. 

We will be glad to serve you and help you grow your business.

Regards

Julia kites

SEO Manager ( TOB )
B7 Green Avenue, Amritsar 143001 Punjab
____________________________
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Lina Iyer | 21 Nov 19:03 2014

[PATCH v10 00/10] cpuidle driver for QCOM SoCs: 8064, 8074, 8084

Changes since v9:
[ https://www.mail-archive.com/linux-arm-msm <at> vger.kernel.org/msg11714.html ]
- Address review comments on v9
Dependent patchsets - 
        https://lkml.org/lkml/2014/8/4/767
        http://www.spinics.net/lists/linux-arm-msm/msg10799.html
        http://www.spinics.net/lists/linux-arm-msm/msg10795.html

Changes since v8:
[ https://www.mail-archive.com/linux-arm-msm <at> vger.kernel.org/msg11473.html ]
- Flatten out the file structure - merge pm.c into spm.c after discussions
- Add a new function to set warm boot address, in scm-boot.c
- Support for 8064 (New)
- Tested on 8074, 8084. 8064 was tested with a WIP tree
- Address review comments from v8
- Looking into possiblility of  initializing the cpuidle device for a cpu,
only when the corresponding spm device is probed successfully.

Changes since v7:
[ https://www.mail-archive.com/linux-arm-msm <at> vger.kernel.org/msg11199.html ]
- Address review comments
- Tested on 8974 but not 8084
- WFI renamed to Standby
- Update commit text with original author and link to the downstream tree

Changes since v6:
[ https://www.mail-archive.com/linux-arm-msm <at> vger.kernel.org/msg11012.html ]
- SPM device nodes merged with existing SAW DT nodes
- SPM register information is handled within the driver
- Clean up from using 'msm' to 'qcom'
(Continue reading)

Josh Cartwright | 20 Nov 20:41 2014

[PATCH 0/3] qcom_rpm: add support for IPQ8064 resources

The IPQ8064 SoC has several Resource Power Manager (RPM) controlled resources:
four regulators (two SMB208s, each controlling two regulators) and two fabric
clocks for the Network Subsystem (NSS).  This patchset adds the appropriate
definitions for these resources, and extends the existing RPM regulator driver
to support the SMB208.

This patchset is based ontop of v7 of Bjorne Andersson's RPM patchset [1].

1: http://lkml.kernel.org/r/1411428329-23172-1-git-send-email-bjorn.andersson <at> sonymobile.com

Josh Cartwright (3):
  mfd: devicetree: qcom_rpm: document IPQ8064 resources
  mfd: qcom_rpm: add support for IPQ8064
  regulator: rpm: add support for RPM-controller SMB208

 Documentation/devicetree/bindings/mfd/qcom-rpm.txt |  6 +++-
 drivers/mfd/qcom_rpm.c                             | 41 ++++++++++++++++++++++
 drivers/regulator/qcom_rpm-regulator.c             | 19 ++++++++++
 include/dt-bindings/mfd/qcom-rpm.h                 |  6 ++++
 4 files changed, 71 insertions(+), 1 deletion(-)

--

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Hai Li | 20 Nov 00:10 2014

[PATCH 1/2] drm/msm: Initial add eDP support in msm drm driver

This change adds a new eDP connector in msm drm driver. With this
change, eDP panel can work with msm platform under drm framework.

Signed-off-by: Hai Li <hali <at> codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile            |    6 +
 drivers/gpu/drm/msm/edp/edp.c           |  211 ++++
 drivers/gpu/drm/msm/edp/edp.h           |   83 ++
 drivers/gpu/drm/msm/edp/edp_aux.c       |  298 +++++
 drivers/gpu/drm/msm/edp/edp_bridge.c    |  206 ++++
 drivers/gpu/drm/msm/edp/edp_connector.c |  155 +++
 drivers/gpu/drm/msm/edp/edp_ctrl.c      | 1799 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/msm/edp/edp_phy.c       |  123 +++
 drivers/gpu/drm/msm/edp/edp_reg.h       |   92 ++
 drivers/gpu/drm/msm/msm_drv.h           |    6 +
 10 files changed, 2979 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/edp/edp.c
 create mode 100644 drivers/gpu/drm/msm/edp/edp.h
 create mode 100644 drivers/gpu/drm/msm/edp/edp_aux.c
 create mode 100644 drivers/gpu/drm/msm/edp/edp_bridge.c
 create mode 100644 drivers/gpu/drm/msm/edp/edp_connector.c
 create mode 100644 drivers/gpu/drm/msm/edp/edp_ctrl.c
 create mode 100644 drivers/gpu/drm/msm/edp/edp_phy.c
 create mode 100644 drivers/gpu/drm/msm/edp/edp_reg.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 143d988..e5464a0 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
 <at>  <at>  -16,6 +16,12  <at>  <at>  msm-y := \
(Continue reading)

Kenneth Westfield | 19 Nov 19:52 2014

[PATCH 0/9] ASoC: QCOM: Add support for ipq806x SOC

From: Kenneth Westfield <kwestfie <at> codeaurora.org>

This set of patches adds support for audio on the Qualcomm Technologies
ipq806x SOC.

The ipq806x SOC has audio-related hardware blocks in its low-power audio
subsystem (or LPASS).  One of the relevant blocks in the LPASS is its
low-power audio interface (or LPAIF).  This encapsulates the MI2S port,
which is what these drivers are configured to use.  The I2S pins are
connected to an external DAC/amp chip.  In addition, a single GPIO is
connected to the same DAC/amp, which gives the SOC enable/disable
control.

The specific drivers added are:
 - a machine driver that handles the board-specific pins
 - a native driver that handles hardware access to the LPAIF
 - a CPU DAI driver for controlling the LPAIF block
 - a PCM MI2S platform driver

Corresponding additions to the device tree for the ipq806x and its
documentation has also been added.  Also, as this is a new directory,
the MAINTAINERS file has been updated as well.

 - Ken

Kenneth Westfield (9):
  MAINTAINERS: Add QCOM audio ASoC maintainer
  ASoC: qcom: Add device tree binding docs
  ASoC: ipq806x: add native LPAIF driver
  ASoC: ipq806x: Add LPASS CPU DAI driver
(Continue reading)

Stephen Boyd | 18 Nov 02:05 2014

[PATCH] ARM: Update processor_modes for hyp and monitor mode

If the kernel is running in hypervisor mode or monitor mode we'll
print UK6_32 or UK10_32 if we call into __show_regs(). Let's
update these strings to indicate the new modes that didn't exist
when this code was written.

Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---
 arch/arm/kernel/process.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index fe972a2f3df3..fdfa3a78ec8c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
 <at>  <at>  -51,8 +51,8  <at>  <at>  EXPORT_SYMBOL(__stack_chk_guard);
 static const char *processor_modes[] __maybe_unused = {
   "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
   "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
-  "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
-  "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
+  "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "MON_32" , "ABT_32" ,
+  "UK8_32" , "UK9_32" , "HYP_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
 };

 static const char *isa_modes[] __maybe_unused = {
--

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

(Continue reading)

Rob Clark | 16 Nov 20:38 2014
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[pull] drm/msm: msm-next for 3.19

Hi Dave,

Main pull for 3.19.  I may have another pull in a few days with some
mdp5 bits (and hopefully mdp5 atomic), but I figured there was no need
to hold up what we have already.  Main highlights so far:

1) a4xx gpu support (userspace gallium bits on mesa master)
2) mdp4/hdmi/core bits for atomic helpers.  Still missing mdp5
conversion, main hold up there is current hard-coded mixer setup isn't
clever enough to deal with disabling primary plane while crtc active.
3) various other misc cleanup/fixes/etc..

The following changes since commit ca5a71de4852e3eeba53a326ddf260b7b2e117b1:

  Merge tag 'drm/gem-cma/for-3.19-rc1' of
git://people.freedesktop.org/~tagr/linux into drm-next (2014-11-15
09:50:21 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~robclark/linux msm-next

for you to fetch changes up to 23bd62fd419755b439152915f4df8ff26346f2b7:

  drm/msm: a4xx support for msm-drm (2014-11-16 14:27:40 -0500)

----------------------------------------------------------------
Aravind Ganesan (2):
      drm/msm: Handle register offset differences between a3xx and a4xx
      drm/msm: a4xx support for msm-drm
(Continue reading)

Hai Li | 14 Nov 23:42 2014

[PATCH 1/2] drm/msm: Register irq handler for each sub-system in mdss

All the sub-systems in mdss share the same irq. This change provides
the sub-systems with the interfaces to register/unregister their own
irq handlers.

With this change, struct mdp5_kms does not have to keep the hdmi or
edp context.

Signed-off-by: Hai Li <hali <at> codeaurora.org>
---
 drivers/gpu/drm/msm/hdmi/hdmi.c         |  12 +++-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 107 ++++++++++++++++++++++++++++++--
 drivers/gpu/drm/msm/msm_drv.h           |  19 +++++-
 3 files changed, 130 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 9d00dcb..aaf5e2b 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
 <at>  <at>  -39,7 +39,7  <at>  <at>  void hdmi_set_mode(struct hdmi *hdmi, bool power_on)
 			power_on ? "Enable" : "Disable", ctrl);
 }

-irqreturn_t hdmi_irq(int irq, void *dev_id)
+static irqreturn_t hdmi_irq(int irq, void *dev_id)
 {
 	struct hdmi *hdmi = dev_id;

 <at>  <at>  -59,6 +59,9  <at>  <at>  void hdmi_destroy(struct kref *kref)
 	struct hdmi *hdmi = container_of(kref, struct hdmi, refcount);
 	struct hdmi_phy *phy = hdmi->phy;
(Continue reading)


Gmane