Ivan T. Ivanov | 21 Apr 09:11 2015

[PATCH] Revert "usb: host: ehci-msm: Use devm_ioremap_resource instead of devm_ioremap"

This reverts commit 70843f623b58 ("usb: host: ehci-msm: Use
devm_ioremap_resource instead of devm_ioremap"), because msm_otg
and this driver are using same address space to access AHB mode
and USB command registers.

Cc: Vivek Gautam <gautam.vivek <at> samsung.com>
Signed-off-by: Ivan T. Ivanov <ivan.ivanov <at> linaro.org>
---
 drivers/usb/host/ehci-msm.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 9db74ca..275c92e 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
 <at>  <at>  -88,13 +88,20  <at>  <at>  static int ehci_msm_probe(struct platform_device *pdev)
 	}

 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hcd->regs = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(hcd->regs)) {
-		ret = PTR_ERR(hcd->regs);
+	if (!res) {
+		dev_err(&pdev->dev, "Unable to get memory resource\n");
+		ret = -ENODEV;
 		goto put_hcd;
 	}
+
 	hcd->rsrc_start = res->start;
 	hcd->rsrc_len = resource_size(res);
(Continue reading)

Lina Iyer | 18 Apr 01:49 2015

[PATCH RFC 0/7] arm64: qcom: cpuidle support for MSM8916 SoC

Hi,

This patchset adds cpuidle support for the MSM8916 Qualcomm SoC.  This is based
on cpu-ops patches for the QCOM arm-v8 SoCs [1].

MSM8916 SoC is a quad-A53 SoC with an L2 configured as a single cluster. Like
many other QCOM SoC's the power management for the cpu is controlled by a
peripheral hardware block called the Subsystem Power Manager (SPM) [2]. The SPM
is a finite state machine that is triggered when the core executes the ARM WFI
instruction. SPM is configured to execute the desired idle state before
terminating the cpu in SCM. Low power modes supported are WFI and SPC (standalone
power collapse - individual cpu power down state).

The patches do the following -

- Modify ARM32 cpuidle_ops structure to match that of ARM64
- Support ARM32 and AARCH64 initialization using the same platform code
- Add 8916 specific SPM register information
- Add device bindings for 8916 SPM nodes
- Add cpuidle device bindings.

Thanks,
Lina

[1]. https://lkml.org/lkml/2015/4/9/774
[2]. http://www.spinics.net/lists/arm-kernel/msg411542.html

Lina Iyer (7):
  arm: Modify cpuidle_ops structures to match ARM64
  arm64: qcom: Add SPM driver support for ARM and ARM64
(Continue reading)

Ivan T. Ivanov | 17 Apr 16:51 2015

[PATCH] iio: adc: spmi-vadc: Fix overflow in output value normalization

With 'dx' equal to 0.625V and 15 bit ADC, calculations overflow
when difference against GND is ~20% of the ADC range. Fix this.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov <at> linaro.org>
---
 drivers/iio/adc/qcom-spmi-vadc.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
index 3211729..0c4618b 100644
--- a/drivers/iio/adc/qcom-spmi-vadc.c
+++ b/drivers/iio/adc/qcom-spmi-vadc.c
 <at>  <at>  -18,6 +18,7  <at>  <at> 
 #include <linux/iio/iio.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
+#include <linux/math64.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 <at>  <at>  -471,11 +472,11  <at>  <at>  static s32 vadc_calibrate(struct vadc_priv *vadc,
 			  const struct vadc_channel_prop *prop, u16 adc_code)
 {
 	const struct vadc_prescale_ratio *prescale;
-	s32 voltage;
+	s64 voltage;

 	voltage = adc_code - vadc->graph[prop->calibration].gnd;
 	voltage *= vadc->graph[prop->calibration].dx;
-	voltage = voltage / vadc->graph[prop->calibration].dy;
(Continue reading)

Ivan T. Ivanov | 17 Apr 16:50 2015

[PATCH] pinctrl: qcom-spmi: Fix pin direction configuration

Pin direction configuration was incorrectly overwritten
by output and function values in set_mux(). Fix this.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov <at> linaro.org>
---
 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 +
 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index e8b74c6..ae4115e 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
 <at>  <at>  -260,6 +260,7  <at>  <at>  static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 			val = 1;
 	}

+	val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
 	val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
 	val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;

diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index 8f6c7be..211b942 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
 <at>  <at>  -370,6 +370,7  <at>  <at>  static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 		}
 	}

+	val = val << PMIC_MPP_REG_MODE_DIR_SHIFT;
(Continue reading)

Hai Li | 15 Apr 22:24 2015

[PATCH 1/2] dt-bindings: Add MSM DSI controller documentation

Signed-off-by: Hai Li <hali <at> codeaurora.org>
---
 Documentation/devicetree/bindings/drm/msm/dsi.txt | 97 +++++++++++++++++++++++
 1 file changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/drm/msm/dsi.txt

diff --git a/Documentation/devicetree/bindings/drm/msm/dsi.txt b/Documentation/devicetree/bindings/drm/msm/dsi.txt
new file mode 100644
index 0000000..b3cf325
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/msm/dsi.txt
 <at>  <at>  -0,0 +1,97  <at>  <at> 
+Qualcomm Technologies Inc. adreno/snapdragon DSI output
+
+Required properties:
+- compatible:
+  * "qcom,mdss-dsi-ctrl"
+- reg: Physical base address and length of the registers of controller, PLL,
+  PHY and PHY regulator
+- reg-names: The names of register regions. The following regions are required:
+  * "dsi_ctrl"
+  * "dsi_pll"
+  * "dsi_phy"
+  * "dsi_phy_regulator"
+- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
+  be 0 or 1, since we have 2 DSI controllers at most for now.
+- interrupts: The interrupt signal from the DSI block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
(Continue reading)

Kumar Gala | 14 Apr 21:58 2015

[PATCH v3 0/3] Add smp booting support for Qualcomm ARMv8 SoCs

This patch set adds support for SMP boot on the MSM8x16 family of Qualcomm SoCs.

To support SMP on the MSM8x16 SoCs we need to add ARMv8/64-bit SCM interfaces to
setup the boot/release addresses for the secondary CPUs.  In addition we need
a uniquie set of cpu ops.  I'm aware the desired methods for booting secondary
CPUs is either via spintable or PSCI.  However, these SoCs are shipping with a
firmware that does not support those methods.

TODO:
* clean up docs related to 'qcom,arm-cortex-acc' and L2

v3:
* dropped use of pen, just release CPUs directly into secondary_start

v2:
* Dropped introduction and use of CPU_METHOD_OF_DECLARE
* Moved qcom cpu ops from drivers/soc/qcom to arch/arm64/kernel
* Renamed msm to qcom in cpu ops code, minor cleans (remove dead defines/code)

- k

--

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Gilad Broner | 14 Apr 13:51 2015

[PATCH v8 0/3] Add ioctl and debug utilities to UFS driver

Changes from V7:
Fix handling of copy_from_user() result in case of incomplete copy in ufshcd_query_ioctl().
Fix ufs-debugfs build in case UFS is configured as a loadable kernel module.

Dolev Raviv (1):
  scsi: ufs: add ioctl interface for query request

Gilad Broner (1):
  scsi: ufs: add trace events and dump prints for debug

Lee Susman (1):
  scsi: ufs: add debugfs for ufs

 drivers/scsi/ufs/Makefile      |   3 +-
 drivers/scsi/ufs/ufs-debugfs.c | 901 ++++++++++++++++++++++++++++++++++++++
 drivers/scsi/ufs/ufs-debugfs.h |  38 ++
 drivers/scsi/ufs/ufs-qcom.c    |  53 +++
 drivers/scsi/ufs/ufs.h         |  53 +--
 drivers/scsi/ufs/ufshcd.c      | 957 ++++++++++++++++++++++++++++++++++++++---
 drivers/scsi/ufs/ufshcd.h      | 110 +++++
 drivers/scsi/ufs/ufshci.h      |   3 +
 include/scsi/scsi.h            |   1 +
 include/trace/events/ufs.h     | 213 +++++++++
 include/uapi/scsi/Kbuild       |   1 +
 include/uapi/scsi/ufs/Kbuild   |   3 +
 include/uapi/scsi/ufs/ioctl.h  |  57 +++
 include/uapi/scsi/ufs/ufs.h    |  66 +++
 14 files changed, 2368 insertions(+), 91 deletions(-)
 create mode 100644 drivers/scsi/ufs/ufs-debugfs.c
 create mode 100644 drivers/scsi/ufs/ufs-debugfs.h
(Continue reading)

Bjorn Andersson | 13 Apr 23:57 2015

[PATCH 0/3] Qualcomm 8974 RPM & Regulator drivers

In 8974 Qualcomm replaced the previously used special purpose mmio
communication with SMD; a packet based point-to-point communication interface
used since the dawn of time for communicating with the modem - now used to
communicate with everything.

This series adds a smd client for the RPM as well as the regulator driver ontop
of this RPM abstraction. It depends on the pending smd patches:
 https://patchwork.kernel.org/patch/6200611/

Bjorn Andersson (3):
  mfd: devicetree: bindings: Add Qualcomm SMD based RPM DT binding
  mfd: qcom-smd-rpm: Driver for the Qualcomm RPM over SMD
  regulator: qcom: smd: Regulator driver for the Qualcomm RPM

 .../devicetree/bindings/mfd/qcom-rpm-smd.txt       | 136 ++++++++
 drivers/mfd/Kconfig                                |  14 +
 drivers/mfd/Makefile                               |   1 +
 drivers/mfd/qcom-smd-rpm.c                         | 234 ++++++++++++++
 drivers/regulator/Kconfig                          |  12 +
 drivers/regulator/Makefile                         |   1 +
 drivers/regulator/qcom_smd-regulator.c             | 351 +++++++++++++++++++++
 include/linux/mfd/qcom-smd-rpm.h                   |  35 ++
 8 files changed, 784 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/qcom-rpm-smd.txt
 create mode 100644 drivers/mfd/qcom-smd-rpm.c
 create mode 100644 drivers/regulator/qcom_smd-regulator.c
 create mode 100644 include/linux/mfd/qcom-smd-rpm.h

--

-- 
1.8.2.2
(Continue reading)

Bjorn Andersson | 12 Apr 01:32 2015

[PATCH v2 1/2] soc: qcom: Add device tree binding for SMEM

Add device tree binding documentation for the Qualcom Shared Memory
manager.

Signed-off-by: Bjorn Andersson <bjorn.andersson <at> sonymobile.com>
---

Changes since v1:
- None

 .../devicetree/bindings/soc/qcom/qcom,smem.txt     | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
new file mode 100644
index 0000000..d90f839
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt
 <at>  <at>  -0,0 +1,49  <at>  <at> 
+Qualcomm Shared Memory binding
+
+This binding describes the Qualcomm Shared Memory, used to share data between
+various subsystems and OSes in Qualcomm platforms.
+
+- compatible:
+	Usage: required
+	Value type: <stringlist>
+	Definition: must be:
+		    "qcom,smem"
+
(Continue reading)

Stephen Boyd | 11 Apr 01:11 2015

[PATCH] phy: qcom-ufs: Switch dependency to ARCH_QCOM

This phy only exists on platforms under ARCH_QCOM, not ARCH_MSM.

Cc: Yaniv Gardi <ygardi <at> codeaurora.org>
Cc: Dov Levenglick <dovl <at> codeaurora.org>
Cc: Christoph Hellwig <hch <at> lst.de>
Cc: David Brown <davidb <at> codeaurora.org>
Cc: Bryan Huntsman <bryanh <at> codeaurora.org>
Cc: Daniel Walker <dwalker <at> fifo99.com>
Signed-off-by: Stephen Boyd <sboyd <at> codeaurora.org>
---
 drivers/phy/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2962de205ba7..9b1ff313bd51 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
 <at>  <at>  -286,7 +286,7  <at>  <at>  config PHY_STIH41X_USB

 config PHY_QCOM_UFS
 	tristate "Qualcomm UFS PHY driver"
-	depends on OF && ARCH_MSM
+	depends on OF && ARCH_QCOM
 	select GENERIC_PHY
 	help
 	  Support for UFS PHY on QCOM chipsets.
--

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

(Continue reading)

Pramod Gurav | 10 Apr 14:19 2015

[PATCH v3 1/3] tty: serial: msm: Add mask value for UART_DM registers

The bit masks for RFR_LEVEL1 and STALE_TIMEOUT_MSB values in MR1 and
IPR registers respectively are different for UART and UART_DM hardware
cores. We have been using UART core mask values for these. Add the same
for UART_DM core.

There is no bit setting as UART_IPR_RXSTALE_LAST for UART_DM core so do
it only for UART core.

Signed-off-by: Pramod Gurav <gpramod <at> codeaurora.org>
---
Changes since v2:

 - Changed the sequnce of code to avoid duplication of code.

 drivers/tty/serial/msm_serial.c | 26 ++++++++++++++++++++------
 drivers/tty/serial/msm_serial.h |  2 ++
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index b73889c..99aba04 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
 <at>  <at>  -421,7 +421,7  <at>  <at>  msm_find_best_baud(struct uart_port *port, unsigned int baud)

 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
 {
-	unsigned int rxstale, watermark;
+	unsigned int rxstale, watermark, mask;
 	struct msm_port *msm_port = UART_TO_MSM(port);
 	const struct msm_baud_map *entry;
(Continue reading)


Gmane