Srinivas Kandagatla | 22 May 17:52 2015

[PATCH v4 0/3] ASoC: qcom: add support to apq8016 audio

Hi Mark, 

Thanks for applying the patches.

Am resending the leftover patches rebased on top of topic/qcom branch.
I have funtionally tested these patches on AP8016-SBC board and also
 compile tested them without CONFIG_OF on x86 to make sure nothing breaks.
All these patches are tested and Acked.

I Also included Arnd's Patch to fix Kconfig dependency on STORM board.

APQ8016 has 4 MI2S( Primary, Secondary, Tertiary, Quaternary) which can be routed
to internal wcd codec or external codecs. This routing is controlled by 2 mux

Changes since v3
 - dropped OF dependency patch
 - dropped 6 patches which are already applied by Mark.
 - fixed Kconfig as suggested by Arnd.

Changes since v2(
 - dropped 3 patches which are already applied by Mark.
 - rebased on top of topic/qcom branch.
 - changed dev_err to dev_warn spotted by Kenneth.
 - fixed typo spotted by kenneth.

Changes since v1(
 - Fixed Kconfig dependencies spotted by Kenneth
 - Fixed compilation error on ipq806x spotted by Kenneth
 - Fixed clk error messages spotted by Kenneth
(Continue reading)

Srinivas Kandagatla | 21 May 23:52 2015

[PATCH v3 00/10] ASoC: qcom: add support to apq8016 audio

Hi Mark, 

Am resending the the patches with rebased on top of topic/qcom branch.

All these patches are tested and Acked.

Thankyou for reviewing the v2 patches, here is the v3 patchset after
incorporating review comments and testing on Storm Board.
This patchset adds apq8016 audio support into lpass driver. Existing
Lpass driver can not be used as-it-is for apq8016 as it contains code
specific to ipq806x. Also the driver only supports single i2s port,
single dma channel and single bitclk control.

APQ8016 has 4 MI2S( Primary, Secondary, Tertiary, Quaternary) which can be routed
to internal wcd codec or external codecs. This routing is controlled by 2 mux

This patch series firstly re-organizes the lpass driver such that the SOC
specific bits are moved away from the driver. And secondly the SOC specifics
are now passed as lpass variant data which would include various register
offsets, dma channel allocations and SOC specific clock handling.

Finally the last few patchs add apq8016 lpass and machine driver.

All these patches are tested for HDMI audio via adv7533 bridge and Analog audio
on APQ8016-SBC, msm8916-mtp boards and Kenneth tested this patchset on
ipq806x Storm board too.

Changes since v2(
 - dropped 3 patches which are already applied by Mark.
(Continue reading)

Arnd Bergmann | 21 May 11:07 2015

[PATCH] ASoC: qcom: remove incorrect dependencies

Compile-tests show a warning for the newly added SND_SOC_STORM

warning: (SND_SOC_STORM) selects SND_SOC_LPASS_CPU which has unmet direct dependencies (SOUND &&
!M68K && !UML && SND && SND_SOC && SND_SOC_QCOM)

The problem is that it can be selected for COMPILE_TEST on non-QCOM
builds, but the symbols it selects have a dependency.
Dropping the dependencies makes it work without warnings and no
other side-effects, because these are not user-visible.

Signed-off-by: Arnd Bergmann <arnd <at>>
Fixes: f380dd3f3cd ("ASoC: qcom: Add ability to build QCOM drivers")

diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
index 5f58e4f1bca9..b07f183fc47f 100644
--- a/sound/soc/qcom/Kconfig
+++ b/sound/soc/qcom/Kconfig
 <at>  <at>  -6,12 +6,10  <at>  <at>  config SND_SOC_QCOM

-	depends on SND_SOC_QCOM
 	select REGMAP_MMIO

-	depends on SND_SOC_QCOM
 	select REGMAP_MMIO

(Continue reading)

Rob Clark | 20 May 17:15 2015

[PATCH] drm/msm/mdp4: Support NV12MT format in mdp4

Using fb modifier flag, support NV12MT format in MDP4.

- rework the modifier's description [Daniel Vetter's comment]
- drop .set_mode_config() callback [Rob Clark's comment]
- change VENDOR's name and restrict usage to NV12 [pointed by Daniel]

Signed-off-by: Rob Clark <robdclark <at>>
 drivers/gpu/drm/drm_crtc.c                | 14 ++++++++++++++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  2 ++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 22 ++++++++++++++++++++++
 include/uapi/drm/drm_fourcc.h             | 15 +++++++++++++++
 4 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3007b44..ed5d3f9 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
 <at>  <at>  -3304,6 +3304,20  <at>  <at>  static int framebuffer_check(const struct drm_mode_fb_cmd2 *r)
 				      r->modifier[i], i);
 			return -EINVAL;
+		/* modifier specific checks: */
+		switch (r->modifier[i]) {
+			if (r->pixel_format != DRM_FORMAT_NV12 ||
+					width % 128 || height % 32) {
(Continue reading)

Arnd Bergmann | 19 May 17:11 2015

[PATCH] phy: qcom-ufs: fix platform dependency

The UFS PHY driver is written for the QCOM platform, but
has an incorrect dependency pointing to the recently
removed MSM platform, causing a warning whenever it
gets selected:

warning: (SCSI_UFS_QCOM) selects PHY_QCOM_UFS which has unmet direct dependencies (OF && ARCH_MSM)

This fixes the dependency.

Signed-off-by: Arnd Bergmann <arnd <at>>
Fixes: af6f8fff446 ("ufs-qcom: Switch dependency to ARCH_QCOM")

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1b5c235562c9..c4d599976306 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
 <at>  <at>  -304,7 +304,7  <at>  <at>  config PHY_STIH41X_USB

 config PHY_QCOM_UFS
 	tristate "Qualcomm UFS PHY driver"
-	depends on OF && ARCH_MSM
+	depends on OF && ARCH_QCOM
 	select GENERIC_PHY
 	  Support for UFS PHY on QCOM chipsets.

Yaniv Gardi | 19 May 15:47 2015

[PATCH v1 0/3] fixing building errors and warnings when components

The following combination of components, when SCSI_UFS_QCOM=y
and PHY_QCOM_UFS=m is illegal and causes build errors.
The 3rd patch in the series enables the SCSI_UFS_QCOM component to 
be compiled as a module (by changing its configuration to tristate).
So now, compiling SCSI_UFS_QCOM=m forces PHY_QCOM_UFS=m, and 

In addition, when PHY_QCOM_UFS=m, external functions in 
phy-ufs-qcom.c should be exported. The 1st patch fixes it.

Another issue that we see when SCSI_UFS_QCOM=m is a warning that
the 2nd patch fixes.

checkpatch gives an error on the commit message of patch 1/3
in the series. Ignore as the commit message is the build errors
that this patch fixes.

Yaniv Gardi (3):
  phy: qcom-ufs: fix build error when the driver is built as a module
  scsi: ufs-qcom: fix compilation warning if compiled as a module
  scsi: ufs-qcom: update configuration option of SCSI_UFS_QCOM component

 drivers/phy/phy-qcom-ufs.c  | 11 +++++++++++
 drivers/scsi/ufs/Kconfig    |  2 +-
 drivers/scsi/ufs/ufs-qcom.c |  2 +-
 3 files changed, 13 insertions(+), 2 deletions(-)


(Continue reading)

Yaniv Gardi | 17 May 17:54 2015

[PATCH v1 00/10] *** introduce quirks for UFS host

This series of patches introduce additional quirks and also,
their enabling in QUALCOMM Technologies specific code.

Yaniv Gardi (10):
  scsi: ufs: introduce the capability and quirk for interrupt
  scsi: ufs-qcom: don't enable interrupt aggregation
  scsi: ufs: provide a quirk to disable the LCC
  scsi: ufs-qcom: enable UFSHCD_QUIRK_BROKEN_LCC
  scsi: ufs: introduce a broken PA_RXHSUNTERMCAP quirk
  scsi: ufs-qcom: enable quirk to fix gear change to HS
  scsi: ufs: introduce UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE quirk
  scsi: ufs-qcom: enable UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE quirk
  scsi: ufs: add quirk to handle broken UFS HCI version
  scsi: ufs-qcom: enable UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION

 drivers/scsi/ufs/ufs-qcom.c |  39 ++++++++++++++--
 drivers/scsi/ufs/ufshcd.c   | 108 ++++++++++++++++++++++++++++++++++++++++++--
 drivers/scsi/ufs/ufshcd.h   |  53 +++++++++++++++++++++-
 drivers/scsi/ufs/ufshci.h   |   8 +++-
 4 files changed, 199 insertions(+), 9 deletions(-)



QUALCOMM ISRAEL, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
Rob Clark | 15 May 20:42 2015

[pull] drm/msm: fixes for 4.1

Sorry for lagging on this a bit (been a bit distracted bring up a new
device and other things).  Here are the set of fixes for the next


The following changes since commit 332545b3016cbff066c17037d32ec8aae8e4cfb5:

  Merge tag 'drm-intel-fixes-2015-05-08' of
git:// into drm-fixes (2015-05-11
06:06:22 +1000)

are available in the git repository at:

  git:// msm-fixes-4.1

for you to fetch changes up to 774449ebcb18bae146e2b6f6d012b46e64a095b9:

  drm/msm: fix locking inconsistencies in gpu->destroy() (2015-05-15
09:28:27 -0400)

Archit Taneja (1):
      drm: msm: Fix build when legacy fbdev support isn't set

Hai Li (3):
      drm/msm/dsi: Fixup missing *break* statement during cmd rx
      drm/msm: Attach assigned encoder to eDP and DSI connectors
      drm/msm/dsi: Simplify the code to get the number of read byte
(Continue reading)

Georgi Djakov | 12 May 13:00 2015

[PATCH 1/3] clk: qcom: Add MSM8916 iommu clocks

Add support for the msm8916 TCU clocks that are needed for IOMMU.

Signed-off-by: Georgi Djakov <georgi.djakov <at>>
 drivers/clk/qcom/gcc-msm8916.c               |   78 ++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |    4 ++
 2 files changed, 82 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index c66f7bc2ae87..7ad4c3751f43 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
 <at>  <at>  -2358,6 +2358,80  <at>  <at>  static struct clk_branch gcc_sdcc2_apps_clk = {

+static const struct freq_tbl ftbl_bimc_ddr_clk[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	F(266500000, P_BIMC, 4, 0, 0),
+	F(400000000, P_GPLL0, 2, 0, 0),
+	F(533000000, P_BIMC, 2, 0, 0),
+	F(800000000, P_GPLL0, 1, 0, 0),
+	F(1066000000, P_BIMC, 1, 0, 0),
+	{ }
+static struct clk_rcg2 bimc_ddr_clk_src = {
+	.cmd_rcgr = 0x32004,
(Continue reading)

Ivan T. Ivanov | 11 May 10:31 2015

[PATCH v3] arm64: dts: qcom: Add msm8916 CoreSight components

Add initial set of CoreSight components found on Qualcomm's 8x16 chipset.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov <at>>

Changes since v2 [1]:
* Added "1x" to "qcom,coresight-replicator" compatible string, to match what
  devicetree bindings documentations says.


 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi | 254 ++++++++++++++++++++++++
 1 file changed, 254 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi

diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
new file mode 100644
index 0000000..900f1f4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
 <at>  <at>  -0,0 +1,254  <at>  <at> 
+ * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
(Continue reading)

Rob Clark | 7 May 21:49 2015

[PATCH] drm/msm: adreno a306 support

As found in apq8016 (used in DragonBoard 410c) and msm8916.

Note that numerically a306 is actually 307 (since a305c already claimed
306).  Nice and confusing.

Signed-off-by: Rob Clark <robdclark <at>>
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c      | 12 +++++++++---
 drivers/gpu/drm/msm/adreno/adreno_device.c |  8 ++++++++
 drivers/gpu/drm/msm/adreno/adreno_gpu.h    |  6 ++++++
 3 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index b66c53b..3d3db1d 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
 <at>  <at>  -93,7 +93,10  <at>  <at>  static int a3xx_hw_init(struct msm_gpu *gpu)
 		/* Set up AOOO: */
 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
+	} else if (adreno_is_a306(adreno_gpu)) {
+		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
+		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
+		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);
 	} else if (adreno_is_a320(adreno_gpu)) {
 		/* Set up 16 deep read/write request queues: */
 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
 <at>  <at>  -186,7 +189,9  <at>  <at>  static int a3xx_hw_init(struct msm_gpu *gpu)
 	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
(Continue reading)