Re: pxa2xx_spi.c : fix resume

Yes, acked.

On Mon, Apr 28, 2008 at 11:21 PM, Eric BENARD <ebenard <at> free.fr> wrote:
> Hi,
>
>  there is a typo in pxa2xx_spi.c, comment says "Enable the SSP clock",
>  code says : clk_disable ... so after resume, the SSP is dead.
>
>  --- drivers/spi/pxa2xx_spi.c~   2008-04-06 18:48:22.000000000 +0200
>  +++ drivers/spi/pxa2xx_spi.c    2008-04-28 17:18:11.000000000 +0200
>   <at>  <at>  -1562,7 +1562,7  <at>  <at> 
>         int status = 0;
>
>         /* Enable the SSP clock */
>  -       clk_disable(ssp->clk);
>  +       clk_enable(ssp->clk);
>
>         /* Start the queue running */
>         status = start_queue(drv_data);
>
>  Eric
>
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--

-- 
Cheers

Re: address constraints for dma_alloc_writecombine

Russell King - ARM Linux wrote:
> On Wed, Apr 30, 2008 at 09:11:03AM +0100, Russell King - ARM Linux wrote:
>   
>> I did have a patch which did a trial-normal-and-retry-dma approach to
>> DMA memory allocations to cover cases where it's one address bit which
>> must be zero.  I'll try to look that out today.
>>     
>
> Here's a patch - I couldn't find the original, so this is untested.
>
> diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
> index 333a82a..4f5efc0 100644
> --- a/arch/arm/mm/consistent.c
> +++ b/arch/arm/mm/consistent.c
>  <at>  <at>  -193,10 +193,12  <at>  <at>  __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
>  
>  	order = get_order(size);
>  
> -	if (mask != 0xffffffff)
> -		gfp |= GFP_DMA;
> +	do {
> +		page = alloc_pages(gfp, order);
> +		if (mask != 0xffffffff)
> +			gfp |= GFP_DMA;
> +	} while (page && page_to_dma(dev, page) & ~mask);
>  
> -	page = alloc_pages(gfp, order);
>  	if (!page)
>  		goto no_page;
>  

Re: [PATCH v2] Orion: Implement power-off method for Kurobox Pro

Lennert Buytenhek wrote:
> On Wed, Apr 30, 2008 at 08:14:58AM +0200, Sylver Bruneau wrote:
> 
>> +		*(buf+i) = orion5x_read(UART1_REG(RX));
> 
> buf[i] ?
> 
I messed up with my patch versions, It should be OK now !
Text wrapping should be fixed too !

> Please also update the MPP table comment.  I.e. change:
> 
> 	 * MPP[16-19] Not used
> 
> to something like:
> 
> 	 * MPP[16] UART1 RXD
> 	 * MPP[17] UART1 TXD
> 	 * MPP[18] UART1 CTSn
> 	 * MPP[19] UART1 RTSn
Done, thanks !

Here comes the latest revision of the patch !

This patch implements the communication with the microcontroller on the
Kurobox Pro and Linkstation Pro/Live boards. This is allowing to send
the commands needed to power-off the board correctly.

Signed-off-by: Sylver Bruneau <sylver.bruneau <at> googlemail.com>
---

Re: [PATCH 0/2] Add cpufreq support for pxa27x CPU

As asked by Eric, I'll repost the 3 patches as they are after all previous
comments.

--
Robert

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[PATCH 2/3] Prepare cpufreq for dual pxa25x/pxa27x support.

Prepared cpufreq support for pxa27x :
 - added CCLKCFG into definition tables
 - prepared multiple frequency tables

Signed-off-by: Robert Jarzmik <rjarzmik <at> free.fr>
---
 arch/arm/mach-pxa/cpu-pxa.c |  114 ++++++++++++++++++++++--------------------
 1 files changed, 60 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index 49cd665..e8734b7 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
 <at>  <at>  -54,6 +54,7  <at>  <at>  typedef struct {
 	unsigned int membus;
 	unsigned int cccr;
 	unsigned int div2;
+	unsigned int cclkcfg;
 } pxa_freqs_t;

 /* Define the refresh period in mSec for the SDRAM and the number of rows */
 <at>  <at>  -63,62 +64,77  <at>  <at>  typedef struct {

 #define CCLKCFG_TURBO		0x1
 #define CCLKCFG_FCS		0x2
-#define PXA25x_MIN_FREQ		99500
-#define PXA25x_MAX_FREQ		398100
 #define MDREFR_DB2_MASK		(MDREFR_K2DB2 | MDREFR_K1DB2)
 #define MDREFR_DRI_MASK		0xFFF

[PATCH 1/3] Indentation correction in cpu-pxa.c.

These indentation corrections prepare the pxa27x support.

Signed-off-by: Robert Jarzmik <rjarzmik <at> free.fr>
---
 arch/arm/mach-pxa/cpu-pxa.c |   94 ++++++++++++++++++++++--------------------
 1 files changed, 49 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index 4b21479..49cd665 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
 <at>  <at>  -57,29 +57,29  <at>  <at>  typedef struct {
 } pxa_freqs_t;

 /* Define the refresh period in mSec for the SDRAM and the number of rows */
-#define SDRAM_TREF          64      /* standard 64ms SDRAM */
-#define SDRAM_ROWS          4096    /* 64MB=8192 32MB=4096 */
-#define MDREFR_DRI(x)       (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
+#define SDRAM_TREF	64	/* standard 64ms SDRAM */
+#define SDRAM_ROWS	4096	/* 64MB=8192 32MB=4096 */
+#define MDREFR_DRI(x)	(((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))

-#define CCLKCFG_TURBO       0x1
-#define CCLKCFG_FCS         0x2
-#define PXA25x_MIN_FREQ     99500
-#define PXA25x_MAX_FREQ     398100
-#define MDREFR_DB2_MASK     (MDREFR_K2DB2 | MDREFR_K1DB2)
-#define MDREFR_DRI_MASK     0xFFF
+#define CCLKCFG_TURBO		0x1
+#define CCLKCFG_FCS		0x2

[PATCH 3/3] Added cpufreq support for pxa27x CPU.

Added pxa27x specific cpufreq values taken from tables in
Intel PXA27x Developers Manual.

As pointed out by  pHilipp Zabel, pxa cpus maximum frequency
depends on the cpu (624  for pxa270, 520 for pxa272, 416 for
pxa271).

The pxa27x maximum frequency should be provided on kernel or
module start (cpu-pxa.pxa27x_maxfreq parameter).

Signed-off-by: Robert Jarzmik <rjarzmik <at> free.fr>
---
 arch/arm/mach-pxa/cpu-pxa.c |  160 +++++++++++++++++++++++++++++++++++++------
 1 files changed, 138 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index e8734b7..6f9f638 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
 <at>  <at>  -49,6 +49,11  <at>  <at>  MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
 #define freq_debug  0
 #endif

+static unsigned int pxa27x_maxfreq;
+module_param(pxa27x_maxfreq, uint, 0);
+MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
+		 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
+
 typedef struct {
 	unsigned int khz;

PXA3xx Suspend/Resume.

Hello again,

I've been having great difficulty getting the suspend/resume working on 
the iPAQ 214 (PXA310).
Firstly, the iPAQ doesn't seem to use this OBM boot ROM you talk about 
in the pxa3xx.c.  It picks up the resume address from RAM+0x0800 (rather 
than RAM+0) and also requires the SRAM clock to be turned on before 
suspend. The code I've had to put into my pxa3xx.c to make it work looks 
like this:

static void pxa3xx_cpu_pm_suspend(void)
{
    volatile unsigned long *p = (volatile void *)0xc0000000;   
    unsigned long saved_data = *p;

+#ifdef CONFIG_MACH_HPIPAQ214
+    volatile unsigned long *resumePtr =  phys_to_virt(0xbc000800);
+    volatile unsigned long *resumeDataPtr = phys_to_virt(0xbc000804);
+
+    unsigned long resumeData[512];   
+#endif

    extern void pxa3xx_cpu_suspend(void);
    extern void pxa3xx_cpu_resume(void);

    /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
+#ifdef CONFIG_MACH_HPIPAQ214   
+    //ipaq boot rom deploys into SRAM, and it 'the other OS' switches 
it off
+    CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM) | (1 << CKEN_ISC);

Re: PXA3xx Suspend/Resume.

More generally, as the ROM bootstrap is always ROM dependant (depends on which
Uboot version you start from for example), each machine definition should be
able to install it's own code before going into suspend and after getting out of
suspend.

The mio a701, for instance, needs to have one word in memory to tell UBOOT that
it is resumed rather than booted for 1st time, and a bootstrap code at address
0xa000100.

All of this would lead to a common evolution for suspend/resume on pxa
architectures. I had the intention to make a RFC for that one, but your message
is a good occasion.

This is what I had done. This is _not_ a submission, it's for discussion purpose
only.

Attached also is what is done on the MIO, for a good understanding of different
resume methods. It should be noticed that the main here is that the resume
behaviour is fully ROM dependant, and thus can't be generic.

So let's that be the ground for discussion. Let's comment on that patch, and see
if a common approach could be found for all pxa.

--
Robert

Re: PXA3xx Suspend/Resume.

On Thu, May 01, 2008 at 03:01:59PM +0200, Robert Jarzmik wrote:
> 
> More generally, as the ROM bootstrap is always ROM dependant (depends on which
> Uboot version you start from for example), each machine definition should be
> able to install it's own code before going into suspend and after getting out of
> suspend.
> 
> The mio a701, for instance, needs to have one word in memory to tell UBOOT that
> it is resumed rather than booted for 1st time, and a bootstrap code at address
> 0xa000100.
> 
> All of this would lead to a common evolution for suspend/resume on pxa
> architectures. I had the intention to make a RFC for that one, but your message
> is a good occasion.
> 
> This is what I had done. This is _not_ a submission, it's for discussion purpose
> only.
> 

How about each machine installs a sysdev to handle it's own suspend/resume?

--

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

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