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linuxcdrom | 1 Jan 2003 08:05
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jffs2 familiar image doesn't work

Hello everyone:
   The following letter is from my problem,because now I have a  difficulty ,could you help and tell me your
solution for the problem .
   I running arm-linux in my hardware board with StrongArm chipset. the board functions are the same as Intel
Assabet developing board.
  Tks!
******************************************************************
Descripting my problem  as following:
******************************************************************

The following is a printout of the bootup of a compiled familiar v4 kernel.  The kernel was compiled using the
given .config file provided, after doing a cvs-rfamiliar-v0_4 checkout.
I have had this error message repeatedly, and it is really starting to get annoying, considering how many
times I've reflashed the root filesystem to see if I can fix it.  Apparently, there is a discrepancy in the
jffs2 filesystem of the root and that built in the kernel???  My friend compiled
the same kernel, and had success getting it working.Additionally, I have the altkernel partitition
freeze after the "Freeing init memory: 60k".  I'll include a boot printout of the defaulted
familiar zImage, and the partition setup, below.  Please help!This is driving me mad!!

<Compiled familiar kernel>

booting flash...
kernel_magic=E1A00000
kernel_region_words[9]=016F2818
Linux ELF flash_imgstart=50080000 size=000C0000 dest=C0000000
offset=00008000
MMU Control=C19F4071
MMU PIDVAM=00000000
copying Linux kernel ... done
linuxEntryPoint: C0008000
(Continue reading)

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SeoBongHee | 1 Jan 2003 08:34

Question about interrupt(IRQ)

Thanks Matthias Welwarsky and the mailing list
Thank you for the responses. And sorry for this direct mailing.
I posted a question about interrupt processing mechanism ,you responded.
I posted a question about CP15 register 2, you responded.
I really, really want to thank you for those.
But, unfortunately enough, I still can't understand how a hardware interrupt
is delivered to the registered isr, and what role the MMU plays in this process.
As I said several times in my previous postings, I'm not a computer science or
computer engineering major. And I'm not so smart as you guys over there.
I've just been doing computer programming as a hobby for a few years.
I wish your considerations for this fact. 

Here goes my question.

You said that the CP15 register 2 is changed at every context switch.
Then, let's assume that a process is running and a hardware interrupt
has occurred on the way. In this situation, the CP15 register 2 would
be the base address of the interrupted process's first level page descriptor table.
Am I right? 
If I am right, then how the hardware interrupt(IRQ) vector address 0x00000018(as
specified on the ARM-ARM) is translated to the appropriate physical address
where the codes that initially process the interrupt are located.
Is the CP15 register 2 changed automatically for the kernel page table
when an interrupt occurs?

What I want to know is not a detailed code-level description.
I just want the principle. What logical faults do I have in my understandings of
or view point for this problem? What stuffs am I miscomprehending?
A step by step explanation of the process of interrupt delivery, from
the onset to the destined isr and the roles played by the MMU(s) in this
(Continue reading)

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Russell King - ARM Linux | 1 Jan 2003 10:51
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Re: DMA buffer access

On Mon, Dec 02, 2002 at 12:16:35PM +0000, dqi <at> freenet.co.uk wrote:
> I used the following line to get access to a piece of memory from the
> driver. My question is how can I convert it back to the physical or
> bus address? e.g. how can I convert a virtual memory range in the
> 0x280000000 to 0x28100000 back to a bus address?
> 
> dmabuff = ioremap(0x28000000, 0x100000);
> 
> virt_to_bus() seems doesn't work in this case, at leat for ARM
> Integrator/AP.

virt_to_bus() is deprecated; it never works on the result of ioremap.
In addition, it is no longer in 2.5 kernels.

There is no linear relationship between the ioremap return value and
the value you pass in.  You must keep the original value so you can
perform the calculation you require.

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Matthias Welwarsky | 1 Jan 2003 13:32
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Re: Thanks for the responses and another question(interrupt, virtual address...)

On Tuesday 31 December 2002 16:42, you wrote:
> Hi, Matthias Welwarsky.
> Thank you for the responses. And sorry for this direct mailing.
> I posted a question about interrupt processing mechanism ,you responded.
> I posted a question about CP15 register 2, you responded.
> I really, really want to thank you for those.

That's no problem. If I've got the time, I usually answer questions from the 
mailing list quickly.

> Here goes my question.
>
> You said that the CP15 register 2 is changed at every context switch.
> Then, let's assume that a process is running and a hardware interrupt
> has occurred on the way. In this situation, the CP15 register 2 would
> be the base address of the interrupted process's first level page
> descriptor table. Am I right?

Yes, that's correct.

> If I am right, then how the hardware interrupt(IRQ) vector address
> 0x00000018(as specified on the ARM-ARM) is translated to the appropriate
> physical address where the codes that initially process the interrupt are
> located.

Well, I cannot explain the translation process in detail, I haven't groked 
this fully, too, but it's quite straight forward. The CPU itself does not 
know anything about the MMU. The CPU's view on the address space is fully 
"virtual". The CPU knows: If an interrupt occours, jump to 0x00000018 (or 
0xffff0018) and save the content of the banked registers while doing so.
(Continue reading)

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Thomas Gleixner | 1 Jan 2003 14:49
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Re: jffs2 familiar image doesn't work

On Wednesday 01 January 2003 08:05, linuxcdrom wrote:

> I running arm-linux in my hardware board with StrongArm chipset. the board
> functions are the same as Intel Assabet developing board.
> The following is a printout of the bootup of a compiled familiar v4 kernel. 
> The kernel was compiled using the given .config file provided, after doing a
> cvs-rfamiliar-v0_4 checkout.
My hardware has the same functions too, but it uses different config settings.

> and it is really starting to get annoying, considering how many times I've
> reflashed the root filesystem to see if I can fix it. 
Keep on reflashing. At some point (see datasheet) your flash chip will reach 
the maximum erase count and your problem will be totaly different.

> My friend compiled the same kernel, and had success getting it working
Me too

> You cannot use older JFFS2 filesystems with newer kernels
True.

Check, if config setting match your hardware. 
Check, if the filesystem image you use is correct
Turn on debugging in MTD
Turn on debugging in JFFS2
Provide detailed logs

--

-- 
Thomas
____________________________________________________
linutronix - competence in embedded & realtime linux
(Continue reading)

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Kentropy | 2 Jan 2003 09:49
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Internal Server Error

http://www.arm.linux.org.uk

Internal Server Error
The server encountered an internal error or misconfiguration and was unable to complete your request.
Please contact the server administrator, webmaster <at> arm.uk.linux.org and inform them of the time the
error occurred, and anything you
might have done that may have caused the error.

More information about this error may be available in the server error log.

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Russell King - ARM Linux | 2 Jan 2003 10:08
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Re: Internal Server Error

On Thu, Jan 02, 2003 at 09:49:36AM +0100, Kentropy wrote:
> http://www.arm.linux.org.uk
> 
> Internal Server Error
> The server encountered an internal error or misconfiguration and was unable to complete your request.
> Please contact the server administrator, webmaster <at> arm.uk.linux.org and inform them of the time the
error occurred, and anything you
> might have done that may have caused the error.
> 
> More information about this error may be available in the server error log.

Date? Time? IP address?

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Russell King - ARM Linux | 2 Jan 2003 10:24
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Re: Internal Server Error

On Thu, Jan 02, 2003 at 09:49:36AM +0100, Kentropy wrote:
> http://www.arm.linux.org.uk
> 
> Internal Server Error
> The server encountered an internal error or misconfiguration and was unable to complete your request.
> Please contact the server administrator, webmaster <at> arm.uk.linux.org and inform them of the time the
error occurred, and anything you
> might have done that may have caused the error.
> 
> More information about this error may be available in the server error log.

Ok, it looks like it crucified itself on 1 Jan 2003 at 4:15am (some 13
minutes after it was automatically restarted after rotating the logs.)

I need to talk to other people to get this sorted.  For the meanwhile,
stuff will be redirected to the backup site.

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Sanal Kumar | 2 Jan 2003 10:25
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Accessing DiskonChip

Hi all,

I am working on an Assabet like board.
I am trying to make a filesystem on msystem Disk on
chip.(The board boots using ramdisk).

I have added entries for mtd* and nftl* in in /dev

TIA
Best Regards
Sanal.

Log message
------------
DiskOnChip Millennium found at address 0x18000000
Flash chip found: Manufacturer ID: 98, Chip ID: E6
(Toshiba TC58V64AFT/DC)
1 flash chips found. Total DiskOnChip size: 8 MiB

My .config is as follows.
---------------------
#
# Automatically generated make config: don't edit
#
CONFIG_ARM=y
# CONFIG_EISA is not set
# CONFIG_SBUS is not set
# CONFIG_MCA is not set
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
(Continue reading)

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Jeff Sutherland | 3 Jan 2003 14:08

Linux ports to Samsung S3C2410/5410

On Samsung's web site and in other info on the net they claim that they have a 
version of Linux running on the S3C2410 (ARM 925 core).  Since I can't seem 
to locate any source code with references to this part, is this just 
vapourware or the typical Asian black hole (open source goes in, but nothing 
ever comes out).

--

-- 
  Jeff Sutherland, Accelent Systems, Inc.   <http://www.accelent.com>
  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  
Kodachrome: After nearly 70 years there's still no better way to
preserve an image.

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Gmane