headers
Kukjin Kim | 25 May 2013 01:25

[GIT PULL] Samsung fixes-3 for v3.10

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-fixes-3

for you to fetch changes up to 15f504f0c2038b9a0f1569c9ce34def61f0c65be:

   ARM: SAMSUNG: Add names to fimd0 IRQ resources (2013-05-25 06:49:43 
+0900)

----------------------------------------------------------------
Fixes following for v3.10
- to get usb2 working on the Chromebook with adding the
   usb phy node for usb2 on exynos5250
- supporting exynos4210 rev0 SoC
- exynos5440 restart applying only to powered-on domains
- drm-exynos probe failure with adding resource names to
   fimd0 platform device

----------------------------------------------------------------
Jungseok Lee (1):
       ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC

Tomasz Figa (2):
       ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
       ARM: SAMSUNG: Add names to fimd0 IRQ resources
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Vikas Sajjan | 24 May 2013 12:31
Favicon

[RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs

This patch series does the following: 

 1) Factors out possible common code, unifies the clk strutures used
    for PLL35XX & PLL36XX and usues clk->base instead of clk->con0

 2) Defines a common rate_table which will contain recommended p, m, s and k
    values for supported rates that needs to be changed for changing
    corresponding PLL's rate

 3) Adds set_rate() and round_rate() clk_ops for PLL35XX and PLL36XXX

Is rebased on branch kgene's "for-next"
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

And tested these patch on chromebook for EPLL settings for Audio on our chrome tree.

Vikas Sajjan (2):
  clk: samsung: Add set_rate() clk_ops for PLL36XX
  clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

Yadwinder Singh Brar (3):
  clk: samsung: Use clk->base instead of directly using clk->con0 for
    PLL3XXX
  clk: samsung: Add support to register rate_table for PLL3XXX
  clk: samsung: Add set_rate() clk_ops for PLL35XX

 drivers/clk/samsung/clk-exynos4.c    |   10 +-
 drivers/clk/samsung/clk-exynos5250.c |   29 +++-
 drivers/clk/samsung/clk-pll.c        |  243 ++++++++++++++++++++++++++++++----
 drivers/clk/samsung/clk-pll.h        |   27 +++-
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Tomasz Figa | 24 May 2013 12:08

Re: [RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs

Hi Yadwinder,

On Friday 24 of May 2013 15:30:58 Yadwinder Singh Brar wrote:
> 
> 
> Hi Tomasz,
> 
> 
> All the patches are delivered properly in 2nd attempt to linux-samsung-soc 
mailing list as seen bellow:

Sure, they are delivered to this mailing list, but don't have any other 
recpients, which makes it impossible to properly reply to them.

> http://www.mail-archive.com/linux-samsung-soc <at> vger.kernel.org/msg18357.html
> http://www.mail-archive.com/linux-samsung-soc <at> vger.kernel.org/msg18362.html
> http://www.mail-archive.com/linux-samsung-soc <at> vger.kernel.org/msg18358.html
> http://www.mail-archive.com/linux-samsung-soc <at> vger.kernel.org/msg18359.html
> http://www.mail-archive.com/linux-samsung-soc <at> vger.kernel.org/msg18360.html
> http://www.mail-archive.com/linux-samsung-soc <at> vger.kernel.org/msg18361.html
> 
> 
> Please let me know if you still want us to resend series again 3rd time.

Please resend the series again with all the necessary recipients, including 
this list, linux-arm-kernel list and all the applicable people on CC.

Also please do _not_ send HTML messages to mailing lists. Only plain text is 
accepted on most of them and even some people block HTML messages, since most 
of the SPAM is sent as HTML.
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Vikas Sajjan | 24 May 2013 07:55
Favicon

[RESEND PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs

This patch series does the following: 

 1) Factors out possible common code, unifies the clk strutures used
    for PLL35XX & PLL36XX and usues clk->base instead of clk->con0

 2) Defines a common rate_table which will contain recommended p, m, s and k
    values for supported rates that needs to be changed for changing
    corresponding PLL's rate

 3) Adds set_rate() and round_rate() clk_ops for PLL35XX and PLL36XXX

Is rebased on branch kgene's "for-next"
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

And tested these patch on chromebook for EPLL settings for Audio on our chrome tree.

Vikas Sajjan (2):
  clk: samsung: Add set_rate() clk_ops for PLL36XX
  clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

Yadwinder Singh Brar (3):
  clk: samsung: Use clk->base instead of directly using clk->con0 for
    PLL3XXX
  clk: samsung: Add support to register rate_table for PLL3XXX
  clk: samsung: Add set_rate() clk_ops for PLL35XX

 drivers/clk/samsung/clk-exynos4.c    |   10 +-
 drivers/clk/samsung/clk-exynos5250.c |   29 +++-
 drivers/clk/samsung/clk-pll.c        |  243 ++++++++++++++++++++++++++++++----
 drivers/clk/samsung/clk-pll.h        |   27 +++-
(Continue reading)

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Vikas Sajjan | 24 May 2013 06:52
Favicon

[PATCH 0/5] Add generic set_rate clk_ops for PLL35XX and PLL36XX for samsung SoCs

This patch series does the following: 

 1) Factors out possible common code, unifies the clk strutures used
    for PLL35XX & PLL36XX and usues clk->base instead of clk->con0

 2) Defines a common rate_table which will contain recommended p, m, s and k
    values for supported rates that needs to be changed for changing
    corresponding PLL's rate

 3) Adds set_rate() and round_rate() clk_ops for PLL35XX and PLL36XXX

Is rebased on branch kgene's "for-next"
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next

And tested these patch on chromebook for EPLL settings for Audio on our chrome tree.

Vikas Sajjan (2):
  clk: samsung: Add set_rate() clk_ops for PLL36XX
  clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC

Yadwinder Singh Brar (3):
  clk: samsung: Use clk->base instead of directly using clk->con0 for
    PLL3XXX
  clk: samsung: Add support to register rate_table for PLL3XXX
  clk: samsung: Add set_rate() clk_ops for PLL35XX

 drivers/clk/samsung/clk-exynos4.c    |   10 +-
 drivers/clk/samsung/clk-exynos5250.c |   29 +++-
 drivers/clk/samsung/clk-pll.c        |  243 ++++++++++++++++++++++++++++++----
 drivers/clk/samsung/clk-pll.h        |   27 +++-
(Continue reading)

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이정석 | 23 May 2013 14:15

[PATCH] ARM: EXYNOS: fix software reset logic for EXYNOS5440 SOC


This patch fixes software reset logic. Software reset applies only to
powered-on domains in SOC because software reset to all domains causes
reboot failure.

Signed-off-by: Jungseok Lee <jays.lee <at> samsung.com>
---
 arch/arm/mach-exynos/common.c |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7f431dd..a22615d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
 <at>  <at>  -317,9 +317,13  <at>  <at>  void exynos5_restart(char mode, const char *cmd)
 		val = 0x1;
 		addr = EXYNOS_SWRESET;
 	} else if (of_machine_is_compatible("samsung,exynos5440")) {
+		u32 status;
 		np = of_find_compatible_node(NULL, NULL,
"samsung,exynos5440-clock");
+		addr = of_iomap(np, 0) + 0xbc;
+		status = __raw_readl(addr);
 		addr = of_iomap(np, 0) + 0xcc;
-		val = (0xfff << 20) | (0x1 << 16);
+		val = __raw_readl(addr);
+		val = (val & 0xffff0000) | (status & 0xffff);
 	} else {
 		pr_err("%s: cannot support non-DT\n", __func__);
 		return;
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Jingoo Han | 22 May 2013 09:20

[PATCH] ARM: EXYNOS: add __cpuinit annotation to write_pen_release()

The variable __cpuinitdata pen_release is referenced by write_pen_release().
Also, write_pen_release() is called by exynos_secondary_init() which is
annotated with __cpuinit. Thus, __cpuinit should be added write_pen_release()
to fix section mismatch warning.

Fixed section mismatch warning as below:

  WARNING: vmlinux.o(.text.unlikely+0x1f4): Section mismatch in reference from the function
write_pen_release() to the variable
.cpuinit.data:pen_release
  The function write_pen_release() references the variable __cpuinitdata pen_release.
  This is often because write_pen_release lacks a __cpuinitdata annotation or the annotation of
pen_release is wrong.

Signed-off-by: Jingoo Han <jg1.han <at> samsung.com>
---
 arch/arm/mach-exynos/platsmp.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a0e8ff7..9676af2 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
 <at>  <at>  -58,7 +58,7  <at>  <at>  static inline void __iomem *cpu_boot_reg(int cpu)
  * observers, irrespective of whether they're taking part in coherency
  * or not.  This is necessary for the hotplug code to work reliably.
  */
-static void write_pen_release(int val)
+static void __cpuinit write_pen_release(int val)
 {
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ruefully.6256 | 22 May 2013 00:05

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ради тех, кто хочет унаследовать предельную выгоду 
http://goo.gl/pCHa4?/hjbiIfdP Дистрибьютор, твою мать!» Три и пять
раз единицы.
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Arun Kumar K | 21 May 2013 14:36

[PATCH] clk: Exynos5250: Add clocks for G3D

This patch adds the required clocks for ARM Mali IP
in Exynos5250.

Signed-off-by: Arun Kumar K <arun.kk <at> samsung.com>
---
 .../devicetree/bindings/clock/exynos5250-clock.txt         |    2 ++
 drivers/clk/samsung/clk-exynos5250.c                       |   12 +++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 1a05761..5b93637 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 <at>  <at>  -155,6 +155,8  <at>  <at>  clock which they consume.
   dp			342
   mixer			343
   hdmi			344
+  g3d			345
+  aclk_400_g3d		346

 Example 1: An example of a clock controller node is listed below.

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..7d87500 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
 <at>  <at>  -23,6 +23,7  <at>  <at> 
 #define DIV_CPU0		0x500
 #define SRC_CORE1		0x4204
 #define SRC_TOP0		0x10210
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Arun Kumar K | 21 May 2013 13:16

[PATCH] clk: Exynos5250: Fix HDMI clock number in documentation

This patch corrects the HDMI clock number given wrongly
in the documentation.

Signed-off-by: Arun Kumar K <arun.kk <at> samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5250-clock.txt |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 781a627..1a05761 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 <at>  <at>  -154,7 +154,7  <at>  <at>  clock which they consume.
   dsim0			341
   dp			342
   mixer			343
-  hdmi			345
+  hdmi			344

 Example 1: An example of a clock controller node is listed below.

--

-- 
1.7.10.4
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Kukjin Kim | 20 May 2013 19:11

[GIT PULL] Samsung fixes-2 for v3.10

The following changes since commit f722406faae2d073cc1d01063d1123c35425939e:

   Linux 3.10-rc1 (2013-05-11 17:14:08 -0700)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
tags/samsung-fixes-2

for you to fetch changes up to 7ec892ef5f1bd707e2d5ab128069cb6af75c7f07:

   ARM: dts: Enabling samsung-usb2phy driver for exynos5250 (2013-05-21 
01:26:17 +0900)

----------------------------------------------------------------
Fix to get usb2 working on the Chromebook with adding the
usb phy node for usb2 on exynos5250

----------------------------------------------------------------
Vivek Gautam (1):
       ARM: dts: Enabling samsung-usb2phy driver for exynos5250

  arch/arm/boot/dts/exynos5250.dtsi | 15 +++++++++++++++
  1 file changed, 15 insertions(+)
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