Lucas Stach | 22 Oct 14:31 2014

[PATCH] PCI / PM: handle failure to enable wakeup on PCIe PME

If the irqchip handling the PCIe PME interrupt is not able
to enable interrupt wakeup we should properly reflect this
in the PME suspend status.

This fixes a kernel warning on resume, where it would try
to disable the irq wakeup that failed to be activated while
suspending. The issue was introduced with 76cde7e49590
(PCI / PM: Make PCIe PME interrupts wake up from suspend-to-idle).

Reported-by: Richard Zhu <richard.zhu <at>>
Signed-off-by: Lucas Stach <l.stach <at>>
Tested-by: Richard Zhu <richard.zhu <at>>
Trimmed warning on resume looks like this:
[  109.292736] WARNING: CPU: 0 PID: 609 at kernel/irq/manage.c:536 irq_set_irq_wake+0xc0/0xf8()
[  109.301193] Unbalanced IRQ 384 wake disable
[  109.305392] Modules linked in:
[  109.308502] CPU: 0 PID: 609 Comm: kworker/u2:9 Tainted: G        W      3.18.0-rc1-00009-g820df3d-dirty #268
[  109.318368] Workqueue: events_unbound async_run_entry_fn
[  109.323718] Backtrace:
[  109.326233] [<80012460>] (dump_backtrace) from [<80012744>] (show_stack+0x18/0x1c)
[  109.339616] [<8001272c>] (show_stack) from [<806d8dc8>] (dump_stack+0x8c/0xa4)
[  109.346885] [<806d8d3c>] (dump_stack) from [<8002a88c>] (warn_slowpath_common+0x70/0x94)
[  109.360773] [<8002a81c>] (warn_slowpath_common) from [<8002a8e8>] (warn_slowpath_fmt+0x38/0x40)
[  109.376334] [<8002a8b4>] (warn_slowpath_fmt) from [<8006c2a8>] (irq_set_irq_wake+0xc0/0xf8)
[  109.388351] [<8006c1e8>] (irq_set_irq_wake) from [<802f22cc>] (pcie_pme_resume+0x34/0x64)
[  109.402328] [<802f2298>] (pcie_pme_resume) from [<802f1590>] (resume_iter+0x44/0x50)
[  109.413742] [<802f154c>] (resume_iter) from [<803784d4>] (device_for_each_child+0x4c/0x78)
[  109.422039] [<80378488>] (device_for_each_child) from [<802f196c>] (pcie_port_device_resume+0x18/0x20)
[  109.436085] [<802f1954>] (pcie_port_device_resume) from [<802e6f40>] (pci_pm_resume+0x7c/0x10c)
(Continue reading)

Jingoo Han | 22 Oct 06:58 2014

[PATCH RESEND ] PCI: exynos: Add exynos prefix before add_pcie_port/pcie_init

The add_pcie_port/pcie_init functions are Exynos-specific.
Add exynos prefix to avoid collision in global name space.

Signed-off-by: Jingoo Han <jg1.han <at>>
 drivers/pci/host/pci-exynos.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index c5d0ca3..902d7cd 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
 <at>  <at>  -509,8 +509,8  <at>  <at>  static struct pcie_host_ops exynos_pcie_host_ops = {
 	.host_init = exynos_pcie_host_init,

-static int __init add_pcie_port(struct pcie_port *pp,
-				struct platform_device *pdev)
+static int __init exynos_add_pcie_port(struct pcie_port *pp,
+				       struct platform_device *pdev)
 	int ret;

 <at>  <at>  -615,7 +615,7  <at>  <at>  static int __init exynos_pcie_probe(struct platform_device *pdev)
 		goto fail_bus_clk;

-	ret = add_pcie_port(pp, pdev);
+	ret = exynos_add_pcie_port(pp, pdev);
 	if (ret < 0)
(Continue reading)

Kevin Wilson | 21 Oct 21:30 2014

Mailboxes userspace application communicating with a PCI driver


Should all PCI devices support mailboxes ?

Is there some example of an opensource userspace application which
communicates with a PCI driver by mailboxes?  (preferably a network

Johannes Thumshirn | 21 Oct 16:37 2014

Question regarding pci_request_region()


I've some questions regarding pci_request_region(). Is there a similar function
that allows me to request the memory from a PCIe device, but not a whole BAR?

in drivers/mcb/mcb-pci.c I do a pci_request_region() for BAR 0. But I only need
the first 0x200 bytes. pci_request_region() locks the memory and thus probing of
mcb attached sub devices fails, as they can't do a request_mem on their part of
the PCI memory space until the mcb parser is done and releases BAR0.

Generally this is no problem when you build all drivers as modules, but once I
do build in drivers, probing fails. Before rewriting all mcb based drivers to
use deferred probing I wanted to ask if there is a more clean way to do this.

Thanks in advance,
Kamal Mostafa | 20 Oct 21:08 2014

[PATCH] Revert duplicate "PCI: pciehp: Prevent NULL dereference during probe"

This reverts commit bceee4a97eb58bd0e80e39eff11b506ddd9e7ad3.

This patch was applied twice (identical patch, different descriptions):
    62e4492 PCI: Prevent NULL dereference during pciehp probe
    bceee4a PCI: pciehp: Prevent NULL dereference during probe

Revert the latter to dispose of the duplicated code block.

Signed-off-by: Kamal Mostafa <kamal <at>>
Cc: Andreas Noever <andreas.noever <at>>
Cc: Bjorn Helgaas <bhelgaas <at>>
Cc: stable <at>  # v3.2+
 drivers/pci/hotplug/pciehp_core.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index 3a5e7e2..07aa722 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
 <at>  <at>  -262,13 +262,6  <at>  <at>  static int pciehp_probe(struct pcie_device *dev)
 		goto err_out_none;

-	if (!dev->port->subordinate) {
-		/* Can happen if we run out of bus numbers during probe */
-		dev_err(&dev->device,
-			"Hotplug bridge without secondary bus, ignoring\n");
-		goto err_out_none;
-	}
(Continue reading)

Marcel Apfelbaum | 20 Oct 16:04 2014

[PATCH v4] PCI: add kernel parameter to override devid<->driver mapping.

Scanning a lot of devices during boot requires a lot of time.
On other scenarios there is a need to bind a driver to a specific slot.

Binding devices to pci-stub driver does not work,
as it will not differentiate between devices of the
same type. Using some start scripts is error prone.

The solution leverages driver_override functionality introduced by

	commit: 782a985d7af26db39e86070d28f987cad21313c0
	Author: Alex Williamson <alex.williamson <at>>
	Date:   Tue May 20 08:53:21 2014 -0600

    	PCI: Introduce new device binding path using pci_dev.driver_override

In order to bind PCI slots to specific drivers use:

Signed-off-by: Marcel Apfelbaum <marcel.a <at>>
v3 -> v4:
 - Addressed Alex Williamson's comments:
   - Modified the type of driver_override_entry's fields
   - Used PCI_DEVFN when appropriated
   - Removed redundant checks
   - Replaced BUG_ON with pr_err messages
   - Simpler command line parsing
 - Addressed Michael S. Tsirkin comments
   - removed DRIVER_OVERRIDE_NAME_LENGTH limitation
v2 -> v3:
(Continue reading)

Vidya Sagar | 20 Oct 13:04 2014

[PATCH v2] PCI: tegra: Enable root port specific features

Enables root port to advertise its ASPM-L1 capability
resulting in possible link entry to L1 when an ASPM-L1 capable
device is connected
Enables per-controller & per-TMS clock clamping by default
Enabling above features result in more power saving

It also avoids PM message truncation by waiting for DLLP to finish
before entering into L1 or L2

Signed-off-by: Vidya Sagar <vidyas <at>>
 Removed rp_read() & rp_write() as they seem to be redundant
 Moved port disable code under error condition i.e. it the link
  is down, corresponding port will be disabled

 drivers/pci/host/pci-tegra.c | 50 +++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 45 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 3d43874..7f32b07 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
 <at>  <at>  -237,6 +237,18  <at>  <at> 
 		(0xf  << PADS_REFCLK_CFG_DRVI_SHIFT)     \

+#define NV_PCIE2_RP_VEND_XP1			0x00000F04
(Continue reading)

Richard Zhu | 20 Oct 07:25 2014

[PATCH v8]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto.

Main changes since the v6(v7 is ignored):
1. Regarding to Lucas' suggestion, assert per-reset in suspend,
and de-assert it in resume.
2. Use pp->ops->get_msi_data in dw_pcie_msi_cfg_restore()
if there is one get_msi_data pp ops callback, refer to Muali's comment.
3. In order to avoid the compilation, squash imx6 changes with patch2-5
of v6, since the prototype of the host_init is changed.

[PATCH v8 1/9] PCI: designware: Refine setup_rc and add msi data
[PATCH v8 2/9] PCI: designware: Fix one potential assignment error of
[PATCH v8 3/9] ARM: imx6sx: Add imx6sx pcie related gpr bits
[PATCH v8 4/9] PCI: imx6: Wait the clocks to stabilize after ref_en
[PATCH v8 5/9] PCI: imx6: Add imx6sx pcie support
[PATCH v8 6/9] ARM: imx6qdl: Enable pcie on imx6qdl sabreauto
[PATCH v8 7/9] ARM: imx6: Update dts and binding for imx6sx pcie
[PATCH v8 8/9] ARM: imx6sx: Add syscon into gpc dts
[PATCH v8 9/9] ARM: imx6sx: Enable pcie on imx6sx sdb board
Richard Zhu | 20 Oct 04:19 2014

[PATCH v7]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto.

Main changes since the v6:
1. Regarding to Lucas' suggestion, assert per-reset in suspend,
and de-assert it in resume. Thanks Lucas.

[PATCH v7 01/13] PCI: designware: Refine setup_rc and add msi data
[PATCH v7 02/13] PCI: designware: Set func type of host init to int
[PATCH v7 03/13] PCI: dra7xx: Change the func type of host init
[PATCH v7 04/13] PCI: exynos: Change the func type of host init
[PATCH v7 05/13] PCI: spear: Change the func type of host init
[PATCH v7 06/13] PCI: designware: Fix one potential assignment error
[PATCH v7 07/13] ARM: imx6sx: Add imx6sx pcie related gpr bits
[PATCH v7 08/13] PCI: imx6: Wait the clocks to stabilize after ref_en
[PATCH v7 09/13] PCI: imx6: Add imx6sx pcie support
[PATCH v7 10/13] ARM: imx6qdl: Enable pcie on imx6qdl sabreauto
[PATCH v7 11/13] ARM: imx6: Update dts and binding for imx6sx pcie
[PATCH v7 12/13] ARM: imx6sx: Add syscon into gpc dts
[PATCH v7 13/13] ARM: imx6sx: Enable pcie on imx6sx sdb board
Daniel J Blueman | 19 Oct 03:45 2014

[PATCH v2 1/5] Numachip: Fix build failure with trunk GCC

Fix APIC declaration to be consistent with definition; this addresses
a compilation failure with the development branch of GCC, see:

Signed-off-by: Daniel J Blueman <daniel <at>>
 arch/x86/kernel/apic/apic_numachip.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index ae91539..81d70ba 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
 <at>  <at>  -32,7 +32,7  <at>  <at> 

 static int numachip_system __read_mostly;

-static const struct apic apic_numachip __read_mostly;
+static const struct apic apic_numachip __refconst;

 static unsigned int get_apic_id(unsigned long x)


Li, Zhen-Hua | 17 Oct 11:13 2014

[PATCH 1/1] pci: reset all pci endpoints to stop on going dma

This is an update of the patch

This patch is doing the reset works before the kdump kernel boots.

On a Linux system with iommu supported and many PCI devices on it,
when kernel crashed and the kdump kernel boots with intel_iommu=on,
there may be some unexpected DMA requests on this adapter, which will
cause DMA Remapping faults like:
    dmar: DRHD: handling fault status reg 102
    dmar: DMAR:[DMA Read] Request device [41:00.0] fault addr fff81000
    DMAR:[fault reason 01] Present bit in root entry is clear

This bug may happen on *any* PCI device.
Analysis for this bug:

The present bit is set in this function:

static struct context_entry * device_to_context_entry(
                struct intel_iommu *iommu, u8 bus, u8 devfn)

Calling tree:
    device driver
(Continue reading)