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Nobin Mathew | 1 Apr 2010 07:36
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registers and cache memory

I have a basic question regarding caching

1) Will peripheral device registers be cached in cache memory?
2) If not how caching is avoided for this address?
3) If yes how is asynchronous changes in hardware registers is getting
reflected in value read from that register.
#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
char __force  *)(a))
#define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
char __force  *)(a) = (v))

will volatile does that magic? I don't think so. Please correct me if
I am wrong.

Thanks in Advance

Nobin

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Anand Raj Manickam | 1 Apr 2010 07:23
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Re: Memory usage analysis

On Wed, Mar 31, 2010 at 9:49 PM, Mulyadi Santosa <mulyadi.santosa <at> gmail.com> wrote:
Hi...

On Wed, Mar 31, 2010 at 17:38, Anand Raj Manickam <anandrm <at> gmail.com> wrote:
>
> Using these tools i m able to account roughly around
>
> 100 MB of user space data
> 20 MB of kernel space (slab allocs)
> The total memory is around 512MB  out of which i m able to account only for
> 120MB of memory .


What you might forgot is the fact that some user space programs (if
not all, in some cases) share some of its memory with others in the
form of shared library, system V shared memory etc. Thus, user space
memory consumption could be smaller than you think. Top, AFAIK, does
not count on this fact.

I suggest you look directly at /proc/<pid>/status, specifically its
VmRSS. AFAIK, this field better describe the memory consumption of a
process. If you need better precision, once I recall there was a patch
from Matt Mckall that does more precise memory accounting.

About kernel space memory assumption, I agree with Srdjan that you
seems missed out the buffer + cache. Further, if you take a look on
/proc/meminfo, there are fields like page tables, vmalloc, kernel
stack etc that form the kernel mode of memory consumption.

Hope it helps


This is a snapshot of meminfo and free

debian:~# cat /proc/meminfo
MemTotal:       508612 kB
MemFree:         12428 kB
Buffers:         94252 kB
Cached:         304792 kB
SwapCached:          0 kB
Active:         267896 kB
Inactive:       188088 kB
HighTotal:           0 kB
HighFree:            0 kB
LowTotal:       508612 kB
LowFree:         12428 kB
SwapTotal:     1485972 kB
SwapFree:      1485908 kB
Dirty:             132 kB
Writeback:           0 kB
AnonPages:       56944 kB
Mapped:          14656 kB
Slab:            34724 kB
SReclaimable:    28268 kB
SUnreclaim:       6456 kB
PageTables:        836 kB
NFS_Unstable:        0 kB
Bounce:              0 kB
WritebackTmp:        0 kB
CommitLimit:   1740276 kB
Committed_AS:   662780 kB
VmallocTotal:   516088 kB
VmallocUsed:      3696 kB
VmallocChunk:   511860 kB
debian:~#
debian:~#
debian:~# free
                      total       used       free     shared    buffers     cached
Mem:        508612     496184      12428          0      94260     304792
-/+ buffers/cache:      97132     411480
Swap:      1485972         64    1485908
debian:~#

I guess free derives all the info from meminfo .

Still can someone shed some light on buffers and cached ?













 
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regards,

Mulyadi Santosa
Freelance Linux trainer and consultant

blog: the-hydra.blogspot.com
training: mulyaditraining.blogspot.com

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Harishkumar V | 1 Apr 2010 08:59
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Netlink Socket in Linux Kernel

Hi,

I am experimenting netlink socket for kernel space to user space communication in linux 2.6.32 kernel.

My intension is to perform,

kernel space --------------> user space
kernel space <------------- user space

i have few questions,

1) how to determine the pid of the userspace process, if kernel is going to initiate the communication by sending the data.
Because, i have seen examples of netlink program where only user space process initiates the data flow by requesting.

2) When netlink receives the data from user space, it invokes the handler which runs in separate context, like below,

         driver_init()
          {
         netlink_kernel_create(&init_net, KNETLINK_UNIT, 0, knetlink_input, NULL, THIS_MODULE);
          }

       void knetlink_input( struct sk_buff * skb)
       {
        mutex_lock(&mut);
        netlink_rcv_skb(skb, &knetlink_process);
        mutex_unlock(&mut);
        }
  
       int knetlink_process( struct sk_buff * skb, struct nlmsghdr *nlh ) //receive data from userspace
       {
               //receive data .........
              //data is only available here
       }

         while (some condition) {
        my_function() //driver
        {
              get_data(data); -> where i get data
              netlink_unicast(data); ---------> send data to userspace
             // i have to process data here, and i do not have data availabe here...
            
         }
        }

can this way possible to implement , if possible, how it can be done,
              
               while (some condition) {  
                my_function () // driver
                {
                          get_data(data); -> where i get data
                          netlink_unicast(data); ---------> send data to userspace
                          netlink_receive(data); -----------> receive data from userspace
                          process data(data); //some processing on data
                          printk ("data");
                 }
               }
        
--
Thanks and Regards,
Harish Kumar. V

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loody | 1 Apr 2010 18:09
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Re: registers and cache memory

hi:

2010/4/1 Nobin Mathew <nobin.mathew <at> gmail.com>:
> I have a basic question regarding caching
>
> 1) Will peripheral device registers be cached in cache memory?
if your register locate the place where cpu don't cache it.
it won't be cached.
take mips for example, address after 0xa0000000 is uncache and if your
registers are located there, it won't be cached.

> 2) If not how caching is avoided for this address?
flush it back after you finish setting all the registers.

> 3) If yes how is asynchronous changes in hardware registers is getting
> reflected in value read from that register.
> #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
> char __force  *)(a))
> #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
> char __force  *)(a) = (v))
>
> will volatile does that magic? I don't think so. Please correct me if
> I am wrong.
As far as I know, volatile is used to force compiler not to do the optimism.
and cache is the behaviour of your cpu.

Hope this help,
miloody

>
> Thanks in Advance
>
> Nobin
>
> --
> To unsubscribe from this list: send an email with
> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
> Please read the FAQ at http://kernelnewbies.org/FAQ
>
>

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Chetan Nanda | 1 Apr 2010 18:04
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Re: registers and cache memory



On Thu, Apr 1, 2010 at 11:06 AM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
I have a basic question regarding caching

1) Will peripheral device registers be cached in cache memory?
2) If not how caching is avoided for this address?
3) If yes how is asynchronous changes in hardware registers is getting
reflected in value read from that register.
#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
char __force  *)(a))
#define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
char __force  *)(a) = (v))
 
Device register address  should never be cached. In case of MIPS architecture device registers are mapped onto uncached address space.
I am sure other architecture must be providing similar kind of provision.
 

will volatile does that magic? I don't think so. Please correct me if
I am wrong.

Thanks in Advance

Nobin

~cnanda
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Nobin Mathew | 1 Apr 2010 19:02
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Re: registers and cache memory

How we will make the uncached region, is this a hardware facility? or
Paging facility, marking pages as uncacheable?

what is KSEG1 register in MIPS?

On Thu, Apr 1, 2010 at 9:39 PM, loody <miloody <at> gmail.com> wrote:
> hi:
>
> 2010/4/1 Nobin Mathew <nobin.mathew <at> gmail.com>:
>> I have a basic question regarding caching
>>
>> 1) Will peripheral device registers be cached in cache memory?
> if your register locate the place where cpu don't cache it.
> it won't be cached.
> take mips for example, address after 0xa0000000 is uncache and if your
> registers are located there, it won't be cached.
>
>> 2) If not how caching is avoided for this address?
> flush it back after you finish setting all the registers.
>
>> 3) If yes how is asynchronous changes in hardware registers is getting
>> reflected in value read from that register.
>> #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
>> char __force  *)(a))
>> #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
>> char __force  *)(a) = (v))
>>
>> will volatile does that magic? I don't think so. Please correct me if
>> I am wrong.
> As far as I know, volatile is used to force compiler not to do the optimism.
> and cache is the behaviour of your cpu.
>
> Hope this help,
> miloody
>
>>
>> Thanks in Advance
>>
>> Nobin
>>
>> --
>> To unsubscribe from this list: send an email with
>> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
>> Please read the FAQ at http://kernelnewbies.org/FAQ
>>
>>
>

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Nobin Mathew | 1 Apr 2010 19:07
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Re: registers and cache memory

I got a link for MIPS
http://www.johnloomis.org/microchip/pic32/memory/memory.html

On Thu, Apr 1, 2010 at 10:32 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
> How we will make the uncached region, is this a hardware facility? or
> Paging facility, marking pages as uncacheable?
>
> what is KSEG1 register in MIPS?
>
> On Thu, Apr 1, 2010 at 9:39 PM, loody <miloody <at> gmail.com> wrote:
>> hi:
>>
>> 2010/4/1 Nobin Mathew <nobin.mathew <at> gmail.com>:
>>> I have a basic question regarding caching
>>>
>>> 1) Will peripheral device registers be cached in cache memory?
>> if your register locate the place where cpu don't cache it.
>> it won't be cached.
>> take mips for example, address after 0xa0000000 is uncache and if your
>> registers are located there, it won't be cached.
>>
>>> 2) If not how caching is avoided for this address?
>> flush it back after you finish setting all the registers.
>>
>>> 3) If yes how is asynchronous changes in hardware registers is getting
>>> reflected in value read from that register.
>>> #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
>>> char __force  *)(a))
>>> #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
>>> char __force  *)(a) = (v))
>>>
>>> will volatile does that magic? I don't think so. Please correct me if
>>> I am wrong.
>> As far as I know, volatile is used to force compiler not to do the optimism.
>> and cache is the behaviour of your cpu.
>>
>> Hope this help,
>> miloody
>>
>>>
>>> Thanks in Advance
>>>
>>> Nobin
>>>
>>> --
>>> To unsubscribe from this list: send an email with
>>> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
>>> Please read the FAQ at http://kernelnewbies.org/FAQ
>>>
>>>
>>
>

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Nobin Mathew | 1 Apr 2010 19:13
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Re: registers and cache memory

But How this will work in ARM/x86 we don't have such address space
division, is that done by pagetable settings?

Nobin

On Thu, Apr 1, 2010 at 10:37 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
> I got a link for MIPS
> http://www.johnloomis.org/microchip/pic32/memory/memory.html
>
>
> On Thu, Apr 1, 2010 at 10:32 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
>> How we will make the uncached region, is this a hardware facility? or
>> Paging facility, marking pages as uncacheable?
>>
>> what is KSEG1 register in MIPS?
>>
>> On Thu, Apr 1, 2010 at 9:39 PM, loody <miloody <at> gmail.com> wrote:
>>> hi:
>>>
>>> 2010/4/1 Nobin Mathew <nobin.mathew <at> gmail.com>:
>>>> I have a basic question regarding caching
>>>>
>>>> 1) Will peripheral device registers be cached in cache memory?
>>> if your register locate the place where cpu don't cache it.
>>> it won't be cached.
>>> take mips for example, address after 0xa0000000 is uncache and if your
>>> registers are located there, it won't be cached.
>>>
>>>> 2) If not how caching is avoided for this address?
>>> flush it back after you finish setting all the registers.
>>>
>>>> 3) If yes how is asynchronous changes in hardware registers is getting
>>>> reflected in value read from that register.
>>>> #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
>>>> char __force  *)(a))
>>>> #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
>>>> char __force  *)(a) = (v))
>>>>
>>>> will volatile does that magic? I don't think so. Please correct me if
>>>> I am wrong.
>>> As far as I know, volatile is used to force compiler not to do the optimism.
>>> and cache is the behaviour of your cpu.
>>>
>>> Hope this help,
>>> miloody
>>>
>>>>
>>>> Thanks in Advance
>>>>
>>>> Nobin
>>>>
>>>> --
>>>> To unsubscribe from this list: send an email with
>>>> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
>>>> Please read the FAQ at http://kernelnewbies.org/FAQ
>>>>
>>>>
>>>
>>
>

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Chetan Nanda | 1 Apr 2010 19:48
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Re: registers and cache memory



On Thu, Apr 1, 2010 at 10:43 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
But How this will work in ARM/x86 we don't have such address space
division, is that done by pagetable settings?
Yes via pagetable settings you can achieve this.
But you don't have to do it manually, kernel provide facilities like 'ioremap_nocache()' to map device address space as uncachable

~cnanda

Nobin

On Thu, Apr 1, 2010 at 10:37 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
> I got a link for MIPS
> http://www.johnloomis.org/microchip/pic32/memory/memory.html
>
>
> On Thu, Apr 1, 2010 at 10:32 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
>> How we will make the uncached region, is this a hardware facility? or
>> Paging facility, marking pages as uncacheable?
>>
>> what is KSEG1 register in MIPS?
>>
>> On Thu, Apr 1, 2010 at 9:39 PM, loody <miloody <at> gmail.com> wrote:
>>> hi:
>>>
>>> 2010/4/1 Nobin Mathew <nobin.mathew <at> gmail.com>:
>>>> I have a basic question regarding caching
>>>>
>>>> 1) Will peripheral device registers be cached in cache memory?
>>> if your register locate the place where cpu don't cache it.
>>> it won't be cached.
>>> take mips for example, address after 0xa0000000 is uncache and if your
>>> registers are located there, it won't be cached.
>>>
>>>> 2) If not how caching is avoided for this address?
>>> flush it back after you finish setting all the registers.
>>>
>>>> 3) If yes how is asynchronous changes in hardware registers is getting
>>>> reflected in value read from that register.
>>>> #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
>>>> char __force  *)(a))
>>>> #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
>>>> char __force  *)(a) = (v))
>>>>
>>>> will volatile does that magic? I don't think so. Please correct me if
>>>> I am wrong.
>>> As far as I know, volatile is used to force compiler not to do the optimism.
>>> and cache is the behaviour of your cpu.
>>>
>>> Hope this help,
>>> miloody
>>>
>>>>
>>>> Thanks in Advance
>>>>
>>>> Nobin
>>>>
>>>> --
>>>> To unsubscribe from this list: send an email with
>>>> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
>>>> Please read the FAQ at http://kernelnewbies.org/FAQ
>>>>
>>>>
>>>
>>
>

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Greg Freemyer | 1 Apr 2010 20:01
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Gravatar

Re: registers and cache memory

I'd be shocked if its not all taken care of in advance at the bus level.

If you are developing a whole new bus architecture, you would need to
ensure the bus gets mapped to non-cacheable address space.

ie. If this were 10 years ago and you were developing the PCIexpress
bus, then you would need to address non-caching issues for the entire
bus and any cards that eventually get popped into it.  But I seriously
doubt the individual card drivers need to worry about it.

Greg

On Thu, Apr 1, 2010 at 1:13 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
> But How this will work in ARM/x86 we don't have such address space
> division, is that done by pagetable settings?
>
> Nobin
>
> On Thu, Apr 1, 2010 at 10:37 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
>> I got a link for MIPS
>> http://www.johnloomis.org/microchip/pic32/memory/memory.html
>>
>>
>> On Thu, Apr 1, 2010 at 10:32 PM, Nobin Mathew <nobin.mathew <at> gmail.com> wrote:
>>> How we will make the uncached region, is this a hardware facility? or
>>> Paging facility, marking pages as uncacheable?
>>>
>>> what is KSEG1 register in MIPS?
>>>
>>> On Thu, Apr 1, 2010 at 9:39 PM, loody <miloody <at> gmail.com> wrote:
>>>> hi:
>>>>
>>>> 2010/4/1 Nobin Mathew <nobin.mathew <at> gmail.com>:
>>>>> I have a basic question regarding caching
>>>>>
>>>>> 1) Will peripheral device registers be cached in cache memory?
>>>> if your register locate the place where cpu don't cache it.
>>>> it won't be cached.
>>>> take mips for example, address after 0xa0000000 is uncache and if your
>>>> registers are located there, it won't be cached.
>>>>
>>>>> 2) If not how caching is avoided for this address?
>>>> flush it back after you finish setting all the registers.
>>>>
>>>>> 3) If yes how is asynchronous changes in hardware registers is getting
>>>>> reflected in value read from that register.
>>>>> #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned
>>>>> char __force  *)(a))
>>>>> #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned
>>>>> char __force  *)(a) = (v))
>>>>>
>>>>> will volatile does that magic? I don't think so. Please correct me if
>>>>> I am wrong.
>>>> As far as I know, volatile is used to force compiler not to do the optimism.
>>>> and cache is the behaviour of your cpu.
>>>>
>>>> Hope this help,
>>>> miloody
>>>>
>>>>>
>>>>> Thanks in Advance
>>>>>
>>>>> Nobin
>>>>>
>>>>> --
>>>>> To unsubscribe from this list: send an email with
>>>>> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
>>>>> Please read the FAQ at http://kernelnewbies.org/FAQ
>>>>>
>>>>>
>>>>
>>>
>>
>
> --
> To unsubscribe from this list: send an email with
> "unsubscribe kernelnewbies" to ecartis <at> nl.linux.org
> Please read the FAQ at http://kernelnewbies.org/FAQ
>
>

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