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GVA Abogados. | 15 Aug 15:36 2014

Transaction XLK-14-TTF/ESP.

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Attorney At Law.
gvaintencia <at> aim.com
Thierry Reding | 13 Aug 12:28 2014

[PATCH v4 0/8] asm-generic/io.h overhaul

From: Thierry Reding <treding <at> nvidia.com>


Here is the fourth version of a series that started out as an attempt to
provide string versions of the read*() and write*() accessors to more
architectures so that drivers can use them portably. The series has
since evolved into a more general cleanup of asm-generic/io.h and the
functions defined therein.

Patch 1 is trivial and removes a redundant redefinition of PCI_IOBASE
from the asm/io.h header on ARC. Patches 2 and 3 remove unnecessary
volatile keywoards from some functions, which is a prerequisite to clean
up some of the functions in subsequent patches.

The xlate_dev_{kmem,mem}_ptr() functions are used to map memory when the
/dev/mem device is accessed. Patches 4 and 5 use more consistent data
types for these functions, which will get a "standard" prototype in the
asm-generic/io.h header in a subsequent patch.

Patch 6 is the bulk of this series. It implements the string variants of
the read*() and write*() accessors and cleans up various other parts of
the asm-generic/io.h header file. Macros are converted to static inline
functions for better type checking. Overriding generic implementations
in architectures is handled more consistently.

Patches 7 and 8, finally, make use of the asm-generic/io.h header on the
32-bit and 64-bit ARM architectures.

This is compile- and runtime-tested on 32-bit and 64-bit ARM and compile
(Continue reading)

Chen Gang | 13 Aug 00:48 2014

[PATCH v2] arch: Kconfig: Let all little endian architectures define CPU_LITTLE_ENDIAN explicitly

x86 and ia64 are always little endian. And another architectures may be
little endian: mips, sh, powerpc, and m32r (may mark CPU_LITTLE_ENDIAN
explicitly); also arm(64) and c6x (which may be !CPU_BIG_ENDIAN).

Some drivers (e.g. some of "drivers/isdn/hisax") may only support little
endian (CPU_LITTLE_ENDIAN), and some drivers may only support big endian

So export all little endian architectures within kernel wide, so can let
Kconfig easier for the modules which only support little endian or only
for big endian (assume !CPU_LITTLE_ENDIAN is same as CPU_BIG_ENDIAN).

Signed-off-by: Chen Gang <gang.chen.5i5j <at> gmail.com>
 arch/arm/Kconfig   | 5 +++++
 arch/arm64/Kconfig | 4 ++++
 arch/c6x/Kconfig   | 4 ++++
 arch/ia64/Kconfig  | 3 +++
 arch/x86/Kconfig   | 3 +++
 5 files changed, 19 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c49a775..0510a5d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
 <at>  <at>  -199,6 +199,11  <at>  <at>  config NEED_DMA_MAP_STATE
 	def_bool y

(Continue reading)

D.Y. CHAN | 9 Aug 15:09 2014

I hope this e-mãil is still in use

Forgivé me if you don't find interest in this.
I have a profitablé / Confidéntial deal [worth 48M Dollars] to discuss  
with you, but I need your permission before I give détails.

Thanks in adv.

This message was sent using IMP, the Internet Messaging Program.
D.Y. CHAN | 8 Aug 17:30 2014

Permission Request

Forgivé me if you don't find interest in this.
I have a profitablé / Confidéntial deal [worth 48M Dollars] to discuss  
with you, but I need your permission before I give détails.

Thanks in adv.

This message was sent using IMP, the Internet Messaging Program.
Nick Krause | 7 Aug 03:13 2014

[PATCH 1/1] bug: Add unreachable() to generic BUG() to silence warnings

Architectures which use generic BUG() have warnings like 

kernel/sched/core.c:2692:1: warning: control reaches end of non-void function [-Wreturn-type]
net/core/ethtool.c:236:1: warning: control reaches end of non-void function [-Wreturn-type]

Other BUG() implementations
have added unreachable() at end but generic does not. I guess
that is why
it showing these errors. We can silence them using unreachable().

Signed-off-by: Nick Krause <xerofoify <at> gmail.com>
 include/asm-generic/bug.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 630dd23..effcc82 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
 <at>  <at>  -48,6 +48,7  <at>  <at>  struct bug_entry {
 #define BUG() do { \
 	printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
 	panic("BUG!"); \
+	unreachable(); \
 } while (0)



(Continue reading)

Mrs Norbert | 6 Aug 12:01 2014

Product Enquiry

Good day,
My name is Mrs Norbert from Transworld Inc. I will like to make order inquiry on your product please send us
your prodcut catalog for a trial order.
Best Regard
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Contact Email: transworld_1mt <at> hotmail.com
Max Filippov | 2 Aug 03:11 2014

[PATCH v4 0/2] mm/highmem: make kmap cache coloring aware


this series adds mapping color control to the generic kmap code, allowing
architectures with aliasing VIPT cache to use high memory. There's also
use example of this new interface by xtensa.

Changes since v3:
- drop #include <asm/highmem.h> from mm/highmem.c as it's done in
- add 'User-visible effect' section to changelog.

Max Filippov (2):
  mm/highmem: make kmap cache coloring aware
  xtensa: support aliasing cache in kmap

 arch/xtensa/include/asm/highmem.h | 40 +++++++++++++++++-
 arch/xtensa/mm/highmem.c          | 18 ++++++++
 mm/highmem.c                      | 86 ++++++++++++++++++++++++++++++++++-----
 3 files changed, 131 insertions(+), 13 deletions(-)



Ho Chen Tung | 29 Jul 22:22 2014

My Dear Beloved!

Contact me with acceptance to transfer $21,410,000.00 to you. I will tell you the facts after I get your reply.
Andrew Morton | 1 Aug 22:10 2014

Re: [PATCH v3 1/2] mm/highmem: make kmap cache coloring aware

On Fri, 25 Jul 2014 23:43:46 +0400 Max Filippov <jcmvbkbc <at> gmail.com> wrote:

> VIPT cache with way size larger than MMU page size may suffer from
> aliasing problem: a single physical address accessed via different
> virtual addresses may end up in multiple locations in the cache.
> Virtual mappings of a physical address that always get cached in
> different cache locations are said to have different colors.
> L1 caching hardware usually doesn't handle this situation leaving it
> up to software. Software must avoid this situation as it leads to
> data corruption.
> One way to handle this is to flush and invalidate data cache every time
> page mapping changes color. The other way is to always map physical page
> at a virtual address with the same color. Low memory pages already have
> this property. Giving architecture a way to control color of high memory
> page mapping allows reusing of existing low memory cache alias handling
> code.
> Provide hooks that allow architectures with aliasing cache to align
> mapping address of high pages according to their color. Such architectures
> may enforce similar coloring of low- and high-memory page mappings and
> reuse existing cache management functions to support highmem.
> This code is based on the implementation of similar feature for MIPS by
> Leonid Yegoshin <Leonid.Yegoshin <at> imgtec.com>.

It's worth mentioning that xtensa needs this.

What is (still) missing from these changelogs is a clear description of
(Continue reading)