Aneesh Kumar K.V | 15 Oct 18:34 2014
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[PATCH 1/2] mm: Update generic gup implementation to handle hugepage directory

Update generic gup implementation with powerpc specific details.
On powerpc at pmd level we can have hugepte, normal pmd pointer
or a pointer to the hugepage directory.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar <at> linux.vnet.ibm.com>
---
 include/linux/hugetlb.h |   1 +
 include/linux/mm.h      |  26 +++++++++++
 mm/gup.c                | 113 +++++++++++++++++++++++-------------------------
 3 files changed, 81 insertions(+), 59 deletions(-)

diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 6e6d338641fe..65e12a24ce1d 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
 <at>  <at>  -138,6 +138,7  <at>  <at>  static inline void hugetlb_show_meminfo(void)
 #define prepare_hugepage_range(file, addr, len)	(-EINVAL)
 #define pmd_huge(x)	0
 #define pud_huge(x)	0
+#define pgd_huge(x)	0
 #define is_hugepage_only_range(mm, addr, len)	0
 #define hugetlb_free_pgd_range(tlb, addr, end, floor, ceiling) ({BUG(); 0; })
 #define hugetlb_fault(mm, vma, addr, flags)	({ BUG(); 0; })
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 02d11ee7f19d..f97732412cb4 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
 <at>  <at>  -1219,6 +1219,32  <at>  <at>  long get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
 		    struct vm_area_struct **vmas);
 int get_user_pages_fast(unsigned long start, int nr_pages, int write,
(Continue reading)

Aneesh Kumar K.V | 14 Oct 12:57 2014
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[PATCH 1/2] mm: Introduce a general RCU get_user_pages_fast.

get_user_pages_fast attempts to pin user pages by walking the page
tables directly and avoids taking locks. Thus the walker needs to be
protected from page table pages being freed from under it, and needs
to block any THP splits.

One way to achieve this is to have the walker disable interrupts, and
rely on IPIs from the TLB flushing code blocking before the page table
pages are freed.

On some platforms we have hardware broadcast of TLB invalidations, thus
the TLB flushing code doesn't necessarily need to broadcast IPIs; and
spuriously broadcasting IPIs can hurt system performance if done too
often.

This problem has been solved on PowerPC and Sparc by batching up page
table pages belonging to more than one mm_user, then scheduling an
rcu_sched callback to free the pages. This RCU page table free logic
has been promoted to core code and is activated when one enables
HAVE_RCU_TABLE_FREE. Unfortunately, these architectures implement
their own get_user_pages_fast routines.

The RCU page table free logic coupled with a an IPI broadcast on THP
split (which is a rare event), allows one to protect a page table
walker by merely disabling the interrupts during the walk.

This patch provides a general RCU implementation of get_user_pages_fast
that can be used by architectures that perform hardware broadcast of
TLB invalidations.

It is based heavily on the PowerPC implementation.
(Continue reading)

Webmaster | 14 Oct 04:17 2014
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Jose Calvache | 11 Oct 21:34 2014
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(Continue reading)

Will Deacon | 24 Sep 19:17 2014

[PATCH v3 00/17] Cross-architecture definitions of relaxed MMIO accessors

Hello everybody,

This is version three of the series I've originally posted here:

  v1: https://lkml.org/lkml/2014/4/17/269
  v2: https://lkml.org/lkml/2014/5/22/468

This is basically just a rebase on top of 3.17-rc6, minus the alpha patch
(which was merged into mainline).

I looked at reworking the non-relaxed accessors to imply mmiowb, but it
quickly got messy as some architectures (e.g. mips) deliberately keep
mmiowb and readX/writeX separate whilst others (e.g. powerpc) don't trust
drivers to get mmiowb correct, so add barriers to both. Given that
arm/arm64/x86 don't care about mmiowb, I've left that as an exercise for
an architecture that does care.

In order to get this lot merged, we probably want to merge the asm-generic
patch (1/17) first, so Acks would be much appreciated on the architecture
bits.

As before, I've included the original cover letter below, as that describes
what I'm trying to do in more detail.

Thanks,

Will

--->8

(Continue reading)

Benjamin Siaka | 22 Sep 03:16 2014
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Daniel Thompson | 9 Sep 14:12 2014

[PATCH] asm-generic/io.h: Implement read[bwlq]_relaxed()

Currently the read[bwlq]_relaxed() family are implemented on every
architecture except blackfin, m68k[1], metag, openrisc, s390[2] and
score. Increasingly drivers are being optimized to exploit relaxed
reads putting these architectures at risk of compilation failures for
shared drivers.

This patch addresses this by providing implementations of
read[bwlq]_relaxed() that are identical to the equivalent read[bwlq]().
All the above architectures include asm-generic/io.h .

Note that currently only eight architectures (alpha, arm, arm64, avr32,
hexagon, microblaze, mips and sh) implement write[bwlq]_relaxed() meaning
these functions are deliberately not included in this patch.

[1] m68k includes the relaxed family only when configured *without* MMU.
[2] s390 requires CONFIG_PCI to include the relaxed family.

Signed-off-by: Daniel Thompson <daniel.thompson <at> linaro.org>
Cc: Will Deacon <will.deacon <at> arm.com>
Cc: Arnd Bergmann <arnd <at> arndb.de>
Cc: linux-arch <at> vger.kernel.org
---
 include/asm-generic/io.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 975e1cc..85ea117 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
 <at>  <at>  -66,6 +66,16  <at>  <at>  static inline u32 readl(const volatile void __iomem *addr)
(Continue reading)

Aaron Lu | 9 Sep 04:32 2014
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[PATCH 0/2] Support CrystalCove PMIC ACPI operation region

The two patches add support for CrystalCove PMIC ACPI operation region.
The PMIC chip has two customized operation regions: one for power rail
manipulation and one for thermal purpose: sensor temperature reading
and trip point value reading/setting.

For an example ASL code on ASUS T100 with CrystalCove PMIC, see here:
https://gist.github.com/aaronlu/f5f65771a6c3251fae5d

Aaron Lu (2):
  gpio / CrystalCove: support virtual GPIO
  PMIC / opregion: support PMIC customized operation region for
    CrystalCove

 drivers/gpio/gpio-crystalcove.c           |  19 +-
 drivers/mfd/Kconfig                       |  11 +
 drivers/mfd/Makefile                      |   1 +
 drivers/mfd/intel_soc_pmic_crc.c          |   3 +
 drivers/mfd/intel_soc_pmic_crc_opregion.c | 229 +++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.c     | 350 ++++++++++++++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.h     |  35 +++
 include/asm-generic/gpio.h                |   2 +-
 8 files changed, 646 insertions(+), 4 deletions(-)
 create mode 100644 drivers/mfd/intel_soc_pmic_crc_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.h

--

-- 
1.9.3

(Continue reading)

Aaron Lu | 9 Sep 04:26 2014
Picon

[PATCH 0/2] Support CrystalCove PMIC ACPI operation region

The two patches add support for CrystalCove PMIC ACPI operation region.
The PMIC chip has two customized operation regions: one for power rail
manipulation and one for thermal purpose: sensor temperature reading
and trip point value reading/setting.

For an example ASL code on ASUS T100 with CrystalCove PMIC, see here:
https://gist.github.com/aaronlu/f5f65771a6c3251fae5d

Aaron Lu (2):
  gpio / CrystalCove: support virtual GPIO
  PMIC / opregion: support PMIC customized operation region for
    CrystalCove

 drivers/gpio/gpio-crystalcove.c           |  19 +-
 drivers/mfd/Kconfig                       |  11 +
 drivers/mfd/Makefile                      |   1 +
 drivers/mfd/intel_soc_pmic_crc.c          |   3 +
 drivers/mfd/intel_soc_pmic_crc_opregion.c | 229 +++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.c     | 350 ++++++++++++++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.h     |  35 +++
 include/asm-generic/gpio.h                |   2 +-
 8 files changed, 646 insertions(+), 4 deletions(-)
 create mode 100644 drivers/mfd/intel_soc_pmic_crc_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.h

--

-- 
1.9.3

(Continue reading)

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