Daniel Thompson | 9 Sep 14:12 2014

[PATCH] asm-generic/io.h: Implement read[bwlq]_relaxed()

Currently the read[bwlq]_relaxed() family are implemented on every
architecture except blackfin, m68k[1], metag, openrisc, s390[2] and
score. Increasingly drivers are being optimized to exploit relaxed
reads putting these architectures at risk of compilation failures for
shared drivers.

This patch addresses this by providing implementations of
read[bwlq]_relaxed() that are identical to the equivalent read[bwlq]().
All the above architectures include asm-generic/io.h .

Note that currently only eight architectures (alpha, arm, arm64, avr32,
hexagon, microblaze, mips and sh) implement write[bwlq]_relaxed() meaning
these functions are deliberately not included in this patch.

[1] m68k includes the relaxed family only when configured *without* MMU.
[2] s390 requires CONFIG_PCI to include the relaxed family.

Signed-off-by: Daniel Thompson <daniel.thompson <at> linaro.org>
Cc: Will Deacon <will.deacon <at> arm.com>
Cc: Arnd Bergmann <arnd <at> arndb.de>
Cc: linux-arch <at> vger.kernel.org
---
 include/asm-generic/io.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 975e1cc..85ea117 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
 <at>  <at>  -66,6 +66,16  <at>  <at>  static inline u32 readl(const volatile void __iomem *addr)
(Continue reading)

Aaron Lu | 9 Sep 04:32 2014
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[PATCH 0/2] Support CrystalCove PMIC ACPI operation region

The two patches add support for CrystalCove PMIC ACPI operation region.
The PMIC chip has two customized operation regions: one for power rail
manipulation and one for thermal purpose: sensor temperature reading
and trip point value reading/setting.

For an example ASL code on ASUS T100 with CrystalCove PMIC, see here:
https://gist.github.com/aaronlu/f5f65771a6c3251fae5d

Aaron Lu (2):
  gpio / CrystalCove: support virtual GPIO
  PMIC / opregion: support PMIC customized operation region for
    CrystalCove

 drivers/gpio/gpio-crystalcove.c           |  19 +-
 drivers/mfd/Kconfig                       |  11 +
 drivers/mfd/Makefile                      |   1 +
 drivers/mfd/intel_soc_pmic_crc.c          |   3 +
 drivers/mfd/intel_soc_pmic_crc_opregion.c | 229 +++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.c     | 350 ++++++++++++++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.h     |  35 +++
 include/asm-generic/gpio.h                |   2 +-
 8 files changed, 646 insertions(+), 4 deletions(-)
 create mode 100644 drivers/mfd/intel_soc_pmic_crc_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.h

--

-- 
1.9.3

(Continue reading)

Aaron Lu | 9 Sep 04:26 2014
Picon

[PATCH 0/2] Support CrystalCove PMIC ACPI operation region

The two patches add support for CrystalCove PMIC ACPI operation region.
The PMIC chip has two customized operation regions: one for power rail
manipulation and one for thermal purpose: sensor temperature reading
and trip point value reading/setting.

For an example ASL code on ASUS T100 with CrystalCove PMIC, see here:
https://gist.github.com/aaronlu/f5f65771a6c3251fae5d

Aaron Lu (2):
  gpio / CrystalCove: support virtual GPIO
  PMIC / opregion: support PMIC customized operation region for
    CrystalCove

 drivers/gpio/gpio-crystalcove.c           |  19 +-
 drivers/mfd/Kconfig                       |  11 +
 drivers/mfd/Makefile                      |   1 +
 drivers/mfd/intel_soc_pmic_crc.c          |   3 +
 drivers/mfd/intel_soc_pmic_crc_opregion.c | 229 +++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.c     | 350 ++++++++++++++++++++++++++++++
 drivers/mfd/intel_soc_pmic_opregion.h     |  35 +++
 include/asm-generic/gpio.h                |   2 +-
 8 files changed, 646 insertions(+), 4 deletions(-)
 create mode 100644 drivers/mfd/intel_soc_pmic_crc_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.c
 create mode 100644 drivers/mfd/intel_soc_pmic_opregion.h

--

-- 
1.9.3

(Continue reading)

info23 | 8 Sep 11:26 2014

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Andy Lutomirski | 6 Sep 00:13 2014
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[PATCH v5 0/5] x86: two-phase syscall tracing and seccomp fastpath

This applies to:
git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git seccomp-fastpath

Gitweb:
https://git.kernel.org/cgit/linux/kernel/git/kees/linux.git/log/?h=seccomp/fastpath

This is both a cleanup and a speedup.  It reduces overhead due to
installing a trivial seccomp filter by 87%.  The speedup comes from
avoiding the full syscall tracing mechanism for filters that don't
return SECCOMP_RET_TRACE.

This series depends on splitting the seccomp hooks into two phases.
The first phase evaluates the filter; it can skip syscalls, allow
them, kill the calling task, or pass a u32 to the second phase.  The
second phase requires a full tracing context, and it sends ptrace
events if necessary.  The seccomp core part is in Kees' seccomp/fastpath
tree.

These patches implement a similar split for the x86 syscall
entry work.  The C callback is invoked in two phases: the first has
only a partial frame, and it can request phase 2 processing with a
full frame.

Finally, I switch the 64-bit system_call code to use the new split
entry work.  This is a net deletion of assembly code: it replaces
all of the audit entry muck.

In the process, I fixed some bugs.

If this is acceptable, someone can do the same tweak for the
(Continue reading)

Husam Al Sayed | 3 Sep 20:31 2014
Picon

FROM: Husam Al Sayed.

FROM: Husam Al Sayed.

EMAIL:alsayedhusa <at> hotmail.com

Hello,

I decided to write you this proposal in good faith, believing that you will
not betray me. I am Mr. Husam Al Sayed, a Bank officer here in U.A.E.

One Mr. Peter Adams, a citizen of your country and Crude Oil dealer made a fixed deposit with my bank in 2005
for 108 calendar months, valued at US$30,000,000.00 (Thirty Million United State Dollars) the due date
for this deposit contract was last 22nd of January 2014. Sadly Peter was among the death victims in the May
27 2006 Earthquake disaster in Java, Indonesia that killed over 5,000 people. He was in Indonesia on a
business trip and that was how he met his untimely end. My bank management is yet to know about his death, I
knew about it because he was my friend and I am his Account Officer. Peter did not mention any Next of Kin/
Heir when the account was opened, he was not married and no children. Last week my Bank Management
requested that Peter should give instructions on what to do 
 about his funds, if to renew the contract.

I know this will happen and that is why I have been looking for a means to handle the situation, because if my
Bank Directors happens to know that Peter is dead and do not have any Heir, they will take the funds for their
personal use, so I don't want such to happen. That is why I am seeking your co-operation to present you as the
Next of Kin/ Heir to the account, since you are a foreigner and my bank head quarters will release the
account to you. There is no risk involved; the transaction will be executed under a legitimate
arrangement that will protect us from any breach of law. It is better that we claim the money, than allowing
the Bank Directors to take it, they are rich already. I am not a greedy person, so I am suggesting we share the
funds in this ratio, 50/50%, equal sharing. Let 
 me know your mind on this and please do treat this information highly confidential. We shall go over the
details once I receive your urgent response. Please Urgently get back to me through this email address as
soon as possible:
(Continue reading)

Ocean Finance Limited | 28 Aug 02:16 2014
Picon

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Harry Roberts
GVA Abogados. | 15 Aug 15:36 2014
Picon

Transaction XLK-14-TTF/ESP.

Dear Friend,

                  Please acknowledge and accept my proposal.

My name is Barrister Miguel Martinez Moreno, an Attorney at Law, in 
Alicante-Spain.

I am writing to notify you of the unclaimed inheritance deposit of our 
late client, who passed on to Great beyond on August 21st, 2010 in a 
motor accident in auto pista de Alcala Del Henares, Madrid-Spain.

I got your name and email address through a web search engine in my 
quest to get a reliable individual who shall work with me in claiming 
this inheritance deposit since all my efforts to get the biological 
relative has proved abortive.

Conclusively, I await your urgent response to include the following :( 
1).Your full Names & Address. (2).Your Telephone and Fax numbers. 
(3).Your business name if any: for more information on how to release 
the inheritance deposit, amount, procedure and legality of this claim 
send me an email via: gva_abogados <at> aim.com

Have a very nice day my friend!

Regards,
Miguel Martinez Moreno (Esq)
Attorney At Law.
gvaintencia <at> aim.com
Thierry Reding | 13 Aug 12:28 2014
Picon

[PATCH v4 0/8] asm-generic/io.h overhaul

From: Thierry Reding <treding <at> nvidia.com>

Hi,

Here is the fourth version of a series that started out as an attempt to
provide string versions of the read*() and write*() accessors to more
architectures so that drivers can use them portably. The series has
since evolved into a more general cleanup of asm-generic/io.h and the
functions defined therein.

Patch 1 is trivial and removes a redundant redefinition of PCI_IOBASE
from the asm/io.h header on ARC. Patches 2 and 3 remove unnecessary
volatile keywoards from some functions, which is a prerequisite to clean
up some of the functions in subsequent patches.

The xlate_dev_{kmem,mem}_ptr() functions are used to map memory when the
/dev/mem device is accessed. Patches 4 and 5 use more consistent data
types for these functions, which will get a "standard" prototype in the
asm-generic/io.h header in a subsequent patch.

Patch 6 is the bulk of this series. It implements the string variants of
the read*() and write*() accessors and cleans up various other parts of
the asm-generic/io.h header file. Macros are converted to static inline
functions for better type checking. Overriding generic implementations
in architectures is handled more consistently.

Patches 7 and 8, finally, make use of the asm-generic/io.h header on the
32-bit and 64-bit ARM architectures.

This is compile- and runtime-tested on 32-bit and 64-bit ARM and compile
(Continue reading)

Chen Gang | 13 Aug 00:48 2014
Picon

[PATCH v2] arch: Kconfig: Let all little endian architectures define CPU_LITTLE_ENDIAN explicitly

x86 and ia64 are always little endian. And another architectures may be
little endian: mips, sh, powerpc, and m32r (may mark CPU_LITTLE_ENDIAN
explicitly); also arm(64) and c6x (which may be !CPU_BIG_ENDIAN).

Some drivers (e.g. some of "drivers/isdn/hisax") may only support little
endian (CPU_LITTLE_ENDIAN), and some drivers may only support big endian
(!CPU_LITTLE_ENDIAN).

So export all little endian architectures within kernel wide, so can let
Kconfig easier for the modules which only support little endian or only
for big endian (assume !CPU_LITTLE_ENDIAN is same as CPU_BIG_ENDIAN).

Signed-off-by: Chen Gang <gang.chen.5i5j <at> gmail.com>
---
 arch/arm/Kconfig   | 5 +++++
 arch/arm64/Kconfig | 4 ++++
 arch/c6x/Kconfig   | 4 ++++
 arch/ia64/Kconfig  | 3 +++
 arch/x86/Kconfig   | 3 +++
 5 files changed, 19 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c49a775..0510a5d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
 <at>  <at>  -199,6 +199,11  <at>  <at>  config NEED_DMA_MAP_STATE
 config ARCH_SUPPORTS_UPROBES
 	def_bool y

+config CPU_LITTLE_ENDIAN
(Continue reading)

D.Y. CHAN | 9 Aug 15:09 2014
Picon

I hope this e-mãil is still in use


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Thanks in adv.

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