Suman Tripathi | 18 Apr 20:05 2014

[PATCH 1/2] PHY: Add function set_rate to generic PHY framework

This patch adds function set_rate to the generic PHY framework operation
structure. This function can be called to instruct the PHY underlying
layer at specified lane to configure for specified rate.

Signed-off-by: Loc Ho <lho <at> apm.com>
Signed-off-by: Suman Tripathi <stripathi <at> apm.com>
---
 drivers/phy/phy-core.c  | 27 +++++++++++++++++++++++++++
 include/linux/phy/phy.h |  8 ++++++++
 2 files changed, 35 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 645c867..51f82e0 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
 <at>  <at>  -258,6 +258,33  <at>  <at>  int phy_power_off(struct phy *phy)
 EXPORT_SYMBOL_GPL(phy_power_off);

 /**
+ * phy_set_rate - set an specified lane at an specified rate
+ *  <at> phy: phy instance to be set
+ *  <at> lane: zero-based lane index
+ *  <at> rate: operating rate in bps (bits per second)
+ *
+ * Returns 0 if successful, -ENOTSUPP if not supported
+ * -EINVAL if parameter out of range.
+ */
+int phy_set_rate(struct phy *phy, int lane, u64 rate)
+{
+	int ret = 0;
(Continue reading)

Suman Tripathi | 18 Apr 20:03 2014

[PATCH 0/2] PHY: Add SATA Gen1/Gen2 support to the APM X-Gene SoC 15Gbps PHY driver

This patch adds the necessary code to support SATA Gen1/Gen2 for the APM X-Gene
SoC 15Gbps Multi-purpose PHY driver.

Suman Tripathi (2):
  PHY: Add function set_rate to generic PHY framework
  PHY: Add Gen1/Gen2 support for the APM SoC X-Gene SATA PHY driver

 drivers/phy/phy-core.c  | 29 ++++++++++++++++++++++
 drivers/phy/phy-xgene.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h |  8 +++++++
 3 files changed, 101 insertions(+)

--
1.8.2.1

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Shawn Guo | 18 Apr 08:44 2014

[PATCH v2 0/2] ahci: imx: software workaround for phy reset issue

Changes since v1:
 - Do not switch to defines and stay with enums
 - Create a wrapper function imx_phy_crbit_assert() to make the code
   a little shorter and easier for eyes

Shawn Guo (2):
  ahci: imx: add namespace for register enums
  ahci: imx: software workaround for phy reset issue in resume

 drivers/ata/ahci_imx.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 165 insertions(+), 7 deletions(-)

--

-- 
1.8.3.2

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Phillip Susi | 18 Apr 03:19 2014

How to cleanly detach port multiplier ( pmp )


I can write to the delete file in the sysfs node for the scsi disk to
cleanly stop the disk and detach the scsi disk driver, but I can find
no similar way to delete the ata link, the pmp, the master link to the
pmp, and disable the ata port.  How are you supposed to disconnect a
port multiplier without causing the kernel to go into error recovery
because the link went dead and the device vanished?

Alexander Gordeev | 17 Apr 18:06 2014
Picon

[PATCH 0/1] ahci: Do not receive interrupts sent by dummy ports

Tejun, David,

I would expect handle_bad_irq()->print_irq_desc() gets called
if dummy port interrupt arrived. Could be a spurious interrupt
complain as well.

Cc: Tejun Heo <tj <at> kernel.org>
Cc: David Milburn <dmilburn <at> redhat.com>
Cc: linux-ide <at> vger.kernel.org

Alexander Gordeev (1):
  ahci: Do not receive interrupts sent by dummy ports

 drivers/ata/ahci.c |   16 ++++++++++------
 1 files changed, 10 insertions(+), 6 deletions(-)

--

-- 
1.7.7.6

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Alexander Gordeev | 17 Apr 14:13 2014
Picon

[PATCH v2 0/2] ahci: Tweaks to the driver's PCI function

Changes since v1:
	- ahci_is_mrsm() open-coded inside ahci_init_interrupt()
	- changelog elaborated

Cc: linux-ide <at> vger.kernel.org

Alexander Gordeev (2):
  ahci: Ensure "MSI Revert to Single Message" mode is not enforced
  ahci: Use pci_enable_msi_exact() instead of pci_enable_msi_range()

 drivers/ata/ahci.c |   19 ++++++++++++++-----
 drivers/ata/ahci.h |    1 +
 2 files changed, 15 insertions(+), 5 deletions(-)

--

-- 
1.7.7.6

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David Milburn | 16 Apr 18:43 2014
Picon

[PATCH] ahci: do not request irq for dummy port

System may crash in ahci_hw_interrupt() or ahci_thread_fn() when accessing
the interrupt status in a port's private_data if the port is actually a
DUMMY port.

# lspci | grep ATA
00:1f.2 SATA controller: Intel Corporation 82801JI (ICH10 Family) SATA AHCI Controller

# systemctl status kdump (to ensure kdump service is running)
# echo c > /proc/sysrq-trigger

<snip console output for linux-3.15-rc1>
[    9.352080] ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 6 ports 3 Gbps 0x1 impl SATA mode
[    9.352084] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ccc 
[    9.368155] Console: switching to colour frame buffer device 128x48
[    9.439759] mgag200 0000:11:00.0: fb0: mgadrmfb frame buffer device
[    9.446765] mgag200 0000:11:00.0: registered panic notifier
[    9.470166] scsi1 : ahci
[    9.479166] scsi2 : ahci
[    9.488172] scsi3 : ahci
[    9.497174] scsi4 : ahci
[    9.506175] scsi5 : ahci
[    9.515174] scsi6 : ahci
[    9.518181] ata1: SATA max UDMA/133 abar m2048 <at> 0x95c00000 port 0x95c00100 irq 91
[    9.526448] ata2: DUMMY
[    9.529182] ata3: DUMMY
[    9.531916] ata4: DUMMY
[    9.534650] ata5: DUMMY
[    9.537382] ata6: DUMMY
[    9.576196] [drm] Initialized mgag200 1.0.0 20110418 for 0000:11:00.0 on minor 0
[    9.845257] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
(Continue reading)

Russell King - ARM Linux | 16 Apr 10:42 2014
Picon

[PATCH 0/5] imx ahci DT updates + cubox-i eSATA support

The following series adds several DT properties to the iMX ahci driver,
which are necessary to configure the electrical characteristics of the
SATA interface.

The required electrical characteristics are board dependent, so the
existing solution where the parameters are hard-coded for the first
board(s) which came along is completely rediculous, and cause their
own set of problems: we have to default to these parameters when no
properties are given, and it means we have to use negative properties
to turn stuff off rather than positive properties to enable features.

Yes, I know that the required Documentation/devicetree file is missing,
I couldn't find the existing file to update for this driver with the
new properties. :)

 arch/arm/boot/dts/imx6q-cubox-i.dts |   4 +
 drivers/ata/ahci_imx.c              | 188 ++++++++++++++++++++++++++++++++++--
 2 files changed, 184 insertions(+), 8 deletions(-)

--

-- 
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
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Peter Foley | 15 Apr 19:50 2014

[PATCH] ata: fix kconfig selection warning

When building with COMPILE_TEST, AHCI_XGENE is enabled even though
PHY_XGENE (which it selects) requires OF to be enabled.
Fix this by adding a dependency on OF to AHCI_XGENE.

warning: (AHCI_XGENE) selects PHY_XGENE which has unmet direct
dependencies (HAS_IOMEM && OF && (ARM64 || COMPILE_TEST))

Signed-off-by: Peter Foley <pefoley2 <at> pefoley.com>
---
 drivers/ata/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 20e03a7..071f399 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
 <at>  <at>  -134,7 +134,7  <at>  <at>  config AHCI_SUNXI

 config AHCI_XGENE
 	tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
-	depends on ARM64 || COMPILE_TEST
+	depends on OF && (ARM64 || COMPILE_TEST)
 	select PHY_XGENE
 	help
 	 This option enables support for APM X-Gene SoC SATA host controller.
--

-- 
1.9.2

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(Continue reading)

Thomas Petazzoni | 15 Apr 17:00 2014

[PATCHv3 0/5] Support for Marvell AHCI interface on Armada 38x

Hello,

The Marvell Armada 38x ARM processors use an AHCI compatible interface
for SATA (in replacement of the Marvell-specific SATA interface,
handled by the sata_mv driver). However, like all DMA-capable Marvell
interfaces, some specific MBus window configuration must be done, so a
small specific glue layer is needed, which relies on the recently
introduced libahci_platform.c.

Changes since v2:

 * Added Acked-by from Andrew Lunn <andrew <at> lunn.ch> on the first
   patch.

 * Added comment in the code to explain why we don't have
   suspend/resume support for now. Suggested by Bartlomiej
   Zolnierkiewicz.

 * Added a ahci_mvebu_regret_option() function which enables the
   vendor-specific regret bit, which allows to solve a potential
   deadlock situation in the AHCI interface.

Changes since v1:

 * Rebased on top of v3.15-rc1

 * Added a preliminary patch that orders alphabetically the list of
   compatible strings in the DT binding document
   ahci-platform.txt. Suggested by Andrew Lunn.

(Continue reading)

Shawn Guo | 15 Apr 04:41 2014

[PATCH 1/2] ahci: imx: use macros to define registers and bits

Comparing to enums, macros are more conventional to be used for
registers and bits definition.  Let's switch to macros.

While at it, the names of the registers and bit-fields are updated to
have proper namespace prefix and match the hardware reference manual.

No functional change is involved.

Signed-off-by: Shawn Guo <shawn.guo <at> freescale.com>
---
 drivers/ata/ahci_imx.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index 497c7ab..39629b4 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
 <at>  <at>  -28,11 +28,9  <at>  <at> 
 #include <linux/libata.h>
 #include "ahci.h"

-enum {
-	PORT_PHY_CTL = 0x178,			/* Port0 PHY Control */
-	PORT_PHY_CTL_PDDQ_LOC = 0x100000,	/* PORT_PHY_CTL bits */
-	HOST_TIMER1MS = 0xe0,			/* Timer 1-ms */
-};
+#define IMX_SATA_TIMER1MS			0x00e0
+#define IMX_SATA_P0PHYCR			0x0178
+#define  P0PHYCR_TEST_PDDQ			(1 << 20)

(Continue reading)


Gmane