1 Aug 2010 08:42
[4751] trunk/binutils-2.17/sim/bfin: sim: add gptimer/ ppi stubs so default bf527-ezkit can boot up (has a splash screen)
Revision 4751
Author vapier
Date 2010-08-01 02:42:14 -0400 (Sun, 01 Aug 2010)
Log Message
sim: add gptimer/ppi stubs so default bf527-ezkit can boot up (has a splash screen)Modified Paths
- trunk/binutils-2.17/sim/bfin/Makefile.in
- trunk/binutils-2.17/sim/bfin/configure.ac
- trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c
- trunk/binutils-2.17/sim/bfin/machs.c
Added Paths
Diff
Modified: trunk/binutils-2.17/sim/bfin/Makefile.in (4750 => 4751)
--- trunk/binutils-2.17/sim/bfin/Makefile.in 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/Makefile.in 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -59,8 +59,10 <at> <at> dv-bfin_ebiu_sdc.o: dv-bfin_ebiu_sdc.c devices.h $(INCLUDE) dv-bfin_emac.o: dv-bfin_emac.c devices.h $(INCLUDE) dv-bfin_evt.o: dv-bfin_evt.c devices.h $(INCLUDE) +dv-bfin_gptimer.o: dv-bfin_gptimer.c devices.h $(INCLUDE) dv-bfin_mmu.o: dv-bfin_mmu.c devices.h $(INCLUDE) dv-bfin_pll.o: dv-bfin_pll.c devices.h $(INCLUDE) +dv-bfin_ppi.o: dv-bfin_ppi.c devices.h $(INCLUDE) dv-bfin_rtc.o: dv-bfin_rtc.c devices.h $(INCLUDE) dv-bfin_sic.o: dv-bfin_sic.c devices.h $(INCLUDE) dv-bfin_trace.o: dv-bfin_trace.c devices.h $(INCLUDE)Modified: trunk/binutils-2.17/sim/bfin/configure.ac (4750 => 4751)
--- trunk/binutils-2.17/sim/bfin/configure.ac 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/configure.ac 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -26,8 +26,10 <at> <at> bfin_ebiu_sdc \ bfin_emac \ bfin_evt \ + bfin_gptimer \ bfin_mmu \ bfin_pll \ + bfin_ppi \ bfin_rtc \ bfin_sic \ bfin_trace \Added: trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.c (0 => 4751)
--- trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.c (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.c 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -0,0 +1,182 <at> <at> +/* Blackfin General Purpose Timers (GPtimer) model + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_gptimer.h" + +/* XXX: This is merely a stub. */ + +struct bfin_gptimer +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(config); + bu32 counter, period, width; +}; +#define mmr_base() offsetof(struct bfin_gptimer, config) +#define mmr_offset(mmr) (offsetof(struct bfin_gptimer, mmr) - mmr_base()) + +static const char * const mmr_names[] = { + "TIMER_CONFIG", "TIMER_COUNTER", "TIMER_PERIOD", "TIMER_WIDTH", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_gptimer_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gptimer *gptimer = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - gptimer->base; + valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(config): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + break; + case mmr_offset(counter): + case mmr_offset(period): + case mmr_offset(width): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + *value32p = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_gptimer_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gptimer *gptimer = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - gptimer->base; + valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(config): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + dv_store_2 (dest, *value16p); + break; + case mmr_offset(counter): + case mmr_offset(period): + case mmr_offset(width): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + dv_store_4 (dest, *value32p); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_gptimer_ports[] = { + { "stat", 0, 0, output_port, }, +}; + +static void +attach_bfin_gptimer_regs (struct hw *me, struct bfin_gptimer *gptimer) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_GPTIMER_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPTIMER_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + gptimer->base = attach_address; +} + +static void +bfin_gptimer_finish (struct hw *me) +{ + struct bfin_gptimer *gptimer; + + gptimer = HW_ZALLOC (me, struct bfin_gptimer); + + set_hw_data (me, gptimer); + set_hw_io_read_buffer (me, bfin_gptimer_io_read_buffer); + set_hw_io_write_buffer (me, bfin_gptimer_io_write_buffer); + set_hw_ports (me, bfin_gptimer_ports); + + attach_bfin_gptimer_regs (me, gptimer); +} + +const struct hw_descriptor dv_bfin_gptimer_descriptor[] = { + {"bfin_gptimer", bfin_gptimer_finish,}, + {NULL, NULL}, +};Added: trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.h (0 => 4751)
--- trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.h (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.h 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -0,0 +1,27 <at> <at> +/* Blackfin General Purpose Timers (GPtimer) model + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#ifndef DV_BFIN_GPTIMER_H +#define DV_BFIN_GPTIMER_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_GPTIMER_SIZE (4 * 4) + +#endifAdded: trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.c (0 => 4751)
--- trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.c (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.c 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -0,0 +1,198 <at> <at> +/* Blackfin Parallel Port Interface (PPI) model + For "old style" PPIs on BF53x/etc... parts. + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_ppi.h" + +/* XXX: This is merely a stub. Maybe put a simple SDL window up ? */ + +struct bfin_ppi +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(control); + bu16 BFIN_MMR_16(status); + bu16 BFIN_MMR_16(count); + bu16 BFIN_MMR_16(delay); + bu16 BFIN_MMR_16(frame); +}; +#define mmr_base() offsetof(struct bfin_ppi, control) +#define mmr_offset(mmr) (offsetof(struct bfin_ppi, mmr) - mmr_base()) + +static const char * const mmr_names[] = { + "PPI_CONTROL", "PPI_STATUS", "PPI_COUNT", "PPI_DELAY", "PPI_FRAME", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_ppi_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ppi *ppi = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - ppi->base; + valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(control): + case mmr_offset(count): + case mmr_offset(delay): + case mmr_offset(frame): + *valuep = value; + break; + case mmr_offset(status): + dv_w1c_2 (valuep, value, (1 << 10)); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ppi_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ppi *ppi = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - ppi->base; + valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(control): + case mmr_offset(count): + case mmr_offset(delay): + case mmr_offset(frame): + case mmr_offset(status): + dv_store_2 (dest, *valuep); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ppi_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return 0; +} + +static unsigned +bfin_ppi_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_ppi *ppi = hw_data (me); + unsigned ret; + + HW_TRACE_DMA_WRITE (); + + return 0; +} + +static const struct hw_port_descriptor bfin_ppi_ports[] = { + { "stat", 0, 0, output_port, }, +}; + +static void +attach_bfin_ppi_regs (struct hw *me, struct bfin_ppi *ppi) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_PPI_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PPI_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + ppi->base = attach_address; +} + +static void +bfin_ppi_finish (struct hw *me) +{ + struct bfin_ppi *ppi; + + ppi = HW_ZALLOC (me, struct bfin_ppi); + + set_hw_data (me, ppi); + set_hw_io_read_buffer (me, bfin_ppi_io_read_buffer); + set_hw_io_write_buffer (me, bfin_ppi_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_ppi_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_ppi_dma_write_buffer); + set_hw_ports (me, bfin_ppi_ports); + + attach_bfin_ppi_regs (me, ppi); +} + +const struct hw_descriptor dv_bfin_ppi_descriptor[] = { + {"bfin_ppi", bfin_ppi_finish,}, + {NULL, NULL}, +};Added: trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.h (0 => 4751)
--- trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.h (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.h 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -0,0 +1,28 <at> <at> +/* Blackfin Parallel Port Interface (PPI) model + For "old style" PPIs on BF53x/etc... parts. + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#ifndef DV_BFIN_PPI_H +#define DV_BFIN_PPI_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_PPI_SIZE (4 * 5) + +#endifModified: trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c (4750 => 4751)
--- trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -191,7 +191,7 <at> <at> { "emac_stat", 21, 0, input_port, }, { "sport <at> 0_stat", 22, 0, input_port, }, { "sport <at> 1_stat", 23, 0, input_port, }, - { "ppi_stat", 24, 0, input_port, }, + { "ppi", 24, 0, input_port, }, { "spi_stat", 25, 0, input_port, }, { "uart <at> 0_stat", 26, 0, input_port, }, { "uart <at> 1_stat", 27, 0, input_port, }, <at> <at> -213,14 +213,14 <at> <at> { "porth_irq_a", 171, 0, input_port, }, { "dma2", 180, 0, input_port, }, { "porth_irq_b", 181, 0, input_port, }, - { "timer0", 190, 0, input_port, }, - { "timer1", 200, 0, input_port, }, - { "timer0", 210, 0, input_port, }, - { "timer3", 220, 0, input_port, }, - { "timer4", 230, 0, input_port, }, - { "timer5", 240, 0, input_port, }, - { "timer6", 250, 0, input_port, }, - { "timer7", 260, 0, input_port, }, + { "gptimer <at> 0", 190, 0, input_port, }, + { "gptimer <at> 1", 200, 0, input_port, }, + { "gptimer <at> 2", 210, 0, input_port, }, + { "gptimer <at> 3", 220, 0, input_port, }, + { "gptimer <at> 4", 230, 0, input_port, }, + { "gptimer <at> 5", 240, 0, input_port, }, + { "gptimer <at> 6", 250, 0, input_port, }, + { "gptimer <at> 7", 260, 0, input_port, }, { "portf_irq_a", 270, 0, input_port, }, { "portg_irq_a", 271, 0, input_port, }, { "portg_irq_b", 280, 0, input_port, },Modified: trunk/binutils-2.17/sim/bfin/machs.c (4750 => 4751)
--- trunk/binutils-2.17/sim/bfin/machs.c 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/machs.c 2010-08-01 06:42:14 UTC (rev 4751) <at> <at> -36,7 +36,9 <at> <at> #include "dv-bfin_ebiu_sdc.h" #include "dv-bfin_emac.h" #include "dv-bfin_evt.h" +#include "dv-bfin_gptimer.h" #include "dv-bfin_mmu.h" +#include "dv-bfin_ppi.h" #include "dv-bfin_pll.h" #include "dv-bfin_rtc.h" #include "dv-bfin_sic.h" <at> <at> -104,6 +106,7 <at> <at> #define bf518_chipid bf51x_chipid static const struct bfin_memory_layout bf51x_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI0 stub */ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ <at> <at> -122,14 +125,32 <at> <at> #define bf516_mem bf51x_mem #define bf518_mem bf51x_mem static const struct bfin_dev_layout bf512_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), }; #define bf514_dev bf512_dev static const struct bfin_dev_layout bf516_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), DEVICE (0, 0x20, "bfin_emac/eth_phy"), }; #define bf518_dev bf516_dev <at> <at> -142,6 +163,7 <at> <at> #define bf527_chipid bf523_chipid static const struct bfin_memory_layout bf52x_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ <at> <at> -162,16 +184,34 <at> <at> #define bf526_mem bf52x_mem #define bf527_mem bf52x_mem static const struct bfin_dev_layout bf522_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), }; #define bf523_dev bf522_dev #define bf524_dev bf522_dev #define bf525_dev bf522_dev static const struct bfin_dev_layout bf526_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), DEVICE (0, 0x20, "bfin_emac/eth_phy"), }; #define bf527_dev bf526_dev <at> <at> -181,6 +221,7 <at> <at> #define bf533_chipid bf531_chipid static const struct bfin_memory_layout bf531_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ + LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */ LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ <at> <at> -188,6 +229,7 <at> <at> }; static const struct bfin_memory_layout bf532_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ + LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */ LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ <at> <at> -197,6 +239,7 <at> <at> }; static const struct bfin_memory_layout bf533_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ + LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */ LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ <at> <at> -208,7 +251,11 <at> <at> LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ }; static const struct bfin_dev_layout bf533_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), }; #define bf531_dev bf533_dev #define bf532_dev bf533_dev <at> <at> -218,6 +265,7 <at> <at> #define bf537_chipid bf536_chipid static const struct bfin_memory_layout bf534_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ <at> <at> -233,6 +281,7 <at> <at> }; static const struct bfin_memory_layout bf536_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ <at> <at> -246,6 +295,7 <at> <at> }; static const struct bfin_memory_layout bf537_mem[] = { LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ + LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ <at> <at> -260,13 +310,31 <at> <at> LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ }; static const struct bfin_dev_layout bf534_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), }; static const struct bfin_dev_layout bf537_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), DEVICE (0, 0x20, "bfin_emac/eth_phy"), }; #define bf536_dev bf537_dev <at> <at> -292,9 +360,18 <at> <at> }; #define bf539_mem bf538_mem static const struct bfin_dev_layout bf538_dev[] = { - DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart <at> 2"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart <at> 2"), }; #define bf539_dev bf538_dev <at> <at> -357,6 +434,8 <at> <at> }; static const struct bfin_dev_layout bf561_dev[] = { DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi <at> 0"), + DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi <at> 1"), }; static const struct bfin_model_data bfin_model_data[] = <at> <at> -475,6 +554,16 <at> <at> sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac <at> 0", dev->dev, sint); sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint); } + else if (!strncmp (dev->dev, "bfin_gptimer", 12)) + { + const char *sint = dev->dev + 5; + sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint); + } + else if (!strncmp (dev->dev, "bfin_ppi", 7)) + { + const char *sint = dev->dev + 5; + sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint); + } } done:<div> <div> Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&path=/&view=rev&root=toolchain&revision=4751">4751</a> Author <a href="http://blackfin.uclinux.org/gf/user/vapier/">vapier</a> Date 2010-08-01 02:42:14 -0400 (Sun, 01 Aug 2010) <h3>Log Message</h3> sim: add gptimer/ppi stubs so default bf527-ezkit can boot up (has a splash screen) <h3>Modified Paths</h3> <ul> <li><a href="#trunkbinutils217simbfinMakefilein">trunk/binutils-2.17/sim/bfin/Makefile.in</a></li> <li><a href="#trunkbinutils217simbfinconfigureac">trunk/binutils-2.17/sim/bfin/configure.ac</a></li> <li><a href="#trunkbinutils217simbfindvbfin_sicc">trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c</a></li> <li><a href="#trunkbinutils217simbfinmachsc">trunk/binutils-2.17/sim/bfin/machs.c</a></li> </ul> <h3>Added Paths</h3> <ul> <li><a href="#trunkbinutils217simbfindvbfin_gptimerc">trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.c</a></li> <li><a href="#trunkbinutils217simbfindvbfin_gptimerh">trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.h</a></li> <li><a href="#trunkbinutils217simbfindvbfin_ppic">trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.c</a></li> <li><a href="#trunkbinutils217simbfindvbfin_ppih">trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.h</a></li> </ul> </div> <div> <h3>Diff</h3> <a></a> <div class="modfile"> <h4>Modified: trunk/binutils-2.17/sim/bfin/Makefile.in (4750 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/Makefile.in 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/Makefile.in 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -59,8 +59,10 <at> <at> </span><span class="cx"> dv-bfin_ebiu_sdc.o: dv-bfin_ebiu_sdc.c devices.h $(INCLUDE) </span><span class="cx"> dv-bfin_emac.o: dv-bfin_emac.c devices.h $(INCLUDE) </span><span class="cx"> dv-bfin_evt.o: dv-bfin_evt.c devices.h $(INCLUDE) </span>+dv-bfin_gptimer.o: dv-bfin_gptimer.c devices.h $(INCLUDE) <span class="cx"> dv-bfin_mmu.o: dv-bfin_mmu.c devices.h $(INCLUDE) </span><span class="cx"> dv-bfin_pll.o: dv-bfin_pll.c devices.h $(INCLUDE) </span>+dv-bfin_ppi.o: dv-bfin_ppi.c devices.h $(INCLUDE) <span class="cx"> dv-bfin_rtc.o: dv-bfin_rtc.c devices.h $(INCLUDE) </span><span class="cx"> dv-bfin_sic.o: dv-bfin_sic.c devices.h $(INCLUDE) </span><span class="cx"> dv-bfin_trace.o: dv-bfin_trace.c devices.h $(INCLUDE) </span></span> </div> <a></a> <div class="modfile"> <h4>Modified: trunk/binutils-2.17/sim/bfin/configure.ac (4750 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/configure.ac 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/configure.ac 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -26,8 +26,10 <at> <at> </span><span class="cx"> bfin_ebiu_sdc \ </span><span class="cx"> bfin_emac \ </span><span class="cx"> bfin_evt \ </span>+ bfin_gptimer \ <span class="cx"> bfin_mmu \ </span><span class="cx"> bfin_pll \ </span>+ bfin_ppi \ <span class="cx"> bfin_rtc \ </span><span class="cx"> bfin_sic \ </span><span class="cx"> bfin_trace \ </span></span> </div> <a></a> <div class="addfile"> <h4>Added: trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.c (0 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.c (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.c 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -0,0 +1,182 <at> <at> </span>+/* Blackfin General Purpose Timers (GPtimer) model + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_gptimer.h" + +/* XXX: This is merely a stub. */ + +struct bfin_gptimer +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(config); + bu32 counter, period, width; +}; +#define mmr_base() offsetof(struct bfin_gptimer, config) +#define mmr_offset(mmr) (offsetof(struct bfin_gptimer, mmr) - mmr_base()) + +static const char * const mmr_names[] = { + "TIMER_CONFIG", "TIMER_COUNTER", "TIMER_PERIOD", "TIMER_WIDTH", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_gptimer_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gptimer *gptimer = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + + mmr_off = addr - gptimer->base; + valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + switch (mmr_off) + { + case mmr_offset(config): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + *value16p = value; + break; + case mmr_offset(counter): + case mmr_offset(period): + case mmr_offset(width): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + *value32p = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_gptimer_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gptimer *gptimer = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - gptimer->base; + valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + switch (mmr_off) + { + case mmr_offset(config): + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + dv_store_2 (dest, *value16p); + break; + case mmr_offset(counter): + case mmr_offset(period): + case mmr_offset(width): + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + dv_store_4 (dest, *value32p); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_gptimer_ports[] = { + { "stat", 0, 0, output_port, }, +}; + +static void +attach_bfin_gptimer_regs (struct hw *me, struct bfin_gptimer *gptimer) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, &reg)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + &reg.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me); + + if (attach_size != BFIN_MMR_GPTIMER_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPTIMER_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + gptimer->base = attach_address; +} + +static void +bfin_gptimer_finish (struct hw *me) +{ + struct bfin_gptimer *gptimer; + + gptimer = HW_ZALLOC (me, struct bfin_gptimer); + + set_hw_data (me, gptimer); + set_hw_io_read_buffer (me, bfin_gptimer_io_read_buffer); + set_hw_io_write_buffer (me, bfin_gptimer_io_write_buffer); + set_hw_ports (me, bfin_gptimer_ports); + + attach_bfin_gptimer_regs (me, gptimer); +} + +const struct hw_descriptor dv_bfin_gptimer_descriptor[] = { + {"bfin_gptimer", bfin_gptimer_finish,}, + {NULL, NULL}, +}; </span> </div> <a></a> <div class="addfile"> <h4>Added: trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.h (0 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.h (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_gptimer.h 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -0,0 +1,27 <at> <at> </span>+/* Blackfin General Purpose Timers (GPtimer) model + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#ifndef DV_BFIN_GPTIMER_H +#define DV_BFIN_GPTIMER_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_GPTIMER_SIZE (4 * 4) + +#endif </span> </div> <a></a> <div class="addfile"> <h4>Added: trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.c (0 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.c (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.c 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -0,0 +1,198 <at> <at> </span>+/* Blackfin Parallel Port Interface (PPI) model + For "old style" PPIs on BF53x/etc... parts. + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_ppi.h" + +/* XXX: This is merely a stub. Maybe put a simple SDL window up ? */ + +struct bfin_ppi +{ + /* This top portion matches common dv_bfin struct. */ + bu32 base; + struct hw *dma_master; + bool acked; + + struct hw_event *handler; + char saved_byte; + int saved_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(control); + bu16 BFIN_MMR_16(status); + bu16 BFIN_MMR_16(count); + bu16 BFIN_MMR_16(delay); + bu16 BFIN_MMR_16(frame); +}; +#define mmr_base() offsetof(struct bfin_ppi, control) +#define mmr_offset(mmr) (offsetof(struct bfin_ppi, mmr) - mmr_base()) + +static const char * const mmr_names[] = { + "PPI_CONTROL", "PPI_STATUS", "PPI_COUNT", "PPI_DELAY", "PPI_FRAME", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_ppi_io_write_buffer (struct hw *me, const void *source, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ppi *ppi = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *valuep; + + value = dv_load_2 (source); + mmr_off = addr - ppi->base; + valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off); + + HW_TRACE_WRITE (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(control): + case mmr_offset(count): + case mmr_offset(delay): + case mmr_offset(frame): + *valuep = value; + break; + case mmr_offset(status): + dv_w1c_2 (valuep, value, (1 << 10)); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ppi_io_read_buffer (struct hw *me, void *dest, + int space, address_word addr, unsigned nr_bytes) +{ + struct bfin_ppi *ppi = hw_data (me); + bu32 mmr_off; + bu16 *valuep; + + mmr_off = addr - ppi->base; + valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off); + + HW_TRACE_READ (); + + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(control): + case mmr_offset(count): + case mmr_offset(delay): + case mmr_offset(frame): + case mmr_offset(status): + dv_store_2 (dest, *valuep); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static unsigned +bfin_ppi_dma_read_buffer (struct hw *me, void *dest, int space, + unsigned_word addr, unsigned nr_bytes) +{ + HW_TRACE_DMA_READ (); + return 0; +} + +static unsigned +bfin_ppi_dma_write_buffer (struct hw *me, const void *source, + int space, unsigned_word addr, + unsigned nr_bytes, + int violate_read_only_section) +{ + struct bfin_ppi *ppi = hw_data (me); + unsigned ret; + + HW_TRACE_DMA_WRITE (); + + return 0; +} + +static const struct hw_port_descriptor bfin_ppi_ports[] = { + { "stat", 0, 0, output_port, }, +}; + +static void +attach_bfin_ppi_regs (struct hw *me, struct bfin_ppi *ppi) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, &reg)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + &reg.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me); + + if (attach_size != BFIN_MMR_PPI_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PPI_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + ppi->base = attach_address; +} + +static void +bfin_ppi_finish (struct hw *me) +{ + struct bfin_ppi *ppi; + + ppi = HW_ZALLOC (me, struct bfin_ppi); + + set_hw_data (me, ppi); + set_hw_io_read_buffer (me, bfin_ppi_io_read_buffer); + set_hw_io_write_buffer (me, bfin_ppi_io_write_buffer); + set_hw_dma_read_buffer (me, bfin_ppi_dma_read_buffer); + set_hw_dma_write_buffer (me, bfin_ppi_dma_write_buffer); + set_hw_ports (me, bfin_ppi_ports); + + attach_bfin_ppi_regs (me, ppi); +} + +const struct hw_descriptor dv_bfin_ppi_descriptor[] = { + {"bfin_ppi", bfin_ppi_finish,}, + {NULL, NULL}, +}; </span> </div> <a></a> <div class="addfile"> <h4>Added: trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.h (0 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.h (rev 0) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_ppi.h 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -0,0 +1,28 <at> <at> </span>+/* Blackfin Parallel Port Interface (PPI) model + For "old style" PPIs on BF53x/etc... parts. + + Copyright (C) 2010 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#ifndef DV_BFIN_PPI_H +#define DV_BFIN_PPI_H + +/* XXX: This should be pushed into the model data. */ +#define BFIN_MMR_PPI_SIZE (4 * 5) + +#endif </span> </div> <a></a> <div class="modfile"> <h4>Modified: trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c (4750 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/dv-bfin_sic.c 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -191,7 +191,7 <at> <at> </span><span class="cx"> { "emac_stat", 21, 0, input_port, }, </span><span class="cx"> { "sport <at> 0_stat", 22, 0, input_port, }, </span><span class="cx"> { "sport <at> 1_stat", 23, 0, input_port, }, </span>- { "ppi_stat", 24, 0, input_port, }, + { "ppi", 24, 0, input_port, }, <span class="cx"> { "spi_stat", 25, 0, input_port, }, </span><span class="cx"> { "uart <at> 0_stat", 26, 0, input_port, }, </span><span class="cx"> { "uart <at> 1_stat", 27, 0, input_port, }, </span><span class="lines"> <at> <at> -213,14 +213,14 <at> <at> </span><span class="cx"> { "porth_irq_a", 171, 0, input_port, }, </span><span class="cx"> { "dma2", 180, 0, input_port, }, </span><span class="cx"> { "porth_irq_b", 181, 0, input_port, }, </span>- { "timer0", 190, 0, input_port, }, - { "timer1", 200, 0, input_port, }, - { "timer0", 210, 0, input_port, }, - { "timer3", 220, 0, input_port, }, - { "timer4", 230, 0, input_port, }, - { "timer5", 240, 0, input_port, }, - { "timer6", 250, 0, input_port, }, - { "timer7", 260, 0, input_port, }, + { "gptimer <at> 0", 190, 0, input_port, }, + { "gptimer <at> 1", 200, 0, input_port, }, + { "gptimer <at> 2", 210, 0, input_port, }, + { "gptimer <at> 3", 220, 0, input_port, }, + { "gptimer <at> 4", 230, 0, input_port, }, + { "gptimer <at> 5", 240, 0, input_port, }, + { "gptimer <at> 6", 250, 0, input_port, }, + { "gptimer <at> 7", 260, 0, input_port, }, <span class="cx"> { "portf_irq_a", 270, 0, input_port, }, </span><span class="cx"> { "portg_irq_a", 271, 0, input_port, }, </span><span class="cx"> { "portg_irq_b", 280, 0, input_port, }, </span></span> </div> <a></a> <div class="modfile"> <h4>Modified: trunk/binutils-2.17/sim/bfin/machs.c (4750 => 4751)</h4> <span> <span class="info">--- trunk/binutils-2.17/sim/bfin/machs.c 2010-07-31 05:15:31 UTC (rev 4750) +++ trunk/binutils-2.17/sim/bfin/machs.c 2010-08-01 06:42:14 UTC (rev 4751) </span><span class="lines"> <at> <at> -36,7 +36,9 <at> <at> </span><span class="cx"> #include "dv-bfin_ebiu_sdc.h" </span><span class="cx"> #include "dv-bfin_emac.h" </span><span class="cx"> #include "dv-bfin_evt.h" </span>+#include "dv-bfin_gptimer.h" <span class="cx"> #include "dv-bfin_mmu.h" </span>+#include "dv-bfin_ppi.h" <span class="cx"> #include "dv-bfin_pll.h" </span><span class="cx"> #include "dv-bfin_rtc.h" </span><span class="cx"> #include "dv-bfin_sic.h" </span><span class="lines"> <at> <at> -104,6 +106,7 <at> <at> </span><span class="cx"> #define bf518_chipid bf51x_chipid </span><span class="cx"> static const struct bfin_memory_layout bf51x_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI0 stub */ </span>+ LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ </span><span class="cx"> LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ </span><span class="cx"> LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ </span><span class="lines"> <at> <at> -122,14 +125,32 <at> <at> </span><span class="cx"> #define bf516_mem bf51x_mem </span><span class="cx"> #define bf518_mem bf51x_mem </span><span class="cx"> static const struct bfin_dev_layout bf512_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), <span class="cx"> }; </span><span class="cx"> #define bf514_dev bf512_dev </span><span class="cx"> static const struct bfin_dev_layout bf516_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), <span class="cx"> DEVICE (0, 0x20, "bfin_emac/eth_phy"), </span><span class="cx"> }; </span><span class="cx"> #define bf518_dev bf516_dev </span><span class="lines"> <at> <at> -142,6 +163,7 <at> <at> </span><span class="cx"> #define bf527_chipid bf523_chipid </span><span class="cx"> static const struct bfin_memory_layout bf52x_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ </span>+ LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ </span><span class="cx"> LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ </span><span class="cx"> LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ </span><span class="lines"> <at> <at> -162,16 +184,34 <at> <at> </span><span class="cx"> #define bf526_mem bf52x_mem </span><span class="cx"> #define bf527_mem bf52x_mem </span><span class="cx"> static const struct bfin_dev_layout bf522_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), <span class="cx"> }; </span><span class="cx"> #define bf523_dev bf522_dev </span><span class="cx"> #define bf524_dev bf522_dev </span><span class="cx"> #define bf525_dev bf522_dev </span><span class="cx"> static const struct bfin_dev_layout bf526_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), <span class="cx"> DEVICE (0, 0x20, "bfin_emac/eth_phy"), </span><span class="cx"> }; </span><span class="cx"> #define bf527_dev bf526_dev </span><span class="lines"> <at> <at> -181,6 +221,7 <at> <at> </span><span class="cx"> #define bf533_chipid bf531_chipid </span><span class="cx"> static const struct bfin_memory_layout bf531_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ </span>+ LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */ </span><span class="cx"> LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ </span><span class="cx"> LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ </span><span class="lines"> <at> <at> -188,6 +229,7 <at> <at> </span><span class="cx"> }; </span><span class="cx"> static const struct bfin_memory_layout bf532_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ </span>+ LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */ </span><span class="cx"> LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ </span><span class="cx"> LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ </span><span class="lines"> <at> <at> -197,6 +239,7 <at> <at> </span><span class="cx"> }; </span><span class="cx"> static const struct bfin_memory_layout bf533_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ </span>+ LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */ </span><span class="cx"> LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ </span><span class="cx"> LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ </span><span class="lines"> <at> <at> -208,7 +251,11 <at> <at> </span><span class="cx"> LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ </span><span class="cx"> }; </span><span class="cx"> static const struct bfin_dev_layout bf533_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), <span class="cx"> }; </span><span class="cx"> #define bf531_dev bf533_dev </span><span class="cx"> #define bf532_dev bf533_dev </span><span class="lines"> <at> <at> -218,6 +265,7 <at> <at> </span><span class="cx"> #define bf537_chipid bf536_chipid </span><span class="cx"> static const struct bfin_memory_layout bf534_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ </span>+ LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ </span><span class="cx"> LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ </span><span class="cx"> LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ </span><span class="lines"> <at> <at> -233,6 +281,7 <at> <at> </span><span class="cx"> }; </span><span class="cx"> static const struct bfin_memory_layout bf536_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ </span>+ LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ </span><span class="cx"> LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ </span><span class="cx"> LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ </span><span class="lines"> <at> <at> -246,6 +295,7 <at> <at> </span><span class="cx"> }; </span><span class="cx"> static const struct bfin_memory_layout bf537_mem[] = { </span><span class="cx"> LAYOUT (0xFFC00500, 0x20, read_write), /* SPI stub */ </span>+ LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ <span class="cx"> LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */ </span><span class="cx"> LAYOUT (0xFFC01400, 0x90, read_write), /* TWI stub */ </span><span class="cx"> LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */ </span><span class="lines"> <at> <at> -260,13 +310,31 <at> <at> </span><span class="cx"> LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ </span><span class="cx"> }; </span><span class="cx"> static const struct bfin_dev_layout bf534_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), <span class="cx"> }; </span><span class="cx"> static const struct bfin_dev_layout bf537_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), <span class="cx"> DEVICE (0, 0x20, "bfin_emac/eth_phy"), </span><span class="cx"> }; </span><span class="cx"> #define bf536_dev bf537_dev </span><span class="lines"> <at> <at> -292,9 +360,18 <at> <at> </span><span class="cx"> }; </span><span class="cx"> #define bf539_mem bf538_mem </span><span class="cx"> static const struct bfin_dev_layout bf538_dev[] = { </span>- DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), - DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), - DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart <at> 2"), + DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), + DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 0"), + DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 1"), + DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 2"), + DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 3"), + DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 4"), + DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 5"), + DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 6"), + DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer <at> 7"), + DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi"), + DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart <at> 1"), + DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart <at> 2"), <span class="cx"> }; </span><span class="cx"> #define bf539_dev bf538_dev </span><span class="cx"> </span><span class="lines"> <at> <at> -357,6 +434,8 <at> <at> </span><span class="cx"> }; </span><span class="cx"> static const struct bfin_dev_layout bf561_dev[] = { </span><span class="cx"> DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart <at> 0"), </span>+ DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi <at> 0"), + DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi <at> 1"), <span class="cx"> }; </span><span class="cx"> </span><span class="cx"> static const struct bfin_model_data bfin_model_data[] = </span><span class="lines"> <at> <at> -475,6 +554,16 <at> <at> </span><span class="cx"> sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac <at> 0", dev->dev, sint); </span><span class="cx"> sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint); </span><span class="cx"> } </span>+ else if (!strncmp (dev->dev, "bfin_gptimer", 12)) + { + const char *sint = dev->dev + 5; + sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint); + } + else if (!strncmp (dev->dev, "bfin_ppi", 7)) + { + const char *sint = dev->dev + 5; + sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint); + } <span class="cx"> } </span><span class="cx"> </span><span class="cx"> done: </span></span> </div> </div> </div>
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