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jiez | 1 Apr 2009 11:47
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[3306] trunk/uClibc/include/libc-symbols.h: Fix bug [#4974] Make link_warning work with targets which have symbol prefix.

Revision 3306 Author jiez Date 2009-04-01 04:47:34 -0500 (Wed, 01 Apr 2009)

Log Message

Fix bug [#4974] Make link_warning work with targets which have symbol prefix.

Modified Paths

Diff

Modified: trunk/uClibc/include/libc-symbols.h (3305 => 3306)

--- trunk/uClibc/include/libc-symbols.h 2009-03-31 12:56:21 UTC (rev 3305) +++ trunk/uClibc/include/libc-symbols.h 2009-04-01 09:47:34 UTC (rev 3306) <at> <at> -285,7 +285,9 <at> <at> /* When a reference to SYMBOL is encountered, the linker will emit a warning message MSG. */ -#define link_warning(symbol, msg) \ +#define link_warning(symbol, msg) link_warning2(C_SYMBOL_NAME(symbol), msg) +#define link_warning2(symbol, msg) link_warning3(symbol, msg) +#define link_warning3(symbol, msg) \ __make_section_unallocated (".gnu.warning." #symbol) \ static const char __evoke_link_warning_##symbol[] \ __attribute__ ((used, section (".gnu.warning." #symbol __sec_comment))) \ 
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<div>
Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&amp;path=/&amp;view=rev&amp;root=toolchain&amp;revision=3306">3306</a>
Author <a href="http://blackfin.uclinux.org/gf/user/jiez/">jiez</a>
Date 2009-04-01 04:47:34 -0500 (Wed, 01 Apr 2009)
<h3>Log Message</h3>
Fix bug <a href="http://blackfin.uclinux.org/gf/tracker/4974">[#4974]</a> Make link_warning work with targets which have symbol prefix.

<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkuClibcincludelibcsymbolsh">trunk/uClibc/include/libc-symbols.h</a></li>
</ul>
</div>
<div>
<h3>Diff</h3>
<a></a>
<div class="modfile">
<h4>Modified: trunk/uClibc/include/libc-symbols.h (3305 =&gt; 3306)</h4>
<span>
<span class="info">--- trunk/uClibc/include/libc-symbols.h	2009-03-31 12:56:21 UTC (rev 3305)
+++ trunk/uClibc/include/libc-symbols.h	2009-04-01 09:47:34 UTC (rev 3306)
</span><span class="lines"> <at>  <at>  -285,7 +285,9  <at>  <at> 
</span><span class="cx"> 
</span><span class="cx"> /* When a reference to SYMBOL is encountered, the linker will emit a
</span><span class="cx">    warning message MSG.  */
</span>-#define link_warning(symbol, msg) \
+#define link_warning(symbol, msg) link_warning2(C_SYMBOL_NAME(symbol), msg)
+#define link_warning2(symbol, msg) link_warning3(symbol, msg)
+#define link_warning3(symbol, msg) \
<span class="cx">   __make_section_unallocated (".gnu.warning." #symbol) \
</span><span class="cx">   static const char __evoke_link_warning_##symbol[]	\
</span><span class="cx">     __attribute__ ((used, section (".gnu.warning." #symbol __sec_comment))) \
</span></span>
</div>
</div>

</div>
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jiez | 1 Apr 2009 11:54
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[3307] branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h: Fix bug [#4974] Make link_warning work with targets which have symbol prefix.

Revision 3307 Author jiez Date 2009-04-01 04:54:42 -0500 (Wed, 01 Apr 2009)

Log Message

Fix bug [#4974] Make link_warning work with targets which have symbol prefix.

Modified Paths

Diff

Modified: branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h (3306 => 3307)

--- branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h 2009-04-01 09:47:34 UTC (rev 3306) +++ branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h 2009-04-01 09:54:42 UTC (rev 3307) <at> <at> -285,7 +285,9 <at> <at> /* When a reference to SYMBOL is encountered, the linker will emit a warning message MSG. */ -#define link_warning(symbol, msg) \ +#define link_warning(symbol, msg) link_warning2(C_SYMBOL_NAME(symbol), msg) +#define link_warning2(symbol, msg) link_warning3(symbol, msg) +#define link_warning3(symbol, msg) \ __make_section_unallocated (".gnu.warning." #symbol) \ static const char __evoke_link_warning_##symbol[] \ __attribute__ ((used, section (".gnu.warning." #symbol __sec_comment))) \ 
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<div>
Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&amp;path=/&amp;view=rev&amp;root=toolchain&amp;revision=3307">3307</a>
Author <a href="http://blackfin.uclinux.org/gf/user/jiez/">jiez</a>
Date 2009-04-01 04:54:42 -0500 (Wed, 01 Apr 2009)
<h3>Log Message</h3>
Fix bug <a href="http://blackfin.uclinux.org/gf/tracker/4974">[#4974]</a> Make link_warning work with targets which have symbol prefix.

<h3>Modified Paths</h3>
<ul>
<li><a href="#branchestoolchain_09r1_branchuClibcincludelibcsymbolsh">branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h</a></li>
</ul>
</div>
<div>
<h3>Diff</h3>
<a></a>
<div class="modfile">
<h4>Modified: branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h (3306 =&gt; 3307)</h4>
<span>
<span class="info">--- branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h	2009-04-01 09:47:34 UTC (rev 3306)
+++ branches/toolchain_09r1_branch/uClibc/include/libc-symbols.h	2009-04-01 09:54:42 UTC (rev 3307)
</span><span class="lines"> <at>  <at>  -285,7 +285,9  <at>  <at> 
</span><span class="cx"> 
</span><span class="cx"> /* When a reference to SYMBOL is encountered, the linker will emit a
</span><span class="cx">    warning message MSG.  */
</span>-#define link_warning(symbol, msg) \
+#define link_warning(symbol, msg) link_warning2(C_SYMBOL_NAME(symbol), msg)
+#define link_warning2(symbol, msg) link_warning3(symbol, msg)
+#define link_warning3(symbol, msg) \
<span class="cx">   __make_section_unallocated (".gnu.warning." #symbol) \
</span><span class="cx">   static const char __evoke_link_warning_##symbol[]	\
</span><span class="cx">     __attribute__ ((used, section (".gnu.warning." #symbol __sec_comment))) \
</span></span>
</div>
</div>

</div>
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rgetz | 1 Apr 2009 20:26
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[3308] trunk/proc-defs/header-frags: Update comments, so descriptions are all alike

Diff

Modified: trunk/proc-defs/header-frags/bf518/anomaly.h (3307 => 3308)

--- trunk/proc-defs/header-frags/bf518/anomaly.h 2009-04-01 09:54:42 UTC (rev 3307) +++ trunk/proc-defs/header-frags/bf518/anomaly.h 2009-04-01 18:26:13 UTC (rev 3308) <at> <at> -47,7 +47,7 <at> <at> #define ANOMALY_05000435 (1) /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ #define ANOMALY_05000438 (1) -/* Preboot Cannot be Used to Program the PLL_DIV Register */ +/* Preboot Cannot be Used to Alter the PLL_DIV Register */ #define ANOMALY_05000439 (1) /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ #define ANOMALY_05000440 (1)

Modified: trunk/proc-defs/header-frags/bf527/anomaly.h (3307 => 3308)

--- trunk/proc-defs/header-frags/bf527/anomaly.h 2009-04-01 09:54:42 UTC (rev 3307) +++ trunk/proc-defs/header-frags/bf527/anomaly.h 2009-04-01 18:26:13 UTC (rev 3308) <at> <at> -31,7 +31,7 <at> <at> #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ #define ANOMALY_05000254 (1)

Modified: trunk/proc-defs/header-frags/bf533/anomaly.h (3307 => 3308)

--- trunk/proc-defs/header-frags/bf533/anomaly.h 2009-04-01 09:54:42 UTC (rev 3307) +++ trunk/proc-defs/header-frags/bf533/anomaly.h 2009-04-01 18:26:13 UTC (rev 3308) <at> <at> -48,7 +48,7 <at> <at> #define ANOMALY_05000158 (__SILICON_REVISION__ < 5) /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) -/* Turning Serial Ports on with External Frame Syncs */ +/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (__SILICON_REVISION__ < 5) <at> <at> -104,7 +104,7 <at> <at> #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Data CPLBs Should Prevent Spurious Hardware Errors */ #define ANOMALY_05000246 (__SILICON_REVISION__ < 5) <at> <at> -172,7 +172,7 <at> <at> #define ANOMALY_05000311 (__SILICON_REVISION__ < 6) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 6) -/* PPI Is Level-Sensitive on First Transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 6) /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 6) <at> <at> -237,17 +237,17 <at> <at> #define ANOMALY_05000145 (__SILICON_REVISION__ < 3) /* MDMA may lose the first few words of a descriptor chain */ #define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* The source MDMA descriptor may stop with a DMA Error */ +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ #define ANOMALY_05000147 (__SILICON_REVISION__ < 3) /* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ #define ANOMALY_05000148 (__SILICON_REVISION__ < 3) /* Frame Delay in SPORT Multichannel Mode */ #define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ #define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ #define ANOMALY_05000155 (__SILICON_REVISION__ < 3) -/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ +/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 3) /* SPORT transmit data is not gated by external frame sync in certain conditions */ #define ANOMALY_05000163 (__SILICON_REVISION__ < 3)

Modified: trunk/proc-defs/header-frags/bf537/anomaly.h (3307 => 3308)

--- trunk/proc-defs/header-frags/bf537/anomaly.h 2009-04-01 09:54:42 UTC (rev 3307) +++ trunk/proc-defs/header-frags/bf537/anomaly.h 2009-04-01 18:26:13 UTC (rev 3308) <at> <at> -36,77 +36,77 <at> <at> /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ #define ANOMALY_05000074 (1) -/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */ +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) -/* Rx.H cannot be used to access 16-bit System MMR registers */ +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ #define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) -/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ +/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) /* Instruction Cache Is Not Functional */ #define ANOMALY_05000237 (__SILICON_REVISION__ < 2) -/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) -/* Spurious Hardware Error from an access in the shadow of a conditional branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* CLKIN Buffer Output Enable Reset Behavior Is Changed */ #define ANOMALY_05000247 (1) -/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */ +/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) /* EMAC Tx DMA error after an early frame abort */ #define ANOMALY_05000252 (__SILICON_REVISION__ < 3) -/* Maximum external clock speed for Timers */ +/* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (__SILICON_REVISION__ < 3) -/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */ +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ #define ANOMALY_05000254 (__SILICON_REVISION__ > 2) -/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */ +/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ #define ANOMALY_05000255 (__SILICON_REVISION__ < 3) /* EMAC MDIO input latched on wrong MDC edge */ #define ANOMALY_05000256 (__SILICON_REVISION__ < 3) -/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */ +/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ #define ANOMALY_05000257 (__SILICON_REVISION__ < 3) -/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */ +/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2) -/* ICPLB_STATUS MMR register may be corrupted */ +/* ICPLB_STATUS MMR Register May Be Corrupted */ #define ANOMALY_05000260 (__SILICON_REVISION__ == 2) -/* DCPLB_FAULT_ADDR MMR register may be corrupted */ +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) -/* Stores to data cache may be lost */ +/* Stores To Data Cache May Be Lost */ #define ANOMALY_05000262 (__SILICON_REVISION__ < 3) -/* Hardware loop corrupted when taking an ICPLB exception */ +/* Hardware Loop Corrupted When Taking an ICPLB Exception */ #define ANOMALY_05000263 (__SILICON_REVISION__ == 2) -/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */ +/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ #define ANOMALY_05000264 (__SILICON_REVISION__ < 3) -/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */ +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ #define ANOMALY_05000268 (__SILICON_REVISION__ < 3) -/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */ +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 3) -/* Certain data cache write through modes fail for VDDint <=0.9V */ +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* Writes to Synchronous SDRAM memory may be lost */ +/* Writes to Synchronous SDRAM Memory May Be Lost */ #define ANOMALY_05000273 (__SILICON_REVISION__ < 3) -/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) -/* Disabling Peripherals with DMA running may cause DMA system instability */ +/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) /* SPI Master boot mode does not work well with Atmel Data flash devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception when ISR context is not restored */ +/* False Hardware Error Exception When ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) -/* Memory DMA corruption with 32-bit data and traffic control */ +/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 3) /* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ #define ANOMALY_05000285 (__SILICON_REVISION__ < 3) -/* SPORTs may receive bad data if FIFOs fill up */ +/* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 3) -/* Memory to memory DMA source/destination descriptors must be in same memory space */ +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ #define ANOMALY_05000301 (1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 3) <at> <at> -116,11 +116,11 <at> <at> #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) /* Writing UART_THR while UART clock is disabled sends erroneous start bit */ #define ANOMALY_05000309 (__SILICON_REVISION__ < 3) -/* False hardware errors caused by fetches at the boundary of reserved memory */ +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) -/* PPI is level sensitive on first transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 3)

Modified: trunk/proc-defs/header-frags/bf538/anomaly.h (3307 => 3308)

--- trunk/proc-defs/header-frags/bf538/anomaly.h 2009-04-01 09:54:42 UTC (rev 3307) +++ trunk/proc-defs/header-frags/bf538/anomaly.h 2009-04-01 18:26:13 UTC (rev 3308) <at> <at> -24,7 +24,7 <at> <at> #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ +/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ #define ANOMALY_05000179 (1) <at> <at> -40,13 +40,13 <at> <at> #define ANOMALY_05000229 (1) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ #define ANOMALY_05000233 (1) -/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (1) -/* DCPLB_FAULT_ADDR MMR register may be corrupted */ +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) <at> <at> -58,11 +58,11 <at> <at> #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error Exception When ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) -/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ +/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) <at> <at> -80,11 +80,11 <at> <at> #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) -/* PPI Is Level-Sensitive on First Transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) -/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ +/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ #define ANOMALY_05000318 (__SILICON_REVISION__ < 4)

Modified: trunk/proc-defs/header-frags/bf548/anomaly.h (3307 => 3308)

--- trunk/proc-defs/header-frags/bf548/anomaly.h 2009-04-01 09:54:42 UTC (rev 3307) +++ trunk/proc-defs/header-frags/bf548/anomaly.h 2009-04-01 18:26:13 UTC (rev 3308) <at> <at> -19,13 +19,13 <at> <at> #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception when ISR context is not restored */ +/* False Hardware Error Exception When ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) <at> <at> -59,7 +59,7 <at> <at> #define ANOMALY_05000340 (__SILICON_REVISION__ < 1) /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) -/* USB Calibration Value Is Not Intialized */ +/* USB Calibration Value Is Not Initialized */ #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) /* USB Calibration Value to use */ #define ANOMALY_05000346_value 0x5411 <at> <at> -147,11 +147,11 <at> <at> #define ANOMALY_05000416 (1) /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ #define ANOMALY_05000425 (1) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ #define ANOMALY_05000427 (__SILICON_REVISION__ < 2) -/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */ +/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) /* Software System Reset Corrupts PLL_LOCKCNT Register */ #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)

Modified: trunk/proc-defs/header-frags/bf561/anomaly.h (3307 => 3308)

--- trunk/proc-defs/header-frags/bf561/anomaly.h 2009-04-01 09:54:42 UTC (rev 3307) +++ trunk/proc-defs/header-frags/bf561/anomaly.h 2009-04-01 18:26:13 UTC (rev 3308) <at> <at> -22,7 +22,7 <at> <at> #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */ +/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ #define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* Testset instructions restricted to 32-bit aligned memory locations */ #define ANOMALY_05000120 (1) <at> <at> -40,7 +40,7 <at> <at> #define ANOMALY_05000136 (__SILICON_REVISION__ < 3) /* Allowing the SPORT RX FIFO to fill will cause an overflow */ #define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ +/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ #define ANOMALY_05000141 (__SILICON_REVISION__ < 3) /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ #define ANOMALY_05000142 (__SILICON_REVISION__ < 3) <at> <at> -80,7 +80,7 <at> <at> #define ANOMALY_05000163 (__SILICON_REVISION__ < 3) /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) -/* Turning Serial Ports on with External Frame Syncs */ +/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ #define ANOMALY_05000167 (1) /* SDRAM auto-refresh and subsequent Power Ups */ #define ANOMALY_05000168 (__SILICON_REVISION__ < 5) <at> <at> -164,7 +164,7 <at> <at> #define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (__SILICON_REVISION__ < 5) /* TESTSET operation forces stall on the other core */ #define ANOMALY_05000248 (__SILICON_REVISION__ < 5) <at> <at> -208,7 +208,7 <at> <at> #define ANOMALY_05000275 (__SILICON_REVISION__ > 2) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) -/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */ +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 3) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) <at> <at> -232,7 +232,7 <at> <at> #define ANOMALY_05000310 (1) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ #define ANOMALY_05000312 (1) -/* PPI Is Level-Sensitive on First Transfer */ +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ #define ANOMALY_05000313 (1) /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ #define ANOMALY_05000315 (1) 
<div>

<div>
Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&amp;path=/&amp;view=rev&amp;root=toolchain&amp;revision=3308">3308</a>
Author <a href="http://blackfin.uclinux.org/gf/user/rgetz/">rgetz</a>
Date 2009-04-01 13:26:13 -0500 (Wed, 01 Apr 2009)
<h3>Log Message</h3>
Update comments, so descriptions are all alike

<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkprocdefsheaderfragsbf518anomalyh">trunk/proc-defs/header-frags/bf518/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf527anomalyh">trunk/proc-defs/header-frags/bf527/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf533anomalyh">trunk/proc-defs/header-frags/bf533/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf537anomalyh">trunk/proc-defs/header-frags/bf537/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf538anomalyh">trunk/proc-defs/header-frags/bf538/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf548anomalyh">trunk/proc-defs/header-frags/bf548/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf561anomalyh">trunk/proc-defs/header-frags/bf561/anomaly.h</a></li>
</ul>
</div>
<div>
<h3>Diff</h3>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf518/anomaly.h (3307 =&gt; 3308)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf518/anomaly.h	2009-04-01 09:54:42 UTC (rev 3307)
+++ trunk/proc-defs/header-frags/bf518/anomaly.h	2009-04-01 18:26:13 UTC (rev 3308)
</span><span class="lines"> <at>  <at>  -47,7 +47,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000435 (1)
</span><span class="cx"> /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
</span><span class="cx"> #define ANOMALY_05000438 (1)
</span>-/* Preboot Cannot be Used to Program the PLL_DIV Register */
+/* Preboot Cannot be Used to Alter the PLL_DIV Register */
<span class="cx"> #define ANOMALY_05000439 (1)
</span><span class="cx"> /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
</span><span class="cx"> #define ANOMALY_05000440 (1)
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf527/anomaly.h (3307 =&gt; 3308)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf527/anomaly.h	2009-04-01 09:54:42 UTC (rev 3307)
+++ trunk/proc-defs/header-frags/bf527/anomaly.h	2009-04-01 18:26:13 UTC (rev 3308)
</span><span class="lines"> <at>  <at>  -31,7 +31,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000119 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
</span><span class="cx"> /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
</span><span class="cx"> #define ANOMALY_05000122 (1)
</span>-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
<span class="cx"> #define ANOMALY_05000245 (1)
</span><span class="cx"> /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
</span><span class="cx"> #define ANOMALY_05000254 (1)
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf533/anomaly.h (3307 =&gt; 3308)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf533/anomaly.h	2009-04-01 09:54:42 UTC (rev 3307)
+++ trunk/proc-defs/header-frags/bf533/anomaly.h	2009-04-01 18:26:13 UTC (rev 3308)
</span><span class="lines"> <at>  <at>  -48,7 +48,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000158 (__SILICON_REVISION__ &lt; 5)
</span><span class="cx"> /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
</span><span class="cx"> #define ANOMALY_05000166 (1)
</span>-/* Turning Serial Ports on with External Frame Syncs */
+/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
<span class="cx"> #define ANOMALY_05000167 (1)
</span><span class="cx"> /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
</span><span class="cx"> #define ANOMALY_05000179 (__SILICON_REVISION__ &lt; 5)
</span><span class="lines"> <at>  <at>  -104,7 +104,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000242 (__SILICON_REVISION__ &lt; 5)
</span><span class="cx"> /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
</span><span class="cx"> #define ANOMALY_05000244 (__SILICON_REVISION__ &lt; 5)
</span>-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
<span class="cx"> #define ANOMALY_05000245 (1)
</span><span class="cx"> /* Data CPLBs Should Prevent Spurious Hardware Errors */
</span><span class="cx"> #define ANOMALY_05000246 (__SILICON_REVISION__ &lt; 5)
</span><span class="lines"> <at>  <at>  -172,7 +172,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000311 (__SILICON_REVISION__ &lt; 6)
</span><span class="cx"> /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
</span><span class="cx"> #define ANOMALY_05000312 (__SILICON_REVISION__ &lt; 6)
</span>-/* PPI Is Level-Sensitive on First Transfer */
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
<span class="cx"> #define ANOMALY_05000313 (__SILICON_REVISION__ &lt; 6)
</span><span class="cx"> /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
</span><span class="cx"> #define ANOMALY_05000315 (__SILICON_REVISION__ &lt; 6)
</span><span class="lines"> <at>  <at>  -237,17 +237,17  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000145 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* MDMA may lose the first few words of a descriptor chain */
</span><span class="cx"> #define ANOMALY_05000146 (__SILICON_REVISION__ &lt; 3)
</span>-/* The source MDMA descriptor may stop with a DMA Error */
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
<span class="cx"> #define ANOMALY_05000147 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
</span><span class="cx"> #define ANOMALY_05000148 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* Frame Delay in SPORT Multichannel Mode */
</span><span class="cx"> #define ANOMALY_05000153 (__SILICON_REVISION__ &lt; 3)
</span>-/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
<span class="cx"> #define ANOMALY_05000154 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
</span><span class="cx"> #define ANOMALY_05000155 (__SILICON_REVISION__ &lt; 3)
</span>-/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
+/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
<span class="cx"> #define ANOMALY_05000157 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* SPORT transmit data is not gated by external frame sync in certain conditions */
</span><span class="cx"> #define ANOMALY_05000163 (__SILICON_REVISION__ &lt; 3)
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf537/anomaly.h (3307 =&gt; 3308)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf537/anomaly.h	2009-04-01 09:54:42 UTC (rev 3307)
+++ trunk/proc-defs/header-frags/bf537/anomaly.h	2009-04-01 18:26:13 UTC (rev 3308)
</span><span class="lines"> <at>  <at>  -36,77 +36,77  <at>  <at> 
</span><span class="cx"> 
</span><span class="cx"> /* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
</span><span class="cx"> #define ANOMALY_05000074 (1)
</span>-/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
<span class="cx"> #define ANOMALY_05000119 (1)
</span>-/* Rx.H cannot be used to access 16-bit System MMR registers */
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
<span class="cx"> #define ANOMALY_05000122 (1)
</span><span class="cx"> /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
</span><span class="cx"> #define ANOMALY_05000157 (__SILICON_REVISION__ &lt; 2)
</span><span class="cx"> /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
</span><span class="cx"> #define ANOMALY_05000167 (1)
</span>-/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
<span class="cx"> #define ANOMALY_05000180 (1)
</span><span class="cx"> /* Instruction Cache Is Not Functional */
</span><span class="cx"> #define ANOMALY_05000237 (__SILICON_REVISION__ &lt; 2)
</span>-/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
<span class="cx"> #define ANOMALY_05000244 (__SILICON_REVISION__ &lt; 3)
</span>-/* Spurious Hardware Error from an access in the shadow of a conditional branch */
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
<span class="cx"> #define ANOMALY_05000245 (1)
</span><span class="cx"> /* CLKIN Buffer Output Enable Reset Behavior Is Changed */
</span><span class="cx"> #define ANOMALY_05000247 (1)
</span>-/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
+/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
<span class="cx"> #define ANOMALY_05000250 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* EMAC Tx DMA error after an early frame abort */
</span><span class="cx"> #define ANOMALY_05000252 (__SILICON_REVISION__ &lt; 3)
</span>-/* Maximum external clock speed for Timers */
+/* Maximum External Clock Speed for Timers */
<span class="cx"> #define ANOMALY_05000253 (__SILICON_REVISION__ &lt; 3)
</span>-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
<span class="cx"> #define ANOMALY_05000254 (__SILICON_REVISION__ &gt; 2)
</span>-/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
+/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
<span class="cx"> #define ANOMALY_05000255 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* EMAC MDIO input latched on wrong MDC edge */
</span><span class="cx"> #define ANOMALY_05000256 (__SILICON_REVISION__ &lt; 3)
</span>-/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
+/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
<span class="cx"> #define ANOMALY_05000257 (__SILICON_REVISION__ &lt; 3)
</span>-/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
+/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
<span class="cx"> #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) &amp;&amp; __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
</span>-/* ICPLB_STATUS MMR register may be corrupted */
+/* ICPLB_STATUS MMR Register May Be Corrupted */
<span class="cx"> #define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
</span>-/* DCPLB_FAULT_ADDR MMR register may be corrupted */
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
<span class="cx"> #define ANOMALY_05000261 (__SILICON_REVISION__ &lt; 3)
</span>-/* Stores to data cache may be lost */
+/* Stores To Data Cache May Be Lost */
<span class="cx"> #define ANOMALY_05000262 (__SILICON_REVISION__ &lt; 3)
</span>-/* Hardware loop corrupted when taking an ICPLB exception */
+/* Hardware Loop Corrupted When Taking an ICPLB Exception */
<span class="cx"> #define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
</span>-/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
+/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
<span class="cx"> #define ANOMALY_05000264 (__SILICON_REVISION__ &lt; 3)
</span>-/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
<span class="cx"> #define ANOMALY_05000265 (1)
</span><span class="cx"> /* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
</span><span class="cx"> #define ANOMALY_05000268 (__SILICON_REVISION__ &lt; 3)
</span>-/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
<span class="cx"> #define ANOMALY_05000270 (__SILICON_REVISION__ &lt; 3)
</span>-/* Certain data cache write through modes fail for VDDint &lt;=0.9V */
+/* Certain Data Cache Writethrough Modes Fail for Vddint &lt;= 0.9V */
<span class="cx"> #define ANOMALY_05000272 (1)
</span>-/* Writes to Synchronous SDRAM memory may be lost */
+/* Writes to Synchronous SDRAM Memory May Be Lost */
<span class="cx"> #define ANOMALY_05000273 (__SILICON_REVISION__ &lt; 3)
</span>-/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
<span class="cx"> #define ANOMALY_05000277 (__SILICON_REVISION__ &lt; 3)
</span>-/* Disabling Peripherals with DMA running may cause DMA system instability */
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
<span class="cx"> #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) &amp;&amp; __SILICON_REVISION__ &lt; 3) || (ANOMALY_BF534 &amp;&amp; __SILICON_REVISION__ &lt; 2))
</span><span class="cx"> /* SPI Master boot mode does not work well with Atmel Data flash devices */
</span><span class="cx"> #define ANOMALY_05000280 (1)
</span>-/* False Hardware Error Exception when ISR context is not restored */
+/* False Hardware Error Exception When ISR Context Is Not Restored */
<span class="cx"> #define ANOMALY_05000281 (__SILICON_REVISION__ &lt; 3)
</span>-/* Memory DMA corruption with 32-bit data and traffic control */
+/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
<span class="cx"> #define ANOMALY_05000282 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
</span><span class="cx"> #define ANOMALY_05000283 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
</span><span class="cx"> #define ANOMALY_05000285 (__SILICON_REVISION__ &lt; 3)
</span>-/* SPORTs may receive bad data if FIFOs fill up */
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
<span class="cx"> #define ANOMALY_05000288 (__SILICON_REVISION__ &lt; 3)
</span>-/* Memory to memory DMA source/destination descriptors must be in same memory space */
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
<span class="cx"> #define ANOMALY_05000301 (1)
</span><span class="cx"> /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
</span><span class="cx"> #define ANOMALY_05000304 (__SILICON_REVISION__ &lt; 3)
</span><span class="lines"> <at>  <at>  -116,11 +116,11  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000307 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* Writing UART_THR while UART clock is disabled sends erroneous start bit */
</span><span class="cx"> #define ANOMALY_05000309 (__SILICON_REVISION__ &lt; 3)
</span>-/* False hardware errors caused by fetches at the boundary of reserved memory */
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
<span class="cx"> #define ANOMALY_05000310 (1)
</span>-/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
<span class="cx"> #define ANOMALY_05000312 (1)
</span>-/* PPI is level sensitive on first transfer */
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
<span class="cx"> #define ANOMALY_05000313 (1)
</span><span class="cx"> /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
</span><span class="cx"> #define ANOMALY_05000315 (__SILICON_REVISION__ &lt; 3)
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf538/anomaly.h (3307 =&gt; 3308)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf538/anomaly.h	2009-04-01 09:54:42 UTC (rev 3307)
+++ trunk/proc-defs/header-frags/bf538/anomaly.h	2009-04-01 18:26:13 UTC (rev 3308)
</span><span class="lines"> <at>  <at>  -24,7 +24,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000119 (1)
</span><span class="cx"> /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
</span><span class="cx"> #define ANOMALY_05000122 (1)
</span>-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
+/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
<span class="cx"> #define ANOMALY_05000166 (1)
</span><span class="cx"> /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
</span><span class="cx"> #define ANOMALY_05000179 (1)
</span><span class="lines"> <at>  <at>  -40,13 +40,13  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000229 (1)
</span><span class="cx"> /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
</span><span class="cx"> #define ANOMALY_05000233 (1)
</span>-/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
<span class="cx"> #define ANOMALY_05000244 (__SILICON_REVISION__ &lt; 3)
</span>-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
<span class="cx"> #define ANOMALY_05000245 (1)
</span><span class="cx"> /* Maximum External Clock Speed for Timers */
</span><span class="cx"> #define ANOMALY_05000253 (1)
</span>-/* DCPLB_FAULT_ADDR MMR register may be corrupted */
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
<span class="cx"> #define ANOMALY_05000261 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
</span><span class="cx"> #define ANOMALY_05000270 (__SILICON_REVISION__ &lt; 4)
</span><span class="lines"> <at>  <at>  -58,11 +58,11  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000277 (__SILICON_REVISION__ &lt; 4)
</span><span class="cx"> /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
</span><span class="cx"> #define ANOMALY_05000278 (__SILICON_REVISION__ &lt; 4)
</span>-/* False Hardware Error Exception when ISR Context Is Not Restored */
+/* False Hardware Error Exception When ISR Context Is Not Restored */
<span class="cx"> #define ANOMALY_05000281 (__SILICON_REVISION__ &lt; 4)
</span><span class="cx"> /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
</span><span class="cx"> #define ANOMALY_05000282 (__SILICON_REVISION__ &lt; 4)
</span>-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
<span class="cx"> #define ANOMALY_05000283 (__SILICON_REVISION__ &lt; 4)
</span><span class="cx"> /* SPORTs May Receive Bad Data If FIFOs Fill Up */
</span><span class="cx"> #define ANOMALY_05000288 (__SILICON_REVISION__ &lt; 4)
</span><span class="lines"> <at>  <at>  -80,11 +80,11  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000307 (__SILICON_REVISION__ &lt; 4)
</span><span class="cx"> /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
</span><span class="cx"> #define ANOMALY_05000310 (1)
</span>-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
<span class="cx"> #define ANOMALY_05000312 (__SILICON_REVISION__ &lt; 5)
</span>-/* PPI Is Level-Sensitive on First Transfer */
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
<span class="cx"> #define ANOMALY_05000313 (__SILICON_REVISION__ &lt; 4)
</span>-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
<span class="cx"> #define ANOMALY_05000315 (__SILICON_REVISION__ &lt; 4)
</span><span class="cx"> /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
</span><span class="cx"> #define ANOMALY_05000318 (__SILICON_REVISION__ &lt; 4)
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf548/anomaly.h (3307 =&gt; 3308)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf548/anomaly.h	2009-04-01 09:54:42 UTC (rev 3307)
+++ trunk/proc-defs/header-frags/bf548/anomaly.h	2009-04-01 18:26:13 UTC (rev 3308)
</span><span class="lines"> <at>  <at>  -19,13 +19,13  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000119 (1)
</span><span class="cx"> /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
</span><span class="cx"> #define ANOMALY_05000122 (1)
</span>-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
<span class="cx"> #define ANOMALY_05000245 (1)
</span><span class="cx"> /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
</span><span class="cx"> #define ANOMALY_05000265 (1)
</span><span class="cx"> /* Certain Data Cache Writethrough Modes Fail for Vddint &lt;= 0.9V */
</span><span class="cx"> #define ANOMALY_05000272 (1)
</span>-/* False Hardware Error Exception when ISR context is not restored */
+/* False Hardware Error Exception When ISR Context Is Not Restored */
<span class="cx"> #define ANOMALY_05000281 (__SILICON_REVISION__ &lt; 1)
</span><span class="cx"> /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
</span><span class="cx"> #define ANOMALY_05000304 (__SILICON_REVISION__ &lt; 1)
</span><span class="lines"> <at>  <at>  -59,7 +59,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000340 (__SILICON_REVISION__ &lt; 1)
</span><span class="cx"> /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
</span><span class="cx"> #define ANOMALY_05000344 (__SILICON_REVISION__ &lt; 1)
</span>-/* USB Calibration Value Is Not Intialized */
+/* USB Calibration Value Is Not Initialized */
<span class="cx"> #define ANOMALY_05000346 (__SILICON_REVISION__ &lt; 1)
</span><span class="cx"> /* USB Calibration Value to use */
</span><span class="cx"> #define ANOMALY_05000346_value 0x5411
</span><span class="lines"> <at>  <at>  -147,11 +147,11  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000416 (1)
</span><span class="cx"> /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
</span><span class="cx"> #define ANOMALY_05000425 (1)
</span>-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
<span class="cx"> #define ANOMALY_05000426 (1)
</span><span class="cx"> /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
</span><span class="cx"> #define ANOMALY_05000427 (__SILICON_REVISION__ &lt; 2)
</span>-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
<span class="cx"> #define ANOMALY_05000429 (__SILICON_REVISION__ &lt; 2)
</span><span class="cx"> /* Software System Reset Corrupts PLL_LOCKCNT Register */
</span><span class="cx"> #define ANOMALY_05000430 (__SILICON_REVISION__ &gt;= 2)
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf561/anomaly.h (3307 =&gt; 3308)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf561/anomaly.h	2009-04-01 09:54:42 UTC (rev 3307)
+++ trunk/proc-defs/header-frags/bf561/anomaly.h	2009-04-01 18:26:13 UTC (rev 3308)
</span><span class="lines"> <at>  <at>  -22,7 +22,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000074 (1)
</span><span class="cx"> /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
</span><span class="cx"> #define ANOMALY_05000099 (__SILICON_REVISION__ &lt; 5)
</span>-/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
+/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
<span class="cx"> #define ANOMALY_05000116 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* Testset instructions restricted to 32-bit aligned memory locations */
</span><span class="cx"> #define ANOMALY_05000120 (1)
</span><span class="lines"> <at>  <at>  -40,7 +40,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000136 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* Allowing the SPORT RX FIFO to fill will cause an overflow */
</span><span class="cx"> #define ANOMALY_05000140 (__SILICON_REVISION__ &lt; 3)
</span>-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
+/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
<span class="cx"> #define ANOMALY_05000141 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
</span><span class="cx"> #define ANOMALY_05000142 (__SILICON_REVISION__ &lt; 3)
</span><span class="lines"> <at>  <at>  -80,7 +80,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000163 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
</span><span class="cx"> #define ANOMALY_05000166 (1)
</span>-/* Turning Serial Ports on with External Frame Syncs */
+/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
<span class="cx"> #define ANOMALY_05000167 (1)
</span><span class="cx"> /* SDRAM auto-refresh and subsequent Power Ups */
</span><span class="cx"> #define ANOMALY_05000168 (__SILICON_REVISION__ &lt; 5)
</span><span class="lines"> <at>  <at>  -164,7 +164,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000242 (__SILICON_REVISION__ &lt; 5)
</span><span class="cx"> /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
</span><span class="cx"> #define ANOMALY_05000244 (__SILICON_REVISION__ &lt; 5)
</span>-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
<span class="cx"> #define ANOMALY_05000245 (__SILICON_REVISION__ &lt; 5)
</span><span class="cx"> /* TESTSET operation forces stall on the other core */
</span><span class="cx"> #define ANOMALY_05000248 (__SILICON_REVISION__ &lt; 5)
</span><span class="lines"> <at>  <at>  -208,7 +208,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000275 (__SILICON_REVISION__ &gt; 2)
</span><span class="cx"> /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
</span><span class="cx"> #define ANOMALY_05000276 (__SILICON_REVISION__ &lt; 5)
</span>-/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
<span class="cx"> #define ANOMALY_05000277 (__SILICON_REVISION__ &lt; 3)
</span><span class="cx"> /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
</span><span class="cx"> #define ANOMALY_05000278 (__SILICON_REVISION__ &lt; 5)
</span><span class="lines"> <at>  <at>  -232,7 +232,7  <at>  <at> 
</span><span class="cx"> #define ANOMALY_05000310 (1)
</span><span class="cx"> /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
</span><span class="cx"> #define ANOMALY_05000312 (1)
</span>-/* PPI Is Level-Sensitive on First Transfer */
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
<span class="cx"> #define ANOMALY_05000313 (1)
</span><span class="cx"> /* Killed System MMR Write Completes Erroneously On Next System MMR Access */
</span><span class="cx"> #define ANOMALY_05000315 (1)
</span></span>
</div>
</div>

</div>
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headers
bernds | 2 Apr 2009 00:26
Favicon

[3309] tags/toolchain_09r1_rc5/: Tag 09r1 rc5.

Revision 3309 Author bernds Date 2009-04-01 17:25:57 -0500 (Wed, 01 Apr 2009)

Log Message

Tag 09r1 rc5.

Added Paths

  • tags/toolchain_09r1_rc5/

Diff

Copied: tags/toolchain_09r1_rc5 (from rev 3308, branches/toolchain_09r1_branch)

<div>

<div>
Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&amp;path=/&amp;view=rev&amp;root=toolchain&amp;revision=3309">3309</a>
Author <a href="http://blackfin.uclinux.org/gf/user/bernds/">bernds</a>
Date 2009-04-01 17:25:57 -0500 (Wed, 01 Apr 2009)
<h3>Log Message</h3>
Tag 09r1 rc5.

<h3>Added Paths</h3>
<ul>
<li>tags/toolchain_09r1_rc5/</li>
</ul>
</div>
<div>
<h3>Diff</h3>
<a></a>
<div class="copfile"><h4>Copied: tags/toolchain_09r1_rc5 (from rev 3308, branches/toolchain_09r1_branch)</h4></div>
</div>

</div>
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headers
vapier | 2 Apr 2009 04:28
Favicon

[3310] trunk/proc-defs/header-frags: fix typo in anomaly header

Diff

Modified: trunk/proc-defs/header-frags/bf518/anomaly.h (3309 => 3310)

--- trunk/proc-defs/header-frags/bf518/anomaly.h 2009-04-01 22:25:57 UTC (rev 3309) +++ trunk/proc-defs/header-frags/bf518/anomaly.h 2009-04-02 02:28:13 UTC (rev 3310) <at> <at> -6,7 +6,7 <at> <at> * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List */

Modified: trunk/proc-defs/header-frags/bf527/anomaly.h (3309 => 3310)

--- trunk/proc-defs/header-frags/bf527/anomaly.h 2009-04-01 22:25:57 UTC (rev 3309) +++ trunk/proc-defs/header-frags/bf527/anomaly.h 2009-04-02 02:28:13 UTC (rev 3310) <at> <at> -6,7 +6,7 <at> <at> * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List */

Modified: trunk/proc-defs/header-frags/bf533/anomaly.h (3309 => 3310)

--- trunk/proc-defs/header-frags/bf533/anomaly.h 2009-04-01 22:25:57 UTC (rev 3309) +++ trunk/proc-defs/header-frags/bf533/anomaly.h 2009-04-02 02:28:13 UTC (rev 3310) <at> <at> -6,7 +6,7 <at> <at> * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */

Modified: trunk/proc-defs/header-frags/bf537/anomaly.h (3309 => 3310)

--- trunk/proc-defs/header-frags/bf537/anomaly.h 2009-04-01 22:25:57 UTC (rev 3309) +++ trunk/proc-defs/header-frags/bf537/anomaly.h 2009-04-02 02:28:13 UTC (rev 3310) <at> <at> -6,7 +6,7 <at> <at> * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */

Modified: trunk/proc-defs/header-frags/bf538/anomaly.h (3309 => 3310)

--- trunk/proc-defs/header-frags/bf538/anomaly.h 2009-04-01 22:25:57 UTC (rev 3309) +++ trunk/proc-defs/header-frags/bf538/anomaly.h 2009-04-02 02:28:13 UTC (rev 3310) <at> <at> -6,7 +6,7 <at> <at> * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List * - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List */

Modified: trunk/proc-defs/header-frags/bf548/anomaly.h (3309 => 3310)

--- trunk/proc-defs/header-frags/bf548/anomaly.h 2009-04-01 22:25:57 UTC (rev 3309) +++ trunk/proc-defs/header-frags/bf548/anomaly.h 2009-04-02 02:28:13 UTC (rev 3310) <at> <at> -6,7 +6,7 <at> <at> * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */

Modified: trunk/proc-defs/header-frags/bf561/anomaly.h (3309 => 3310)

--- trunk/proc-defs/header-frags/bf561/anomaly.h 2009-04-01 22:25:57 UTC (rev 3309) +++ trunk/proc-defs/header-frags/bf561/anomaly.h 2009-04-02 02:28:13 UTC (rev 3310) <at> <at> -6,7 +6,7 <at> <at> * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List */ 
<div>

<div>
Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&amp;path=/&amp;view=rev&amp;root=toolchain&amp;revision=3310">3310</a>
Author <a href="http://blackfin.uclinux.org/gf/user/vapier/">vapier</a>
Date 2009-04-01 21:28:13 -0500 (Wed, 01 Apr 2009)
<h3>Log Message</h3>
fix typo in anomaly header

<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkprocdefsheaderfragsbf518anomalyh">trunk/proc-defs/header-frags/bf518/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf527anomalyh">trunk/proc-defs/header-frags/bf527/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf533anomalyh">trunk/proc-defs/header-frags/bf533/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf537anomalyh">trunk/proc-defs/header-frags/bf537/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf538anomalyh">trunk/proc-defs/header-frags/bf538/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf548anomalyh">trunk/proc-defs/header-frags/bf548/anomaly.h</a></li>
<li><a href="#trunkprocdefsheaderfragsbf561anomalyh">trunk/proc-defs/header-frags/bf561/anomaly.h</a></li>
</ul>
</div>
<div>
<h3>Diff</h3>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf518/anomaly.h (3309 =&gt; 3310)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf518/anomaly.h	2009-04-01 22:25:57 UTC (rev 3309)
+++ trunk/proc-defs/header-frags/bf518/anomaly.h	2009-04-02 02:28:13 UTC (rev 3310)
</span><span class="lines"> <at>  <at>  -6,7 +6,7  <at>  <at> 
</span><span class="cx">  * Licensed under the GPL-2 or later.
</span><span class="cx">  */
</span><span class="cx"> 
</span>-/* This file shoule be up to date with:
+/* This file should be up to date with:
<span class="cx">  *  - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
</span><span class="cx">  */
</span><span class="cx"> 
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf527/anomaly.h (3309 =&gt; 3310)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf527/anomaly.h	2009-04-01 22:25:57 UTC (rev 3309)
+++ trunk/proc-defs/header-frags/bf527/anomaly.h	2009-04-02 02:28:13 UTC (rev 3310)
</span><span class="lines"> <at>  <at>  -6,7 +6,7  <at>  <at> 
</span><span class="cx">  * Licensed under the GPL-2 or later.
</span><span class="cx">  */
</span><span class="cx"> 
</span>-/* This file shoule be up to date with:
+/* This file should be up to date with:
<span class="cx">  *  - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
</span><span class="cx">  *  - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
</span><span class="cx">  */
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf533/anomaly.h (3309 =&gt; 3310)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf533/anomaly.h	2009-04-01 22:25:57 UTC (rev 3309)
+++ trunk/proc-defs/header-frags/bf533/anomaly.h	2009-04-02 02:28:13 UTC (rev 3310)
</span><span class="lines"> <at>  <at>  -6,7 +6,7  <at>  <at> 
</span><span class="cx">  * Licensed under the GPL-2 or later.
</span><span class="cx">  */
</span><span class="cx"> 
</span>-/* This file shoule be up to date with:
+/* This file should be up to date with:
<span class="cx">  *  - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
</span><span class="cx">  */
</span><span class="cx"> 
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf537/anomaly.h (3309 =&gt; 3310)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf537/anomaly.h	2009-04-01 22:25:57 UTC (rev 3309)
+++ trunk/proc-defs/header-frags/bf537/anomaly.h	2009-04-02 02:28:13 UTC (rev 3310)
</span><span class="lines"> <at>  <at>  -6,7 +6,7  <at>  <at> 
</span><span class="cx">  * Licensed under the GPL-2 or later.
</span><span class="cx">  */
</span><span class="cx"> 
</span>-/* This file shoule be up to date with:
+/* This file should be up to date with:
<span class="cx">  *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
</span><span class="cx">  */
</span><span class="cx"> 
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf538/anomaly.h (3309 =&gt; 3310)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf538/anomaly.h	2009-04-01 22:25:57 UTC (rev 3309)
+++ trunk/proc-defs/header-frags/bf538/anomaly.h	2009-04-02 02:28:13 UTC (rev 3310)
</span><span class="lines"> <at>  <at>  -6,7 +6,7  <at>  <at> 
</span><span class="cx">  * Licensed under the GPL-2 or later.
</span><span class="cx">  */
</span><span class="cx"> 
</span>-/* This file shoule be up to date with:
+/* This file should be up to date with:
<span class="cx">  *  - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
</span><span class="cx">  *  - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
</span><span class="cx">  */
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf548/anomaly.h (3309 =&gt; 3310)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf548/anomaly.h	2009-04-01 22:25:57 UTC (rev 3309)
+++ trunk/proc-defs/header-frags/bf548/anomaly.h	2009-04-02 02:28:13 UTC (rev 3310)
</span><span class="lines"> <at>  <at>  -6,7 +6,7  <at>  <at> 
</span><span class="cx">  * Licensed under the GPL-2 or later.
</span><span class="cx">  */
</span><span class="cx"> 
</span>-/* This file shoule be up to date with:
+/* This file should be up to date with:
<span class="cx">  *  - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
</span><span class="cx">  */
</span><span class="cx"> 
</span></span>
</div>
<a></a>
<div class="modfile">
<h4>Modified: trunk/proc-defs/header-frags/bf561/anomaly.h (3309 =&gt; 3310)</h4>
<span>
<span class="info">--- trunk/proc-defs/header-frags/bf561/anomaly.h	2009-04-01 22:25:57 UTC (rev 3309)
+++ trunk/proc-defs/header-frags/bf561/anomaly.h	2009-04-02 02:28:13 UTC (rev 3310)
</span><span class="lines"> <at>  <at>  -6,7 +6,7  <at>  <at> 
</span><span class="cx">  * Licensed under the GPL-2 or later.
</span><span class="cx">  */
</span><span class="cx"> 
</span>-/* This file shoule be up to date with:
+/* This file should be up to date with:
<span class="cx">  *  - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
</span><span class="cx">  */
</span><span class="cx"> 
</span></span>
</div>
</div>

</div>
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Bernd Schmidt | 2 Apr 2009 13:41
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Favicon

Re: [3274] branches/toolchain_09r1_branch: Fix bug [#5000].

jiez@... wrote:
> Revision
>     3274
>     <http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&path=/&view=rev&root=toolchain&revision=3274>
> Author
>     jiez <http://blackfin.uclinux.org/gf/user/jiez/>
> Date
>     2009-03-22 23:11:17 -0500 (Sun, 22 Mar 2009)
> 
> 
>       Log Message
> 
> Fix bug [#5000] <http://blackfin.uclinux.org/gf/tracker/5000>. Move C++ header files to a place
where the libstdc++ test
> "abi/header_cxxabi.c" expects.

It turns out that this makes RPM packaging a bit harder.  Do we really 
need this, or can we fix the testcase?

Bernd
--

-- 
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headers
Jie Zhang | 2 Apr 2009 15:21
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Re: [3274] branches/toolchain_09r1_branch: Fix bug [#5000].

Bernd Schmidt wrote:
> jiez@... wrote:
>> Revision
>>     3274
>>     
>>
<http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&path=/&view=rev&root=toolchain&revision=3274> 
>>
>> Author
>>     jiez <http://blackfin.uclinux.org/gf/user/jiez/>
>> Date
>>     2009-03-22 23:11:17 -0500 (Sun, 22 Mar 2009)
>>
>>
>>       Log Message
>>
>> Fix bug [#5000] <http://blackfin.uclinux.org/gf/tracker/5000>. Move 
>> C++ header files to a place where the libstdc++ test
>> "abi/header_cxxabi.c" expects.
> 
> It turns out that this makes RPM packaging a bit harder.  Do we really 
> need this, or can we fix the testcase?
> 
Fixing the testcase seems more difficult. We may need a 
--print-include-dirs option to GCC as said in libstdc++.exp.

Jie
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headers
vapier | 2 Apr 2009 15:52
Favicon

[3311] trunk/buildscript/BuildToolChain: if we could not detect version info, do not say "could not find" because that confuses users and makes us answer the same questions over and over

Revision 3311 Author vapier Date 2009-04-02 08:52:41 -0500 (Thu, 02 Apr 2009)

Log Message

if we could not detect version info, do not say "could not find" because that confuses users and makes us answer the same questions over and over

Modified Paths

Diff

Modified: trunk/buildscript/BuildToolChain (3310 => 3311)

--- trunk/buildscript/BuildToolChain 2009-04-02 02:28:13 UTC (rev 3310) +++ trunk/buildscript/BuildToolChain 2009-04-02 13:52:41 UTC (rev 3311) <at> <at> -366,7 +366,7 <at> <at> continue fi file=$(which $file) - echo "** Could not find version of $file" + echo "** Looking up file $file for more info" while [ -L "$file" ] ; do printf " * " file $file 
<div>

<div>
Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&amp;path=/&amp;view=rev&amp;root=toolchain&amp;revision=3311">3311</a>
Author <a href="http://blackfin.uclinux.org/gf/user/vapier/">vapier</a>
Date 2009-04-02 08:52:41 -0500 (Thu, 02 Apr 2009)
<h3>Log Message</h3>
if we could not detect version info, do not say "could not find" because that confuses users and makes us answer the same questions over and over

<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkbuildscriptBuildToolChain">trunk/buildscript/BuildToolChain</a></li>
</ul>
</div>
<div>
<h3>Diff</h3>
<a></a>
<div class="modfile">
<h4>Modified: trunk/buildscript/BuildToolChain (3310 =&gt; 3311)</h4>
<span>
<span class="info">--- trunk/buildscript/BuildToolChain	2009-04-02 02:28:13 UTC (rev 3310)
+++ trunk/buildscript/BuildToolChain	2009-04-02 13:52:41 UTC (rev 3311)
</span><span class="lines"> <at>  <at>  -366,7 +366,7  <at>  <at> 
</span><span class="cx">                 continue
</span><span class="cx">             fi
</span><span class="cx">             file=$(which $file)
</span>-            echo "** Could not find version of $file"
+            echo "** Looking up file $file for more info"
<span class="cx">             while [ -L "$file" ] ; do
</span><span class="cx">                 printf " * "
</span><span class="cx">                 file $file
</span></span>
</div>
</div>

</div>
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headers
vapier | 2 Apr 2009 16:01
Favicon

[3312] trunk/buildscript/BuildToolChain: if a util exited with 0 due to our version check, but the greps werent able to detect "version info", then include that text in the output anyways

Revision 3312 Author vapier Date 2009-04-02 09:01:05 -0500 (Thu, 02 Apr 2009)

Log Message

if a util exited with 0 due to our version check, but the greps werent able to detect "version info", then include that text in the output anyways

Modified Paths

Diff

Modified: trunk/buildscript/BuildToolChain (3311 => 3312)

--- trunk/buildscript/BuildToolChain 2009-04-02 13:52:41 UTC (rev 3311) +++ trunk/buildscript/BuildToolChain 2009-04-02 14:01:05 UTC (rev 3312) <at> <at> -354,9 +354,13 <at> <at> continue fi + VER_ok="" for VER in --version -version -V do - tmp=`$file $VER < /dev/null 2>&1 | grep -ie "version " | grep -vi "option" | grep -vi "Usage" | grep -vi "\-v"` + if tmp=`$file $VER < /dev/null 2>&1` ; then + VER_ok=$tmp + fi + tmp=$(echo "$tmp" | grep -ie "version " | grep -vi -e "option" -e "Usage" -e "\-v") if [ -n "$tmp" ] ; then echo " " $tmp break <at> <at> -366,7 +370,7 <at> <at> continue fi file=$(which $file) - echo "** Looking up file $file for more info" + echo "** Looking up file $file for more info${VER_ok:+ ($VER_ok)}" while [ -L "$file" ] ; do printf " * " file $file 
<div>

<div>
Revision <a href="http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&amp;path=/&amp;view=rev&amp;root=toolchain&amp;revision=3312">3312</a>
Author <a href="http://blackfin.uclinux.org/gf/user/vapier/">vapier</a>
Date 2009-04-02 09:01:05 -0500 (Thu, 02 Apr 2009)
<h3>Log Message</h3>
if a util exited with 0 due to our version check, but the greps werent able to detect "version info", then include that text in the output anyways

<h3>Modified Paths</h3>
<ul>
<li><a href="#trunkbuildscriptBuildToolChain">trunk/buildscript/BuildToolChain</a></li>
</ul>
</div>
<div>
<h3>Diff</h3>
<a></a>
<div class="modfile">
<h4>Modified: trunk/buildscript/BuildToolChain (3311 =&gt; 3312)</h4>
<span>
<span class="info">--- trunk/buildscript/BuildToolChain	2009-04-02 13:52:41 UTC (rev 3311)
+++ trunk/buildscript/BuildToolChain	2009-04-02 14:01:05 UTC (rev 3312)
</span><span class="lines"> <at>  <at>  -354,9 +354,13  <at>  <at> 
</span><span class="cx">                 continue
</span><span class="cx">             fi
</span><span class="cx"> 
</span>+            VER_ok=""
<span class="cx">             for VER in --version -version -V
</span><span class="cx">             do
</span>-                tmp=`$file $VER &lt; /dev/null 2&gt;&amp;1 | grep -ie "version " | grep -vi "option" | grep -vi "Usage" | grep -vi "\-v"`
+                if tmp=`$file $VER &lt; /dev/null 2&gt;&amp;1` ; then
+                    VER_ok=$tmp
+                fi
+                tmp=$(echo "$tmp" | grep -ie "version " | grep -vi -e "option" -e "Usage" -e "\-v")
<span class="cx">                 if [ -n "$tmp" ] ; then
</span><span class="cx">                     echo "  " $tmp
</span><span class="cx">                     break
</span><span class="lines"> <at>  <at>  -366,7 +370,7  <at>  <at> 
</span><span class="cx">                 continue
</span><span class="cx">             fi
</span><span class="cx">             file=$(which $file)
</span>-            echo "** Looking up file $file for more info"
+            echo "** Looking up file $file for more info${VER_ok:+ ($VER_ok)}"
<span class="cx">             while [ -L "$file" ] ; do
</span><span class="cx">                 printf " * "
</span><span class="cx">                 file $file
</span></span>
</div>
</div>

</div>
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Bernd Schmidt | 2 Apr 2009 17:05
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Re: [3274] branches/toolchain_09r1_branch: Fix bug [#5000].

Jie Zhang wrote:
> Bernd Schmidt wrote:
>> jiez@... wrote:
>>> Revision
>>>     3274
>>>     
>>>
<http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/?action=browse&path=/&view=rev&root=toolchain&revision=3274> 
>>>
>>> Author
>>>     jiez <http://blackfin.uclinux.org/gf/user/jiez/>
>>> Date
>>>     2009-03-22 23:11:17 -0500 (Sun, 22 Mar 2009)
>>>
>>>
>>>       Log Message
>>>
>>> Fix bug [#5000] <http://blackfin.uclinux.org/gf/tracker/5000>. Move 
>>> C++ header files to a place where the libstdc++ test
>>> "abi/header_cxxabi.c" expects.
>>
>> It turns out that this makes RPM packaging a bit harder.  Do we really 
>> need this, or can we fix the testcase?
>>
> Fixing the testcase seems more difficult. We may need a 
> --print-include-dirs option to GCC as said in libstdc++.exp.

Hmm.  I'll probably decide to ignore the problem and build the next RPM 
with this patch reverted.

Bernd
--

-- 
This footer brought to you by insane German lawmakers.
Analog Devices GmbH      Wilhelm-Wagenfeld-Str. 6      80807 Muenchen
Sitz der Gesellschaft Muenchen, Registergericht Muenchen HRB 40368
Geschaeftsfuehrer Thomas Wessel, William A. Martin, Margaret Seif
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Gmane