Re: bf561 / SMP-like patch
The attachment is a patch to add irq affinity to SMP. This patch
should be applied on top of the patch I submitted on 21Jan08
(patch.Smp.2007R1.1-RC3.git). That earlier patch was a refactoring
of the SMP patch for 2007R1.1.
This patch uses the PROG{0,1,2}_INTB interrupts to control which PF
pin interrupts go to coreB while the PROG{0,1,2}_INTA interrupts
control those that go to coreA. This creates a conflict with the PM
facility which uses the PROG{0,1,2}_INTB interrupts to wake up the
processor. This patch uses a config variable BFIN_IRQ_AFFINITY to
control whether the irq affinity code is active so that it can be
disabled when the PM facility is needed.
This patch also corrects what I believe to be a typo in the routine
platform_secondary_init in the file arch/blackfin/mach-bf561/smp.c.
A comment at the top of that routine indicates that it clones
registers from coreA to coreB. However it just copies the registers
SICB_IAR{0-9} onto themselves. This patch changes that code to copy
from the registers SICA_IAR{0-9} to the corresponding register in the
set SICB_IAR{0-9}.
-bob
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