Brian Norris | 28 Feb 11:13 2015

[PATCH 0/5] mtd: nand: misc BBT fixes

A few assorted changes. Some of these are geared toward refactoring the BBT
code for being reused for SPI NAND.

If possible, I'd really like to get some testing for the diskonchip changes.
It's an old driver, but it appears as if some still use it. Perhaps Alexander
(CC'd) can report?

Brian Norris (5):
  mtd: nand_bbt: drop unnecessary header
  mtd: diskonchip: don't call nand_scan_bbt() directly
  mtd: nand_bbt: make nand_scan_bbt() static
  mtd: nand_bbt: unify/fix error handling in nand_scan_bbt()
  mtd: nand_bbt: fix theoretical integer overflow in BBT write

 drivers/mtd/nand/diskonchip.c | 27 ++++++++++++++++-----------
 drivers/mtd/nand/nand_bbt.c   | 24 ++++++++++++++----------
 include/linux/mtd/nand.h      |  1 -
 3 files changed, 30 insertions(+), 22 deletions(-)



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Brian Norris | 28 Feb 11:04 2015

[PATCH] mtd: nand: fix spelling of REPLACEABLE

Signed-off-by: Brian Norris <computersforpeace <at>>
 drivers/mtd/nand/nand_base.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d4cec2f8a016..ff5652211607 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
 <at>  <at>  -2124,7 +2124,7  <at>  <at>  static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

- * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
+ * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
  *  <at> mtd:	mtd info structure
  *  <at> chip:	nand chip info structure
  *  <at> offset:	column address of subpage within the page


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Brian Norris | 28 Feb 10:25 2015

[PATCH] Documentation: devicetree: fix spelling in pxa3xx-nand binding

Signed-off-by: Brian Norris <computersforpeace <at>>
 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
index de8b517a5521..4f833e3c4f51 100644
--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
 <at>  <at>  -14,7 +14,7  <at>  <at>  Optional properties:
  - marvell,nand-enable-arbiter:	Set to enable the bus arbiter
  - marvell,nand-keep-config:	Set to keep the NAND controller config as set
 				by the bootloader
- - num-cs:			Number of chipselect lines to usw
+ - num-cs:			Number of chipselect lines to use
  - nand-on-flash-bbt: 		boolean to enable on flash bbt option if
 				not present false
  - nand-ecc-strength:           number of bits to correct per ECC step


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Nam Nguyen | 27 Feb 00:30 2015

Unbounded update to a UBI volume

Hello list,

The argument to IOCVOLUP is the size of the update.  In case of an
update from a stream, such as from a BZip'ed source, this size is
often not known ahead of time.  Is there a way to programmatically
clear the update marker, without having to pad the volume up to its
size, hence saving unnecessary writes?


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punnaiah choudary kalluri | 25 Feb 16:44 2015

[RFC] How to configure nand address cycles in a generic way


  We are using pl353 smc controller in our zynq soc and currently the
patches for this driver
are under review. Till now we have tested various nand parts (micron
and spansion)
and all these devices require five address cycles for read/write
operations (3 row and 2 column address cycles).Even in our driver the
address cycles value is hard coded to five.

   Recently we come across testing the new part i.e Spansion S34ML01G
and this devices requires four address cycles( 2 row and 2 column
cycles) so, now we want to generalize this by reading the address
cycles information from the onfi parameter page.

 I see that the controller driver can retrieve the address cycles
information from the nand_onfi_params structure. But the number of
address cycles to be configured is different for different commands.
 Page read/write operation: row + col address cycles
 Block erase                    : row address cycles
 onfi parameter page         : one address cycles.

Currently in our driver we are reading the address cycles information
from the nand_onfi_params structure and deriving the required address
cycles based on the given command. Ideally this information should
come from the nand core. So, one way i thought that the core should
pass the
required address cycles using the cmdfuncion as below. so the
controller driver can blindly program this information to the
(Continue reading)

Brian Norris | 23 Feb 22:07 2015

[PATCH] UBI: fix missing brace control flow

commit 0e707ae79ba3 ("UBI: do propagate positive error codes up") seems
to have produced an unintended change in the control flow here.

Completely untested, but it looks obvious.

Caught by Coverity, which didn't like the indentation. CID 1271184.

Signed-off-by: Brian Norris <computersforpeace <at>>
Cc: Dan Carpenter <dan.carpenter <at>>
Should go into 4.0, I expect.

 drivers/mtd/ubi/eba.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index da4c79259f67..16e34b37d134 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
 <at>  <at>  -425,9 +425,10  <at>  <at>  retry:
 					ubi_warn(ubi, "corrupted VID header at PEB %d, LEB %d:%d",
 						 pnum, vol_id, lnum);
 					err = -EBADMSG;
-				} else
+				} else {
 					err = -EINVAL;
+				}
 			goto out_free;
(Continue reading)

Alexander Aronsky | 22 Feb 16:15 2015

Resizing mtd partition

Hi everyone,

I have to resize an existing mtd partition on a NOR flash of an embedded
device (PPC architecture) without losing the data on this partition.

To be more specific, I have /dev/mtd0 and /dev/mtd1 devices on my flash,
and I want to increase the size of the file system mounted on /dev/mtdblock0
at the expense of the one on /dev/mtdblock1. For example, eliminate the
/dev/mtd1 altogether and give the /dev/mtd0 all the available space on the

What is the proper way to do it?

With kind regards,

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James Hilliard | 22 Feb 09:07 2015

MI424WR Rev I Hynix NAND ONFI Error

I've been trying to install an OpenWRT port on an Actiontec MI424WR
Rev I, however some variants of this router use a Hynix NAND chip that
OpenWRT doesn't seem to be able to access. There are other versions of
this router that use a Eon NAND chip which works fine. I've attached
the full boot-log. The stock firmware is the same for both NAND Chips.
My guess is its being detected wrong and may be missing an extended ID
or something along those lines. Any help would be appreciated.
The ID seems to be here in the stock firmware:
I tested up until kernel 3.18 which appears to have the ID here:

The Bad Hynix NAND chip comes up as:
[    0.574220] nand: Could not find valid ONFI parameter page; aborting
[    0.580612] nand: device found, Manufacturer ID: 0xad, Chip ID: 0xf1
[    0.587017] nand: Hynix NAND 128MiB 3,3V 8-bit
[    0.591494] nand: 128MiB, SLC, page size: 2048, OOB size: 64
[    0.597187] Scanning device for bad blocks
[    0.607966] Bad eraseblock 114 at 0x000000e40000
[    0.665416] 4 ofpart partitions found on MTD device orion_nand

While the Eon Nand chip that works comes up as:
[    0.573914] nand: device found, Manufacturer ID: 0x92, Chip ID: 0xf1
[    0.580301] nand: Eon NAND 128MiB 3,3V 8-bit
[    0.584617] nand: 128MiB, SLC, page size: 2048, OOB size: 64
[    0.590310] Scanning device for bad blocks
[    0.624209] 4 ofpart partitions found on MTD device orion_nand
[?1034hbash-3.2$ screen /dev/cu.usbserial 115200
(Continue reading)

Xander Huff | 20 Feb 01:32 2015

[PATCH] Zynq NAND: enable subpage reads and writes

From: Ben Shelton <ben.shelton <at>>

The default 3.10 NAND driver does not support subpage reads or writes
for our device, which causes it not to play nicely with partitions that
have already been formatted with this support.

Acked-by: Jeff Westfahl <jeff.westfahl <at>>
Signed-off-by: Ben Shelton <ben.shelton <at>>
 drivers/mtd/nand/pl353_nand.c | 55 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/mtd/nand/pl353_nand.c b/drivers/mtd/nand/pl353_nand.c
index ee74545..e2a46fc 100644
--- a/drivers/mtd/nand/pl353_nand.c
+++ b/drivers/mtd/nand/pl353_nand.c
 <at>  <at>  -398,6 +398,33  <at>  <at>  static int pl353_nand_read_page_raw(struct mtd_info *mtd,

+ * pl353_nand_read_subpage_raw - [Intern] read raw subpage data without ecc
+ *  <at> mtd:	mtd info structure
+ *  <at> chip:	nand chip info structure
+ *  <at> data_offs:	offset of subpage within the page
+ *  <at> readlen:	data length
+ *  <at> buf:	data buffer
+ *  <at> page:	page number to read
+ *
+ * Return:	Always return zero
+ */
(Continue reading)

Ricard Wanderlof | 19 Feb 09:57 2015

fastmap support in ubinize?

Was flashmap support ever added to ubinize ? I can't see any reference to 
it in the code, unless it is implicit somehow.


Ricard Wolf Wanderlöf                           ricardw(at)
Axis Communications AB, Lund, Sweden  
Phone +46 46 272 2016                           Fax +46 46 13 61 30

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Iwo Mergler | 16 Feb 07:35 2015

UBIFS handling of erased page errors

Hi all,

I've noticed that it is possible for UBIFS to become read-only
after an ECC error when reading an erased page.

This strikes my as odd - the page was erased, so it doesn't
contain important filesystem information. I expected UBI
to deal with this - torture the block, retire it if necessary.

Does this remount behaviour make sense? Could someone give
me an example where remounting read-only would serve a data
integrity purpose under those circumstances?

I have solved the underlying problem for now (see below), but I am
worrying that UBIFS may be a little too trigger-happy with the read-only
remounts. For many real-world applications, a read-only volume is
just as broken as an unmountable one.

Best regards,


P.S.: Details

The background of all this is that I had a customer report a
system failure (UBIFS readonly and unusable). Looking at the log,
the issue was a NAND block with bit errors after erase:

> [   96.830000] UBI warning: ubi_io_read: error -74 (ECC error) while reading 126976 bytes from PEB
(Continue reading)