HARPO PRODUCTION PLC. | 17 Nov 20:48 2014


Dear Sir/Madam.

My name is Lydia Lawson and I am the purchasing officer for HARPO
INTERNATIONAL COMPANY PLC, Kindly view our PO,forward details as regarding
your products for
preview and order confirmation.
We are await your response for further proceedings.

Mrs. Lydia Lawson
Purchase Manager.
134 W 26th Street, Floor 4
New York USA, NY 10001
Phone: (212) 645-1686
Fax: (646) 304-1193.
Attachment (PO.zip): application/zip, 797 KiB
Attachment (Sample-4521.rar): application/rar, 771 KiB
Linux MTD discussion mailing list
Pieter Smith | 13 Nov 22:23 2014

[PATCH 42/56] fs/ubifs: support compiling out splice

Compile out splice support from ubifs when the splice-family of syscalls is not
supported by the system (i.e. CONFIG_SYSCALL_SPLICE is undefined).

Signed-off-by: Pieter Smith <pieter <at> boesman.nl>
 fs/ubifs/file.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c
index b5b593c..76112a9 100644
--- a/fs/ubifs/file.c
+++ b/fs/ubifs/file.c
 <at>  <at>  -1584,8 +1584,8  <at>  <at>  const struct file_operations ubifs_file_operations = {
 	.mmap           = ubifs_file_mmap,
 	.fsync          = ubifs_fsync,
 	.unlocked_ioctl = ubifs_ioctl,
-	.splice_read	= generic_file_splice_read,
-	.splice_write	= iter_file_splice_write,
+	SPLICE_READ_INIT(generic_file_splice_read)
+	SPLICE_WRITE_INIT(iter_file_splice_write)
 	.compat_ioctl   = ubifs_compat_ioctl,


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(Continue reading)

Pieter Smith | 13 Nov 22:23 2014

[PATCH 29/56] fs/jffs2: support compiling out splice

Compile out splice support from jffs2 when the splice-family of syscalls is not
supported by the system (i.e. CONFIG_SYSCALL_SPLICE is undefined).

Signed-off-by: Pieter Smith <pieter <at> boesman.nl>
 fs/jffs2/file.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/jffs2/file.c b/fs/jffs2/file.c
index 64989ca..bb4e88b 100644
--- a/fs/jffs2/file.c
+++ b/fs/jffs2/file.c
 <at>  <at>  -58,7 +58,7  <at>  <at>  const struct file_operations jffs2_file_operations =
 	.mmap =		generic_file_readonly_mmap,
 	.fsync =	jffs2_fsync,
-	.splice_read =	generic_file_splice_read,
+	SPLICE_READ_INIT(generic_file_splice_read)

 /* jffs2_file_inode_operations */


Linux MTD discussion mailing list

Richard Weinberger | 12 Nov 22:11 2014

[PATCH 1/2] mtd-www: UBI: Fastmap: Add a notes section

Add a notes section to clarify that fastmap is an optional
feature and it can happen that a full scan is still done if fastmap
is enabled.

Signed-off-by: Richard Weinberger <richard <at> nod.at>
 doc/ubi.xml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/doc/ubi.xml b/doc/ubi.xml
index 393b27b..4bded98 100644
--- a/doc/ubi.xml
+++ b/doc/ubi.xml
 <at>  <at>  -1269,6 +1269,16  <at>  <at>  where a full scan takes too long. E.g. On 4GiB NAND chips a full scan takes
 several seconds whereas a fast attach needs less than one second.</p>

+<h4><a name="L_fastmap_notes">Notes</a></h4>
+<p>Enabling fastmap does not guarantee that every attach process can be done
+in a fast way. In some situations a full scan is still needed.
+This can happen in two cases, (i) if a power cut occurred while a fastmap was
+written to the flash or (ii) UBI ran out of PEBs while writing the fastmap.
+The latter case can happen if a massive amount of IO errors happen while writing
+and UBI cannot find an usable PEB.

 <h2><a name="L_ubiblock">R/O block devices on top of UBI volumes</a></h2>

(Continue reading)

Graham Moore | 11 Nov 20:41 2014

Re: [V5 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor

On 11/05/2014 09:09 PM, bpqw wrote:
> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
> For Micron SPI NOR flash,enabling or disabling quad I/O protocol is
> controlled
> by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
> When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in quad I/O
> mode.

Hi, I'm having trouble with this patch using a Cadence QSPI controller and
Micron n25q00 part.

I can use quad commands in Extended SPI mode, but I can't make this EVCR Quad
mode work.

The Cadence QSPI Controller has fields to configure the quad transfer, and can
support quad opcode, quad address, and quad data, or some combination.  There
is a chart in the docs which shows the combinations for various read commands.

Problem is, I've tried all of the combinations and all I get is FF with this
EVCR patch.

If I don't set the quad mode in the EVCR, then I can use quad read commands no

Bottom line, with the Cadence QSPI controller, if I use quad commands in
Extended SPI mode, then all good.  If I use this EVCR quad mode, then all bad.

Anybody else have a Cadence QSPI controller and using EVCR quad mode
(Continue reading)

Fabio Estevam | 11 Nov 17:01 2014

[PATCH] mtd: gpmi: Remove noisy error message

mx28evk board has a socket for NAND flash that comes with no NAND flash
populated, and then we get this message on every boot:

[    1.657603] gpmi-nand 8000c000.gpmi-nand: driver registration failed: -19

,which is not very helpful, so get rid of this error message.

Signed-off-by: Fabio Estevam <fabio.estevam <at> freescale.com>
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 959cb9b..1ecf0e3 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
 <at>  <at>  -1828,7 +1828,6  <at>  <at>  static int gpmi_nand_probe(struct platform_device *pdev)
-	dev_err(this->dev, "driver registration failed: %d\n", ret);

 	return ret;


Linux MTD discussion mailing list
(Continue reading)

Brian Norris | 10 Nov 22:06 2014

[PATCH] mtd: cafe_nand: drop duplicate .write_page implementation

This write_page() function is functionally equivalent to the default in
nand_base.c. Its only difference is in subpage programming support,
which cafe_nand.c does not advertise, so the difference is negligible.

Signed-off-by: Brian Norris <computersforpeace <at> gmail.com>
 drivers/mtd/nand/cafe_nand.c | 45 --------------------------------------------
 1 file changed, 45 deletions(-)

diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
index 4e66726da9aa..9a0f45f1d932 100644
--- a/drivers/mtd/nand/cafe_nand.c
+++ b/drivers/mtd/nand/cafe_nand.c
 <at>  <at>  -529,50 +529,6  <at>  <at>  static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 	return 0;

-static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-			uint32_t offset, int data_len, const uint8_t *buf,
-			int oob_required, int page, int cached, int raw)
-	int status;
-	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
-	if (unlikely(raw))
-		status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
-	else
-		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
(Continue reading)

alison_chaiken | 10 Nov 16:54 2014

[PATCH 0/2] mtd: m25p80, spi-nor: Spansion S25FL132K plus fixup

From: Alison Chaiken <alison_chaiken <at> mentor.com>

Add support for new chip and fix-up differences between spi_nor_ids
and m25p_ids created by a5b7616c "mtd: m25p80,spi-nor: Fix module
aliases for m25p80".

Alison Chaiken (1):
  MTD: m25p80: fix inconsistency in m25p_ids compared to spi_nor_ids

Knut Wohlrab (1):
  mtd: m25p80: Add support for serial flash Spansion S25FL132K

 drivers/mtd/devices/m25p80.c  | 10 ++++------
 drivers/mtd/spi-nor/spi-nor.c |  1 +
 2 files changed, 5 insertions(+), 6 deletions(-)



Linux MTD discussion mailing list

Richard Weinberger | 10 Nov 13:35 2014

Re: [RFC/PATCH 0/5 v2] mtd:ubi: Read disturb and Data retention handling

Am 10.11.2014 um 13:07 schrieb Juergen Borleis:
> Hi Richard,
> sorry to jump in so lately:
> Richard Weinberger wrote:
>>> If we ignore read-disturb and don't' scrubb heavily read blocks we will 
>>> have data loss as well. the only difference between the 2 scenarios is
>>> "how long before it happens". Read-disturb wasn't an issue since average
>>> lifespan of a nand device was ~5 years. Read-disturb occurs in a longer
>>> lifespan. that's why it's required now: a need for a "long life nand".
>> Okay, read-disturb will only happen if you read blocks *very* often. Do you
>> have numbers, datasheets, etc...?
> I have made some simple test by reading the first 2048 pages of my NAND in an
> endless loop. Only reading, nothing else (made while the bootloader was run,
> nothing else touches the NAND memory).
> Below a result of my test with a 512 MiB SLC NAND with 2kiB page size and
> 128kiB block size:
> The used NAND controller is able to correct up to 8 flipped bits. After the
> 9th bit is flipped the read returns -74.
> This log is a snapshot after the whole area of the first 4 MiB of the NAND
> were read 201688 times.
>   Page no
>  /    1st bitflip after iteration #
(Continue reading)

Sunny Owo | 9 Nov 11:18 2014

be informed

Re: Transfer of Funds to your nominated account.


This is to inform you that our finance company has been mandated by the Presidency of the Republic of South
Africa to remit your outstanding Funding that is in a suspense deposit account here. We shall remit your
fund in four (4) instrumental phases. The management will also like to Inform you that our remittance
department has been receiving different request from different individuals/companies for the claims
to the funds and a change to the beneficiary status and account details.

Recently there was a formal request by Mr. Edward C. Ringer of Ringer Company, Tampa Bay, Florida for the
change of your account to Terrace Bank through some individuals claiming to be your local
representatives here in South Africa.

The management will like you to send the following information for the successful transfer of your funds
and also to avoid the transfer of your funds into a different nominated account and wrong beneficiary.

The information required from you is listed below:

1) Your full name and address
2) Your banking details where your funds will be transferred.
3) Your telephone and fax number.

You are required to get in touch with Mrs.Vivian Smith who is your payment officer on
(vivian.smith59 <at> gmail.com) for further instructions on how your funds will be transferred.

There is an option if you want the funds to be brought to you in your country then you can advise your payment
officer on that issue.In regards to the present situation, a lot of people are claiming that you gave them
authority over your funds and you are therefore advised in your own interest to cut off all communications
between you and your local representatives to avoid the wrongful transfer of your funds into another
(Continue reading)

Aaron Sierra | 8 Nov 20:11 2014

[PATCH v2] mtd: fsl_upm: Support NAND ECC DTS properties

From: Jordan Friendshuh <jfriendshuh <at> xes-inc.com>

Support the generic nand-ecc-mode and nand-ecc-strength device-tree
properties with the Freescale UPM NAND driver.

This patch preserves the default software ECC mode while adding the
ability to use BCH ECC for larger NAND devices.

Signed-off-by: Jordan Friendshuh <jfriendshuh <at> xes-inc.com>
Signed-off-by: Aaron Sierra <asierra <at> xes-inc.com>
    * Now using ECC mode and strength helpers from of_mtd.h
    * ECC mode and strength checking is more robust

 .../devicetree/bindings/mtd/fsl-upm-nand.txt       |  2 +
 drivers/mtd/nand/Kconfig                           |  1 +
 drivers/mtd/nand/fsl_upm.c                         | 51 +++++++++++++++++++---
 3 files changed, 49 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
index fce4894..a9906f6 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
 <at>  <at>  -18,6 +18,8  <at>  <at>  Optional properties:
 - chip-delay : chip dependent delay for transferring data from array to
 	read registers (tR). Required if property "gpios" is not used
 	(R/B# pins not connected).
+- nand-ecc-mode : as defined by nand.txt ("soft" and "soft_bch", only).
+- nand-ecc-strength : as defined by nand.txt.
(Continue reading)