1 May 2009 03:11
Re: For Chris Radek and John Kasunich
John Kasunich wrote: > John Kasunich wrote: > > >> I'm not going to go through that >> learning curve again just to try to find a bug in proprietary code. >> > > Perhaps that was a bit too dismissive. I'm not going to try to figure > out the code at home by myself, but I am willing to study it at the > workshop in Wichita (assuming you are there). The difference is that > I'll be able to ask you questions. > > The problem is that I won't have the software to change the FPGA code with me at the Fest. But, maybe I can now use the free version of Xilinx Ise that runs under Linux. I'll see about getting that on one of the computers I bring to the fest. But, I think I have already found a potential bug, while trying to write up how it works. The "index pulse seen" logic is totally separate from the "reset count on index pulse" logic, which seems on the surface to be a "really bad idea"! I just can't explain the sensitivity to a specific thread pitch, or the frequency of ocurrence. It looks to me like it should only fail when a VERY rare number of critically timed events happen just so. I have to go over the driver code again, but I think the logic there was that I KNEW, at the time, of this critical timing sensitivity, and so I required the spindle sync to be turned on for so many servo cycles before it was tripped, to be sure the driver couldn't have gotten the pulse seen signal before the reset counter logic had been activated.(Continue reading)
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